EEE433/EEE591 Analog Integrated Circuit Design Dr. Barnaby … · 2019-06-09 · Christopher Smith EEE433/EEE591 Analog Integrated Circuit Design Dr. Barnaby Final Project LDO Design

Christopher Smith

EEE433/EEE591 Analog Integrated Circuit Design

Dr. Barnaby

Final Project

LDO Design

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Table of Contents

I. Project Definition 3

II. Hand Calculations 4

III. Amp Design and Analysis 7

IV. Driver stage 9

V. LDO simulations

(1) Open Loop

(a) DC analysis 11

(b) AC analysis 14

(c) Stability 17

(2) Close Loop

(a) Transient analysis 19

(b) Regulation 23

(c) AC analysis 26

VI. Conclusion 28

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I. Project definition:

The low dropout, or LDO, regulator is similar to a standard voltage regulator, but the LDO

regulator uses a p channel mosfet as its pass transistor. This improves dropout voltage, allowing

for further voltage dip at the input than seen with the standard regulator. The LDO regulator is

an integral component in electronics, making the understanding of its operation important for

any aspiring electrical engineer.

This project consists of the design, simulations, and analysis of a LDO regulator.

Requirements:

CMOS TSMC 0.3μm Process

VDD = 2.5 V

Vref = 1.25 V

Output capacitor = 100 pF

Minimum current = 0.1 mA

Maximum current = 50 mA

Output Regulated Voltage = 2.3 V

Maximum voltage ripple < 5%

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II. Hand Calculations:

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III. Amp Design and Analysis:

For the amplifier sustaining the drive current for the pass transistor, the two stage

operational amplifier was chosen, due to the high gain requirement. This design is similar to

the amplifier seen in lab 4, except the second stage current has been reduced to improve phase

margin. Also, a source follower has been added on the output to reduce the output impedance.

After initial simulation, it was found that ripple during load regulation was a serious

concern with the two stage amplifier, so the channel lengths were reduced to their minimum

value to maximize switching speed. In addition, Cc and Rc were optimized to increase phase

margin.

Simulation 1: Operational Amplifier – DC Node Voltages

Variable wmirr (μm)

wp_in

(μm) wn_in (μm)

wp_amp (μm)

wn_amp (μm)

Idc (μA)

CC (pF)

RC (kΩ)

Value 5.45 2.72 0.79 5.45 1.58 20 1 60

Table 1: Component values as seen in schematic

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Simulation 2: Operational Amplifier – AC Gain and Phase

Simulation 3: Operational Amplifier – Output Swing

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IV. Driver Stage:

As mentioned in the project definition, the pass transistor selected for the LDO regulator is a p

channel mosfet. Simulations were performed to determine the optimum size of the transistor by

sweeping the width while monitoring the source voltage to determine where an output of 2.3V is

produced.

Simulation 4: Driver Stage – DC Node Voltages

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Simulation 5: Driver Stage – Sweep of Transistor Width – 50mA Load Current

Simulation 6: Driver Stage – Sweep of VGS – 0.1mA Load Current

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V. LDO Simulation: 1) Open Loop:

a) DC Analysis:

During DC analysis, it was determined that the width found in the driver stage analysis was not

sufficient to maintain an output voltage of 2.3VDC. Therefore, the width was increased to 1.7 mm to

ensure the output voltage would be consistent across the load current’s full range.

Simulation 7: Open Loop Analysis – DC Node Voltages – 0.1mA load current

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Simulation 8: Open Loop Analysis – DC Node Voltages – 1mA load current


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Load current (mA) Vout (V) VG (V) 0.1 2.31 2.077 1 2.31 1.952

10 2.309 1.75 50 2.306 1.089

Table 2: Open Loop – DC node values

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b) AC Analysis:

Simulation 11: Open Loop Analysis – AC Gain and Phase – 0.1mA load current

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Simulation 12: Open Loop Analysis – AC Gain and Phase – 1mA load current


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Current (mA) Gain (dB) f-3dB (kHz) fT (MHz) PM (deg)

0.1 87.92 21.6 11.13 32.6 1 85.61 35.12 31.21 20.5

10 65.62 30.5 48.83 43.5 50 36.36 41.47 3.759 113.76

Table 3: Open Loop – AC values

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c) Stability:

To find an appropriate CC, the value determined through hand calculations was used. It

was then decreased until the AC response was stable for both max and min load current while keeping the miller cap the dominant pole for the system: CC = 10nF.

Simulation 15: Open Loop Analysis – AC Gain and Phase – 0.1mA load current – 10nF comp cap

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Simulation 15: Open Loop Analysis – AC Gain and Phase – 50mA load current – 10nF comp cap

Current (mA) Gain (dB) f-3dB fT (MHz) PM (deg) Without

compensation 0.1 87.92 21.6 kHz 11.13 MHz 32.6 50 36.36 41.47 kHz 3.759 MHz 113.76

With compensation

0.1 87.92 54.34 Hz 1.251 MHz -83.7 50 36.36 2.756 kHz 87.05 kHz 20.8

Table 3: Open Loop – AC values

The value of the compensation capacitor is dependent on the load current. This creates

instability in amplifier performance, as can be seen in the table above. Only decreasing the capacitor

value to the point where it was no longer the dominant pole reinstated a stable response.

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2) Closed Loop:

a) Transient analysis:

Simulation 15: Closed Loop Analysis – Load Regulation – 0.1mA to 1mA load current

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Simulation 16: Closed Loop Analysis – Load Regulation – 1mA to 10mA load current


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Load - Low to High Load - High to Low

Current (mA) Voltage Ripple (%) Settling time (μs) Voltage Ripple (%) Settling time (μs)

0.1 to 1 1.2 0.88 2.2 0.33

1 to 10 3.8 0.29 7 0.92

10 to 50 4 0.55 7 0.53

0.1 to 10 4 0.25 12.7 0.76

1 to 50 8.6 0.56 14.9 1.24

0.1 to 50 14.7 0.47 15.9 0.81

Table 4: Closed loop – Load regulation values

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b) Regulation:

Simulation 21: Closed Loop Analysis – Supply Regulation – 0.1mA load current

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Simulation 22: Closed Loop Analysis – Supply Regulation – 1mA load current


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Input Voltage - Low to High Input Voltage - High to Low

Current (mA) Voltage Ripple (%) Settling time (μs) Voltage Ripple (%) Settling time (μs)

0.1 1.4 0.59 0.4 0.09

1 1.3 0.60 0.4 1.11

10 1.3 0.59 0.5 1.14

50 2.8 0.58 1.7 1.52

Table 5: Closed loop – Supply regulation values

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c) AC analysis:

Simulation 25: Closed Loop Analysis – AC Gain and Phase – 0.1mA load current

Simulation 25: Closed Loop Analysis – AC Gain and Phase – 1mA load current

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VI. Conclusion:

It can be seen that the hand calculations depart from the simulations, especially for the LDO

calculations. This is largely due to the number of simplifications made in the equations. These

simplifications are small for any individual portion of the regulator, but in aggregate create significant

error. Such a situation shows the necessity for compiling simulations to support initial hand calculations.

Thanks to the small voltage drop of the regulator, the efficiency of this circuit is actually very

high, when compared to circuits using voltage regulators. LDO efficiency equates to 92%.

Overall, the regulator performed as intended. The greatest error found in the simulations was in

output ripple during load regulation. Even with the provisions taken to increase speed and phase

margin, as mentioned in section III, the output ripple was still above 5%. However, it was specified that

exceeding the output ripple constraint would be acceptable, so this error was considered satisfactory.

To improve output ripple, a folded OTA could be used in place of the two stage operational amplifier.

EEE433/EEE591 Analog Integrated Circuit Design Dr. Barnaby … · 2019-06-09 · Christopher Smith EEE433/EEE591 Analog Integrated Circuit Design Dr. Barnaby Final Project LDO Design

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