EECS 150 - Components and Design Techniques for Digital Systems Lec 16 – Arithmetic II (Multiplication) David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://inst.eecs.berkeley.edu/~cs150
31
Embed
EECS 150 - Components and Design Techniques for Digital Systems Lec 16 – Arithmetic II (Multiplication) David Culler Electrical Engineering and Computer.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
EECS 150 - Components and Design
Techniques for Digital Systems
Lec 16 – Arithmetic II (Multiplication)
David CullerElectrical Engineering and Computer Sciences
2s Complement OverflowAdd two positive numbers to get a negative number
or two negative numbers to get a positive number
5 + 3 = -8! -7 - 2 = +7!
0000
0001
0010
0011
1000
0101
0110
0100
1001
1010
1011
1100
1101
0111
1110
1111
+0
+1
+2
+3
+4
+5
+6
+7-8
-7
-6
-5
-4
-3
-2
-1
0000
0001
0010
0011
1000
0101
0110
0100
1001
1010
1011
1100
1101
0111
1110
1111
+0
+1
+2
+3
+4
+5
+6
+7-8
-7
-6
-5
-4
-3
-2
-1
How can you tell an overflow occurred?
2s comp. Overflow Detection
5
3
-8
0 1 1 1 0 1 0 1
0 0 1 1
1 0 0 0
-7
-2
7
1 0 0 0 1 0 0 1
1 1 0 0
1 0 1 1 1
5
2
7
0 0 0 0 0 1 0 1
0 0 1 0
0 1 1 1
-3
-5
-8
1 1 1 1 1 1 0 1
1 0 1 1
1 1 0 0 0
Overflow Overflow
No overflow No overflow
Overflow occurs when carry in to sign does not equal carry out
2s Complement Adder/Subtractor
A - B = A + (-B) = A + B + 1
A B
CO
S
+ CI
A B
CO
S
+ CI
A B
CO
S
+ CI
A B
CO
S
+ CI
0 1
Add/Subtract
A 3 B 3 B 3
0 1
A 2 B 2 B 2
0 1
A 1 B 1 B 1
0 1
A 0 B 0 B 0
Sel Sel Sel Sel
S 3 S 2 S 1 S 0
Overflow
Adders on the Xilinx Virtex
• Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB.
• The arithmetic logic includes an XOR gate and AND gate that allows a 2-bit full adder to be implemented within a slice.
• Cin to Cout delay = 0.1ns, versus 0.4ns for F to X delay. How do we map a 2-bit adder to one slice?
Time / Space (resource) Trade-offs
• Carry select and CLA utilize more silicon to reduce time.
• Can we use more time to reduce silicon?
• How few FAs does it take to do addition?
Bit-serial Adder
• Addition of 2 n-bit numbers:– takes n clock cycles,
– uses 1 FF, 1 FA cell, plus registers
– the bit streams may come from or go to other circuits, therefore the registers may be optional.
• Requires controller– What does the FSM look like? Implemented?
• Final carry out?
• A, B, and R held in shift-registers. Shift right once per clock cycle.
• Reset is asserted by controller.
n-bit shift register
n-bit shift registers
sc
reset
R
FAFF
B
A
lsb
Discussion
• What is sign extension and why does it work?
• Where is addition used in the project?
• Where might you want more powerful arithmetic operations?
Announcements
• Reading: 5.8 (4 pages!)
• Digital Design in the news – from UCB– UC Berkeley is among six universities to be part of the
program started by IBM Corp. and Google Inc. on college campuses to promote computer-programming techniques for clusters of processors known as "clouds". Cloud computing allows computers in remote data centers to run parallel, increasing their processing power. Each company will spend between $20 million and $25 million for hardware, software and services that can be used by computer-science professors and students.