1 EECS 150 - Components and Design Techniques for Digital Systems Lec 04 – Hardware Description Languages / Verilog 9/9-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150
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1 EECS 150 - Components and Design Techniques for Digital Systems Lec 04 – Hardware Description Languages / Verilog 9/9-04 David Culler Electrical Engineering.
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EECS 150 - Components and Design Techniques for Digital Systems
Lec 04 – Hardware Description Languages / Verilog
9/9-04 David Culler
Electrical Engineering and Computer SciencesUniversity of California, Berkeley
• Combinational logic– Describe output as a function of inputs
– Note use of assign keyword: continuous assignment
Output port of a primitive mustbe first in the list of ports
Restriction does not apply tomodules
When is this evaluated?
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2-to-1 mux behavioral description
// Behavioral model of 2-to-1
// multiplexor.
module mux2 (in0,in1,select,out);
input in0,in1,select;
output out;
//
reg out;
always @ (in0 or in1 or select)
if (select) out=in1;
else out=in0;
endmodule // mux2
• Notes:– behavioral descriptions use the
keyword always followed by blocking procedural assignments
– Target output of procedural assignments must of of type reg
(not a real register)
– Unlike wire types where the target output of an assignment may be continuously updated, a reg type retains it value until a new value is assigned (the assigning statement is executed).
– Optional initial statement
Sensitivity list
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Behavioral 4-to1 mux
//Does not assume that we have // defined a 2-input mux.
• Leaving out an input trigger usually results in a sequential circuit
• Example: The output of this “and” gate depends on the input history
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Behavioral with Bit Vectors
• Notes:– inputs, outputs 32-bits wide
//Behavioral model of 32-bitwide 2-to-1 multiplexor.module mux32 (in0,in1,select,out); input [31:0] in0,in1; input select; output [31:0] out; // reg [31:0] out; always @ (in0 or in1 or select) if (select) out=in1; else out=in0;endmodule // Mux
//Behavioral model of 32-bit adder.module add32 (S,A,B); input [31:0] A,B; output [31:0] S; reg [31:0] S; // always @ (A or B) S = A + B;endmodule // Add
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Hierarchy & Bit Vectors
//Assuming we have already // defined a 2-input mux (either// structurally or behaviorally,
always @(A) case (A) 8’b00000001: Y = 0; 8’b00000010: Y = 1; 8’b00000100: Y = 2; 8’b00001000: Y = 3; 8’b00010000: Y = 4; 8’b00100000: Y = 5; 8’b01000000: Y = 6; 8’b10000000: Y = 7; default: Y = 3’bX; // Don’t care when input is not 1-hot endcaseendmodule
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Verilog case (cont)
• Cases are executed sequentially– The following implements a priority encoder
always @(A) case (1’b1) A[0]: Y = 0; A[1]: Y = 1; A[2]: Y = 2; A[3]: Y = 3; A[4]: Y = 4; A[5]: Y = 5; A[6]: Y = 6; A[7]: Y = 7; default: Y = 3’bX; // Don’t care when input is all 0’s endcaseendmodule
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Parallel Case
• A priority encoder is more expensive than a simple encoder– If we know the input is 1-hot, we can tell the synthesis tools– “parallel-case” pragma says the order of cases does not matter
always @(A) case (1’b1) // synthesis parallel-case A[0]: Y = 0; A[1]: Y = 1; A[2]: Y = 2; A[3]: Y = 3; A[4]: Y = 4; A[5]: Y = 5; A[6]: Y = 6; A[7]: Y = 7; default: Y = 3’bX; // Don’t care when input is all 0’s endcaseendmodule
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Verilog casex
• Like case, but cases can include ‘X’– X bits not used when evaluating the cases
– In other words, you don’t care about those bits!
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casex Example
// Priority encodermodule encode (A, valid, Y);input [7:0] A; // 8-bit input vectoroutput [2:0] Y; // 3-bit encoded outputoutput valid; // Asserted when an input is not all 0’sreg [2:0] Y; // target of assignmentreg valid;
always @(A) begin valid = 1; casex (A) 8’bXXXXXXX1: Y = 0; 8’bXXXXXX10: Y = 1; 8’bXXXXX100: Y = 2; 8’bXXXX1000: Y = 3; 8’bXXX10000: Y = 4; 8’bXX100000: Y = 5; 8’bX1000000: Y = 6; 8’b10000000: Y = 7; default: begin valid = 0; Y = 3’bX; // Don’t care when input is all 0’s end endcase endendmodule
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Sequential Logic
• Notes:– “always @ (posedge CLK)” forces Q
register to be rewritten every simulation cycle.
– “>>” operator does right shift (shifts in a zero on the left).
– Shifts on non-reg variables can be done with concatenation:
• Notes:– initial block similar to always except only
executes once (at beginning of simulation)
– #n’s needed to advance time
– $monitor - prints output
– A variety of other “system functions”, similar to monitor exist for displaying output and controlling the simulation.
Top-level modules written specifically to test sub-modules.
Generally no ports.
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Final thoughts
• Verilog looks like C, but it describes hardware– Multiple physical elements, Parallel activities
– Temporal relationships
– Basis for simulation and synthesis
– figure out the circuit you want, then figure out how to express it in Verilog
• Understand the elements of the language– Modules, ports, wires, reg, primitive, continuous assignment,
blocking statements, sensitivity lists, hierarchy
– Best done through experience
• Behavioral constructs hide a lot of the circuit details but you as the designer must still manage the structure, data-communication, parallelism, and timing of your design.