inst.eecs.berkeley.edu/~ee241b Borivoje Nikolić EE241B : Advanced Digital Circuits Lecture 20 – Dynamic Voltage Scaling EECS241B L20 DYNAMIC VOLTAGE SCALING 1 Supreme Court hands Google a victory in a multibillion-dollar case against Oracle By Brian Fung, CNN Business, Mon April 5, 2021 The Supreme Court has handed Google a win in a decade-old case in software development, holding that the technology giant did not commit copyright infringement against Oracle when it copied snippets of programming language to build its Android operating system.
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inst.eecs.berkeley.edu/~ee241b
Borivoje Nikolić
EE241B : Advanced Digital Circuits
Lecture 20 – Dynamic Voltage Scaling
EECS241B L20 DYNAMIC VOLTAGE SCALING 1
Supreme Court hands Google a victory in a multibillion-dollar case against OracleBy Brian Fung, CNN Business, Mon April 5, 2021
The Supreme Court has handed Google a win in a decade-old case in software development, holding that the technology giant did not commit copyright infringement against Oracle when it copied snippets of programming language to build its Android operating system.
Announcements
• Assignment 3 due this week• Quiz next Tuesday
EECS241B L20 DYNAMIC VOLTAGE SCALING 2
Outline
• Power-performance tradeoffs through supply voltage• Multiple supplies
• Maximize Peak Throughput• Minimize Average Energy/operation
System Optimizations:BurdISSCC’00
Processor Usage Model
EECS241B L21 DVS2 20
Compute ASAP:
Deliv
ered
Thr
ough
put
Clock Frequency Reduction:
Excessthroughput
Always high throughput
Energy/operation remains unchanged…while throughput scaled down with fCLK
fCLKReduced
time
time
Common Design Approaches (Fixed VDD)
EECS241B L21 DVS2 21
0
0.5
1
0 0.5 1
Ener
gy/o
pera
tion
Throughput ( fCLK)
Constant supply voltage
Reduce VDD, slowcircuits down.
~10x EnergyReduction
3.3V
1.1V
BurdISSCC’00
Scale VDD with Clock Frequency
∝EECS241B L21 DVS2 22
InverterRingOscRegFileSRAM
1.0
0.5
0VT 2VT 3VT 4VT
Norm
alize
d m
ax. f
CLK
VDD
Delay tracks within +/- 10%BurdISSCC’00
CMOS Circuits Track Over VDD
EECS241B L21 DVS2 23
time
• Dynamically scale energy/operation with throughput.• Always minimize speed → minimize average energy/operation.• Extend battery life up to 10x with the exact same hardware!
Vary fCLK,VDDDe
liver
edTh
roug
hput
1 2 Dynamically adapt
BurdISSCC’00
Dynamic Voltage Scaling (DVS)
EECS241B L21 DVS2 24
• DVS requires a voltage scheduler (VS).• VS predicts workload to estimate CPU cycles.• Applications supply completion deadlines.
0
20
40
60
80
0 0.2 0.4 0.6 1.0 1.2 1.40.8
Processor Speed (MPEG)
F DESI
RED
(MHz
)
Time (sec)
Operating System Sets Processor Speed
DESIREDCPU cycles F
time=
∆
EECS241B L21 DVS2 25
RST Counter
Latch
Digital Loop Filter
L CDD
VDD
PENAB
NENABΣFERR
FMEAS
f1MHz
0110
100 FDES
+Register
fCLK
Ring Oscillator Processor
IDD
• Feedback loop sets VDD so that FERR → 0.• Ring oscillator delay-matched to CPU critical paths.• Custom loop implementation → Can optimize CDD.