inst.eecs.berkeley.edu/~ee241b Borivoje Nikoliü EE241B : Advanced Digital Circuits Lecture 24 – DTS, Clock EECS241B L24 CLOCK The Promise and Pitfalls of Neuromorphic Computers, by Sunny Bains, EE Times, April 22, 2020. https://www.eetimes.com Announcements • Assignment 4 due on Friday. • Quiz on Tuesday • Last lecture on Tuesday • Final on Thursday, April 30 • Project presentations on Monday, May 4 • Reading: Wong, JSSC, 2006 EECS241B L24 CLOCK Outline • Module 5 • Dynamic threshold scaling • Optimal thresholds and supplies • Module 6 • Clock generation EECS241B L24 CLOCK 5.M Dynamic Threshold Scaling EECS241B L24 CLOCK Dynamic Body Bias (Bulk) EECS241B L24 CLOCK Switches between active and sleep ... ... 450mV FBB 450mV FBB V CC V SS PMOS body NMOS body PMOS bias NMOS bias PMOS bias ... ... NMOS bias 500mV RBB 500mV RBB V CC V SS PMOS body NMOS body V HIGH V LOW Forward body bias (FBB) Local V CC tracking Active mode Reverse body bias (RBB) Triple well needed Idle mode Dual-V T core Tschanz, ISSCC’03 Dynamic Body Bias (Bulk) EECS241B L24 CLOCK Body Bias Layout Sleep transistor LBGs Number of ALU core LBGs 30 Number of sleep transistor LBGs 10 PMOS device width 13mm Area overhead 8% ALU core LBGs Sleep transistor LBGs ALU core LBGs ALU EECS241B L24 CLOCK 0% 5% 10% 15% 20% 10 100 1000 10000 100000 1000000 Total Active Power Savings (Fixed activity: D = 0.05) Body bias (1.28V): active: FBB, idle: ZBB Reference: 450mV FBB to core with clock gating, 1.28V, 4.05GHz, 75°C 0.5 5 50 500 5000 50000 Number of consecutive idle cycles (T OFF ) Number of consecutive active cycles (T ON ) Power savings for T OFF > ~100 idle cycles PMOS sleep transistor (1.32V) Total power savings Max 18% Max 8% EECS241B L24 CLOCK
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inst.eecs.berkeley.edu/~ee241b
Borivoje Nikoli
EE241B : Advanced Digital Circuits
Lecture 24 – DTS, Clock
EECS241B L24 CLOCK
The Promise and Pitfalls of Neuromorphic Computers, by Sunny Bains, EE Times, April 22, 2020.
https://www.eetimes.com
Announcements
• Assignment 4 due on Friday.• Quiz on Tuesday
• Last lecture on Tuesday
• Final on Thursday, April 30
• Project presentations on Monday, May 4
• Reading: Wong, JSSC, 2006
EECS241B L24 CLOCK
Outline
• Module 5• Dynamic threshold scaling
• Optimal thresholds and supplies
• Module 6• Clock generation
EECS241B L24 CLOCK
5.M Dynamic Threshold Scaling
EECS241B L24 CLOCK
Dynamic Body Bias (Bulk)
EECS241B L24 CLOCK
Switches between active and sleep
... ...
450mVFBB
450mVFBB
VCC
VSS
PMOSbody
NMOSbody
PMOSbias
NMOSbias
PMOSbias ... ...
NMOSbias
500mVRBB
500mVRBB
VCC
VSS
PMOSbody
NMOSbody
VHIGH
VLOW
Forward body bias (FBB)
Local VCC tracking
Active mode
Reverse body bias (RBB)
Triple well needed
Idle mode
Dual-VTcore
Tschanz, ISSCC’03
Dynamic Body Bias (Bulk)
EECS241B L24 CLOCK
Body Bias Layout
Sleep transistor LBGs
Number of ALU core LBGs 30
Number of sleep transistor LBGs 10
PMOS device width 13mm
Area overhead 8%
ALU core LBGs
Sleep transistor LBGsALU core LBGs
ALU
EECS241B L24 CLOCK
0%
5%
10%
15%
20%
10 100 1000 10000 100000 1000000Number of idle cycles
Tota
l pow
er s
avin
gs
Total Active Power Savings(Fixed activity: = 0.05)
Body bias (1.28V): active: FBB, idle: ZBB
Reference: 450mV FBB to core with clock gating, 1.28V, 4.05GHz, 75°C
0.5 5 50 500 5000 50000
Number of consecutive idle cycles (TOFF)
Number of consecutive active cycles (TON)
Power savings for TOFF > ~100 idle cycles
PMOS sleep transistor (1.32V)
Tota
l pow
er s
avin
gs Max 18%
Max 8%
EECS241B L24 CLOCK
Generating Back-Bias
• Tradeoff – speed of charging and discharging well caps
• Often measure VBB indirectly (leakage)
• Challenge: Generating –VSS
• 28nm FDSOI implementation
D. Jacquet, VLSI 2013
EECS241B L24 CLOCK
Generating Back Bias
• Fast and wide voltage range back-bias in FDSOI
M. Blagojevic, VLSI 2016
Switched capacitors generate negative bias and pump substrate
chN
dchN
chP
dchP
nwell
pwell
VDD1V8
GND
GND
Neg.BootStrap
Neg.BootStrap
VDD1V8
GND
GND
1
1
2
2
Cfly
pwellCharger
pwellDischarger
nwellCharger
nwellDischarger
LEVEL
SHIFT
VDD1V0VDD1V8
LEVEL
SHIFT
VDD1V0VDD1V8
EECS241B L24 CLOCK
Supply/Process Compensation
• Able to track ~200mV supply droops and maintain constant frequency (measured by a replica) by back-bias adjustments
EECS241B L24 CLOCK
5.N Dynamic Threshold Scaling and Variations
EECS241B L24 CLOCK
Body Biasing and Variations
• Body biasing with a local control loop can be used to lower the impact of process variations
• Used to limit die-to-die and within-die variations
EECS241B L24 CLOCK
Self-Adjusting Threshold-Voltage Scheme (SATS)
• Older bulk technologies had stronger body effect