EE141 1 EE141 EE141-Spring 2008 Spring 2008 Digital Integrated Digital Integrated Circuits Circuits Circuits Circuits Lecture 8 Lecture 8 EE141 EECS141 1 Lecture #8 Inverter Delay and Power Inverter Delay and Power Announcements Announcements Homework #3 due today Homework #4 posted today, due next Fr Midterm1 Friday February 29 6:00- 7:30pm Open book EE141 EECS141 2 Lecture #8 Will cover Lecture 1-8 (not including power)
17
Embed
EE141EE141--Spring 2008Spring 2008 Digital Integrated Circuits
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
EE141
1
EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuits
Lecture 8Lecture 8
EE141EECS141 1Lecture #8
Inverter Delay and PowerInverter Delay and Power
AnnouncementsAnnouncements
Homework #3 due todayHomework #4 posted today, due next FrMidterm1 Friday February 29 6:00-7:30pm
Open book
EE141EECS141 2Lecture #8
Will cover Lecture 1-8 (not including power)
EE141
2
Class MaterialClass MaterialLast lecture
MOS capacitancesToday’s lecture
Inverter delayPower dissipation
EE141EECS141 3Lecture #8
Reading (3.3.2, 5.4, 5.5)
Simplified ModelSimplified ModelCapacitance models important for analysis and intuition
– But often need something simpler to work withSimpler model:
– Lump together as effective linear capacitance to (ac) ground
– In most processes: Cg = Cd = 1.5 – 2fF·W(µm)
EE141EECS141 4Lecture #8
VoutVin
CL
VoutVin
EE141
3
Review Review –– MOS CapacitancesMOS Capacitances
EE141EECS141 5Lecture #8
The Miller EffectThe Miller Effect
Cgd1VoutΔV
As Vin increases, Vout drops – Once get into the transition region, gain
from V to V > 1Vin
M1
ΔVfrom Vin to Vout > 1
So, Cgd experiences voltage swing larger than Vin
– Which means you need to provide more charge
– Makes Cgd look larger than it really is
EE141EECS141 6Lecture #8
Known as the “Miller Effect” in the analog world
EE141
4
Review Review –– MOS CapacitancesMOS Capacitances
EE141EECS141 7Lecture #8
Review Review –– MOS CapacitancesMOS Capacitances
EE141EECS141 8Lecture #8
EE141
5
Model CalibrationModel Calibration -- CapacitanceCapacitanceCan calculate Cg, Cd based on tech. parameters
But these models are simplified too– But these models are simplified tooAnother approach:
– Tune (e.g., in spice) the linear capacitance until it makes the simplified circuit match the real circuit
– Matching could be for delay, power, etc.
EE141EECS141 9Lecture #8
CloadDelay1 Delay2Match
Model CalibrationModel Calibration for Delayfor DelayA
For gate capacitance:– Make inverter fanout 4 (will see why in 2 lectures)
Adjust C until Delay1 = Delay2
CloadDelay1 Delay2Match
EE141EECS141 10Lecture #8
– Adjust Cload until Delay1 = Delay2For diffusion capacitance
– Replace inverter “A” with a diffusion capacitance load
EE141
6
Delay CalibrationDelay Calibration1 4 16 64
Why did we need that last inverter stage?
Delay
"Edge Shaper" Load ???
EE141EECS141 11Lecture #8
Propagation DelayPropagation Delay
EE141EECS141 12Lecture #8
EE141
7
3
Transient ResponseTransient Response
1
1.5
2
2.5
Vou
t(V)
tpHL = ln(2) CL ReqntpLH = ln(2) CL Reqp
tpHLtpLH
EE141EECS141 13Lecture #8
0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
t (sec)
( )1 1
2ln(2) 1
with '
=+
⎛ ⎞= − −⎜ ⎟
⎝ ⎠2
DDeq
DD DSAT
DS,effDSAT DD T DS,eff
VRλV I
VWI k V V VL
Delay as a function of VDelay as a function of VDDDD