EE141 1 gital Integrated Circuits 2nd Combinational Circu Combinatorial Logic Circuits
EE141 1© Digital Integrated Circuits2ndCombinational Circuits
Combinatorial Logic Circuits
EE141 2Adapted from © Digital Integrated Circuits2nd
Index
Basic CMOS gates: Properties Ratioed Logic Pass transistor Logic Dynamic Logic
EE141 3Adapted from © Digital Integrated Circuits2nd
Combinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
EE141 4Adapted from © Digital Integrated Circuits2nd
Static CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
EE141 5Adapted from © Digital Integrated Circuits2nd
Static Complementary CMOS
VDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
……
F(In1,In2,…InN)=1 produce F=Vdd
F(In1,In2,…InN)=0 produce F=GND
EE141 6Adapted from © Digital Integrated Circuits2nd
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
EE141 7Adapted from © Digital Integrated Circuits2nd
PMOS Transistors in Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
EE141 8Adapted from © Digital Integrated Circuits2nd
Complementary CMOS Logic Style
EE141 9Adapted from © Digital Integrated Circuits2nd
Example Gate: NAND
EE141 10Adapted from © Digital Integrated Circuits2nd
Example Gate: NOR
EE141 11Adapted from © Digital Integrated Circuits2nd
Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
EE141 12Adapted from © Digital Integrated Circuits2nd
Constructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
EE141 13Adapted from © Digital Integrated Circuits2nd
Cell Design
Standard Cells General purpose logic Can be synthesized Same height, varying width
Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width
EE14114
© Digital Integrated Circuits2ndCombinational CircuitsAdapted from © Digital Integrated Circuits2nd
Standard Cell Layout Methodology – 1980sStandard Cell Layout Methodology – 1980s
signals
Routingchannel
VDD
GND
EE14115
© Digital Integrated Circuits2ndCombinational CircuitsAdapted from © Digital Integrated Circuits2nd
Standard Cell Layout Methodology – 1990sStandard Cell Layout Methodology – 1990s
M2
No Routingchannels
VDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
EE14116
© Digital Integrated Circuits2ndCombinational CircuitsAdapted from © Digital Integrated Circuits2nd
Standard CellsStandard Cells
Cell boundary
N Well
Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objects
Cell height is “12 pitch”
2
Rails ~10
InOut
VDD
GND
EE14117
© Digital Integrated Circuits2ndCombinational CircuitsAdapted from © Digital Integrated Circuits2nd
Standard CellsStandard Cells
A
Out
VDD
GND
B
2-input ??? gate
EE14118
© Digital Integrated Circuits2ndCombinational CircuitsAdapted from © Digital Integrated Circuits2nd
Stick DiagramsStick Diagrams
Contains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
EE141 19Adapted from © Digital Integrated Circuits2nd
Stick Diagrams
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
EE14120
© Digital Integrated Circuits2ndCombinational CircuitsAdapted from © Digital Integrated Circuits2nd
Two Versions of C • (A + B)Two Versions of C • (A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
Permutation of input signals that produce uninterrupted active strips is important !
EE141 21Adapted from © Digital Integrated Circuits2nd
Euler Paths
There is a systematic approach to uninterrupted strips of active. Two steps:
Step 1: Construction of logic graph Step 2: Identification of Euler graphs
Euler path is a path through all nodes such that every edge is visited once.
Euler path is equivalent to an uninterrupted A-strip (succesive S and D connections)
Consistency: Same ordering for PUN and PDN
EE141 22Adapted from © Digital Integrated Circuits2nd
Euler Path
j
VDDX
X
i
GND
AB
C
A B C
Node
Edge = Transistor
EE141 23Adapted from © Digital Integrated Circuits2nd
OAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
EE141 24Adapted from © Digital Integrated Circuits2nd
Example: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}
b
EE141 25Adapted from © Digital Integrated Circuits2nd
CMOS Gates
Static Properties of gates Delay characteristics Fan-in and Fan-out considerations
EE141 26Adapted from © Digital Integrated Circuits2nd
Static Properties
Depend on input pattern
0V 3V
3V
0V
Vin
Vout
a) A=B=0 → 1
b) A=1, B=0 → 1 c) B=1, A=0 → 1
a) Two pull-up transistors in parallel are more difficult to turn off than oneb) One pull-up transistor, one pull-down. Dynamically, the internal node has
to be discharged (slower)c) Vds1 produces bulk effect during discharge. More Vin is needed
EE141 27Adapted from © Digital Integrated Circuits2nd
Switch Delay Model
A
Req
A
Rp
A
Rp
A
Rn CL
A
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND2 INVNOR2
EE141 28Adapted from © Digital Integrated Circuits2nd
Input Pattern Effects on Delay
Delay is dependent on the pattern of inputs
Low to high transition both inputs go low
delay is 0.69 Rp/2 CL
one input goes low delay is 0.69 Rp CL
when N transistor A goes off, internal node has to be charged
High to low transition both inputs go high
delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
EE141 29Adapted from © Digital Integrated Circuits2nd
Delay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=10
A=1, B=10
A=1 0, B=1
time [ps]
Vo
ltage
[V]
Input DataPattern
Delay(psec)
A=B=01 67
A=1, B=01 64
A= 01, B=1 61
A=B=10 45
A=1, B=10 80
A= 10, B=1 81
NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF
when N transistor A goes off, internal node has to be charged (slower)
EE141 30Adapted from © Digital Integrated Circuits2nd
Transistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
11
4
4
NAND based implementations are preferred over NOR …
EE141 31Adapted from © Digital Integrated Circuits2nd
Transistor Sizing a Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
EE141 32Adapted from © Digital Integrated Circuits2nd
Fan-In Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model (Elmore delay)
tpHL = 0.69 Re (C1+2C2+3C3+4CL) = Re C1+2 Re C2+3Re C3+4Re CL
* Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. (prop. to R×C)
* Internal nodes important !!
EE141 33Adapted from © Digital Integrated Circuits2nd
tp as a Function of Fan-In
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
tpLH
t p (
pse
c)
fan-in
Gates with a fan-in greater than 4 should be avoided.
Intrinsec C increases linearly
Series transistors cause a double slowdown
Parallel transistors increase C
EE141 34Adapted from © Digital Integrated Circuits2nd
tp as a Function of Fan-Out
2 4 6 8 10 12 14 16
tpNOR2
t p (
pse
c)
eff. fan-out
All gates have the same drive current.
tpNAND2
tpINV
Slope is a function of “driving strength”
EE141 35Adapted from © Digital Integrated Circuits2nd
tp as a Function of Fan-In and Fan-Out
Fan-in: quadratic due to increasing resistance and capacitance
Fan-out: each additional fan-out gate adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
EE141 36Adapted from © Digital Integrated Circuits2nd
Fast Complex Gates: Design Technique 1
Transistor sizing as long as fan-out capacitance dominates
Progressive sizing
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MN
Distributed RC line
M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest)Lower caps see smaller RCan reduce delay by more than 20%; decreasing gains as technology shrinks
EE141 37Adapted from © Digital Integrated Circuits2nd
Fast Complex Gates: Design Technique 2
Transistor ordering Transistor with more activity or with latest changes on
top
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
01charged
charged1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
1
1
01 charged
discharged
discharged
EE141 38Adapted from © Digital Integrated Circuits2nd
Fast Complex Gates: Design Technique 3
Alternative logic structures
F = ABCDEFGH
There are techniques to minimize switching time: logical effort
EE141 39Adapted from © Digital Integrated Circuits2nd
Fast Complex Gates: Design Technique 4
Isolating fan-in from fan-out using buffer insertion
CLCL
EE141 40Adapted from © Digital Integrated Circuits2nd
Fast Complex Gates: Design Technique 5
Reducing the voltage swing
linear reduction in delay (only when variation of Req is not substantial; after this, delay gets worse)
also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the
receiving end to restore the signal level (memory design)
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
EE141 41Adapted from © Digital Integrated Circuits2nd
Stages with general logic
What happens in the general case: no longer inverters
Suppose we drive a load using a non-inverter stage We increase the transistors by a factor g so
that we have the same driving as the inverter (per input)
The input capacitance is g times bigger
int int int
/
p eq L eq
p eq INV INV po
t kR C C kR C fC
t kR gC fgC t p g f
there’s more than one inputtpo is the intrinsic time of a min. size inv.
EE141 42Adapted from © Digital Integrated Circuits2nd
Logical Effort
/0 fgptt pp
f – effective fanout
p – intrinsic delay factor (multiple times of the inverter intrinsic delay)g – logical effort (ratio of its input capacitance to the inverter capacitance when sized to deliver the same current). Increases with gate complexity. Depends only on topology
EE141 43Adapted from © Digital Integrated Circuits2nd
Logical Effort
Logical effort quantifies how much less driving strength a gate has compared to an inveter
g = 1 g = 4/3 g = 5/3
B
A
A B
F
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
2
1 1
4
4
Inverter 2-input NAND 2-input NOR
EE141 44Adapted from © Digital Integrated Circuits2nd
Intrinsic delay factors
Gate Type P
Inverter 1
N-input NAND N
N-input NOR N
N-way mux 2 N
XOR, NXOR N 2^(N-1)
EE141 45Adapted from © Digital Integrated Circuits2nd
Logical Effort of Gates
Fan-out (h)
Nor
mal
ized
del
ay (
d)
t
1 2 3 4 5 6 7
pINVt pNAND
F(Fan-in)
g = 1p = 1d = h+1
g = 4/3p = 2d = (4/3)h+2
EE141 46Adapted from © Digital Integrated Circuits2nd
Logical Effort of Gates
IntrinsicDelay
EffortDelay
1 2 3 4 5
Fanout f
1
2
3
4
5 Inverter:P=1; g=1
2-input NAND:p=2; g=4/3
EE141 47Adapted from © Digital Integrated Circuits2nd
Stage effort: hi = gifi
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay
Multistage Networks
BfF i /
N
iiiip fgptDelay
10
N
iiip hptD
10
EE141 48Adapted from © Digital Integrated Circuits2nd
Add Branching Effort
Branching effort:
pathon
pathoffpathon
C
CCb
EE141 49Adapted from © Digital Integrated Circuits2nd
Optimum Effort per Stage
HhN
When each stage bears the same effort:
N Hh
Effective fanout of each stage: ii ghf
Stage efforts: g1f1 = g2f2 = … = gNfN
EE141 50Adapted from © Digital Integrated Circuits2nd
Sizing
After the fi’s have been obtained, the sizing factors si’s are calculated starting from the first one:
The others are obtained iteratively
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
EE141 51Adapted from © Digital Integrated Circuits2nd
Example: Optimize Path
g = 1f = a
g = 5/3f = b/a
g = 5/3f = c/b
g = 1f = 5/c
1a
b c
5
EE141 52Adapted from © Digital Integrated Circuits2nd
EE141 53Adapted from © Digital Integrated Circuits2nd
Example – 8-input AND
EE141 54Adapted from © Digital Integrated Circuits2nd
Sutherland,SproullHarris
Summary
EE141 55© Digital Integrated Circuits2ndCombinational Circuits
Ratioed Logic
EE141 56Adapted from © Digital Integrated Circuits2nd
Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
EE141 57Adapted from © Digital Integrated Circuits2nd
Ratioed Logic
VDD
VSS
PDN
In1
In2
In3
F
RLLoad
ResistiveN transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
EE141 58Adapted from © Digital Integrated Circuits2nd
Active Loads
VDD
VSS
In1In2In3
F
VDD
VSS
PDN
In1In2In3
F
VSS
PDN
Depletion
LoadPMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
EE141 59Adapted from © Digital Integrated Circuits2nd
Pseudo-NMOS
VDD
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
kn VDD VTn– VOL
VOL2
2-------------–
kp
2------ VDD VTp– 2=
VOL VDD VT– 1 1kpkn------–– (assuming that VT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
EE141 60Adapted from © Digital Integrated Circuits2nd
Pseudo-NMOS VTC
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5
1.0
1.5
2.0
2.5
3.0
Vin [V]
Vou
t [V
]
W/Lp = 4
W/Lp = 2
W/Lp = 1
W/Lp = 0.25
W/Lp = 0.5
The bigger P, the fastest the L to H transition, but more power and higher Vol
i
vVOL V’OL
EE141 61Adapted from © Digital Integrated Circuits2nd
Performance of a P-NMOS inverter
Size Vol Static P Tplh
4 0.693 564W 14 ps
2 0.273 298 W 56 ps
1 0.133 160 W 123 ps
½ 0.064 80 W 268 ps
1/4 0.031 41 W 569 ps
EE141 62Adapted from © Digital Integrated Circuits2nd
Improved Loads (2)
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
EE141 63Adapted from © Digital Integrated Circuits2nd
DCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0-0.5
0.5
1.5
2.5
Time [ns]
Vol
tage
[V] A B
A B
A,BA,B
B
A A
B B B
Out
Out
XOR-NXOR gate
A BA B
EE141 64© Digital Integrated Circuits2ndCombinational Circuits
Pass-TransistorLogic
EE141 65Adapted from © Digital Integrated Circuits2nd
Pass-Transistor LogicIn
puts
Switch
Network
OutOut
A
B
B
B
• N transistors
• No static consumption
EE141 66Adapted from © Digital Integrated Circuits2nd
Example: AND Gate
Bottom ensures low impedance path
B=1 and A=1 produces a weak 1 ouput Worsened by body
effect Fewer gates
Smaller capacitance
B
B
A
F = AB
0
EE141 67Adapted from © Digital Integrated Circuits2nd
NMOS-Only Logic
VDD
In
Outx
0.5m/0.25m0.5m/0.25m
1.5m/0.25m
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time [ns]
Vo
ltage
[V]
xOut
In
Tail end of transient very slow due to the small current available
EE141 68Adapted from © Digital Integrated Circuits2nd
Series cascade
EE141 69Adapted from © Digital Integrated Circuits2nd
NMOS-only Switch
A = 2.5 V
B
C = 2.5 V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Vb does not pull up to 2.5V, but to 2.5V - VtnThreshold voltage loss causes static power consumptionNMOS has higher threshold than PMOS (body effect)
EE141 70Adapted from © Digital Integrated Circuits2nd
NMOS Only Logic: Level Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem: Mn has to be able to pull down node X from Vdd to GND
EE141 71Adapted from © Digital Integrated Circuits2nd
Restorer Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
W/Lr =1.50/0.25
W/Lr =1.75/0.25
Vol
tage
[V]
Time [ps]
3.0
• Upper limit on restorer size• Pass-transistor pull-downcan have several transistors in stack• Fall time is accelerated, rise is slowed down
Transistor Mn is fixed and size of Feedback (Mr) is increased (Switching threshold of inverter is mid-rail).
EE141 73Adapted from © Digital Integrated Circuits2nd
Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=AÝ
F=AÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
EE141 74Adapted from © Digital Integrated Circuits2nd
Complementary Pass Transistor Logic
Complementary data inputs and outputs are always available
Output are always connected to low-impedance
Design is very modular. The same topology is used. Permutation of inputs is used.
Complementary signals have to be routed Restorer has to be used, otherwise static
consumption
EE141 75Adapted from © Digital Integrated Circuits2nd
Solution 3: Transmission Gate
A B
C
C
A B
C
C
B
CL
C = 0 V
A = 2.5 V
C = 2.5 V
EE141 76Adapted from © Digital Integrated Circuits2nd
Pass-Transistor Based Multiplexer
AM2
M1
B
S
S
S F
VDD
GND
VDD
In1
In2
S S
S S
EE141 77Adapted from © Digital Integrated Circuits2nd
Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
EE141 78Adapted from © Digital Integrated Circuits2nd
Resistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce, o
hm
s
Rn
Rp
Rn || Rp
R [kΩ]
It has a series resistance that can be assumed constant, and equal to a couple of KΩ
EE141 79Adapted from © Digital Integrated Circuits2nd
Delay in Transmission Gate Networks
V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
In
ReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
C
In
m
(c)
EE141 80Adapted from © Digital Integrated Circuits2nd
Delay Optimization
mopt is typically 3 or 4 ..
EE141 81© Digital Integrated Circuits2ndCombinational Circuits
Dynamic Logic
EE141 82Adapted from © Digital Integrated Circuits2nd
Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type)
devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type)
transistors
EE141 84Adapted from © Digital Integrated Circuits2nd
Dynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
EE141 85Adapted from © Digital Integrated Circuits2nd
Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
EE141 86Adapted from © Digital Integrated Circuits2nd
Properties of Dynamic Gates
Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static
complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect
the logic levels Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL
EE141 87Adapted from © Digital Integrated Circuits2nd
Properties of Dynamic Gates
Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND
(including Psc) no glitching higher transition probabilities due to periodic charge and
discharge extra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock
EE141 88Adapted from © Digital Integrated Circuits2nd
Issues in Dynamic Design: Charge Leakage
CL
Clk
Clk
Out
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dominant component is subthreshold current
EE141 89Adapted from © Digital Integrated Circuits2nd
Solution to Charge Leakage
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Same approach as level restorer for pass-transistor logic
Keeper
EE141 90Adapted from © Digital Integrated Circuits2nd
Issues in Dynamic Design: Charge Sharing
CL
Clk
Clk
CA
CB
B=0
A
OutMp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
EE141 91Adapted from © Digital Integrated Circuits2nd
Charge Sharing
Mp
Me
VDD
Out
A
B = 0
CL
Ca
Cb
Ma
Mb
X
CLVDD CLVout t Ca VDD VTn VX – +=
or
Vout Vout t VDD–CaCL-------- VDD VTn VX
– –= =
Vout VDD
CaCa CL+----------------------
–=
case 1) if Vout < VTn
case 2) if Vout > VTnB 0
Clk
X
CL
Ca
Cb
A
Out
Mp
Ma
VDD
Mb
Clk Me
EE141 92Adapted from © Digital Integrated Circuits2nd
Solution to Charge Redistribution
Clk
Clk
Me
Mp
A
B
OutMkp
Clk
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
EE141 93Adapted from © Digital Integrated Circuits2nd
Issues in Dynamic Design: Backgate Coupling
CL1
Clk
Clk
B=0
A=0
Out1Mp
Me
Out2
CL2
In
Dynamic NAND Static NAND
=1=0
EE141 94Adapted from © Digital Integrated Circuits2nd
Backgate Coupling Effect
-1
0
1
2
3
0 2 4 6
Vol
tage
Time, ns
Clk
In
Out1
Out2
EE141 95Adapted from © Digital Integrated Circuits2nd
Issues in Dynamic Design 4: Clock Feedthrough
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
CL
Clk
Clk
B
A
OutMp
Me
Signal levels above VDD may cause the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate: a) possible latch-up, b) other nodes disturbed
EE141 96Adapted from © Digital Integrated Circuits2nd
Clock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In1
In2
In3
In4
Out
In &Clk
Out
Time, ns
Vol
tage
Clock feedthrough
Clock feedthrough
EE141 97Adapted from © Digital Integrated Circuits2nd
Other Effects
Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)
EE141 98Adapted from © Digital Integrated Circuits2nd
Cascading Dynamic Gates
Clk
Clk
Out1
In
Mp
Me
Mp
Me
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2V
VTn
Due to finite discharge time of first stage, the second stage output drops when it shouldn’t
EE141 99Adapted from © Digital Integrated Circuits2nd
Domino Logic
In1
In2 PDN
In3
Me
Mp
Clk
ClkOut1
In4 PDN
In5
Me
Mp
Clk
ClkOut2
Mkp
1 11 0
0 00 1
Output transition always starts at 0, and only 0 →1 transitions occur
EE141 100Adapted from © Digital Integrated Circuits2nd
Why Domino?
Clk
Clk
Ini PDNInj
Ini
Inj
PDN Ini PDNInj
Ini PDNInj
Like falling dominos!
EE141 101Adapted from © Digital Integrated Circuits2nd
Properties of Domino Logic
Only non-inverting logic can be implemented
Very high speed static inverter can be skewed, only L-H
transition Input capacitance reduced – smaller logical
effort
EE141 102Adapted from © Digital Integrated Circuits2nd
Summary
Static CMOS: Performance is a strong function of fan-in. Speed is a linear function of fan-in
Ratioed logic: reduction of complexity at the expense of static consumption and asymmetrical response
Pass-transistor logic: simple for some functions. Long switch networks have quadratic delay. NMOS only networks are even simpler, but suffer from power consumption and reduced margins
Dynamic logic: Trades off noise margins for performance. Sensitive to leakage, coupling and charge sharing. Cascading can cause problems
EE141 103© Digital Integrated Circuits2ndCombinational Circuits
Appendix I
Elmore Delay
EE141 104Adapted from © Digital Integrated Circuits2ndY. Ismail, Equivalent Elmore Delays for RLC Trees, Proc. DAC 1999