EE141 1 EE141 1 EECS141 EE141 EE141- Fall 2006 Fall 2006 Digital Integrated Digital Integrated Circuits Circuits Lecture 11 Lecture 11 Wire modeling Wire modeling CMOS logic CMOS logic EE141 2 EECS141 Announcements Announcements No lab this week Lab 4 reports due next week Hardware lab next week Homework #5 due today No new homework this week Midterm 1 on Thursday, 6:30-8pm, 105 North G. Material until last lecture, homework 5, lab 4 Review session tonight 6-7:30pm, 60 Evans Check the web page for extra office hours There is a lecture on Th No lecture on October 24
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EE141-Fall 2006 Digital Integrated Circuitsbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f06/...No lab this week Lab 4 reports due next week Hardware lab next week Homework #5 due
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EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuits
Midterm 1 on Thursday, 6:30-8pm, 105 North G.Material until last lecture, homework 5, lab 4Review session tonight 6-7:30pm, 60 EvansCheck the web page for extra office hours
More Interconnect Layersreduce average wire-length
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PolycidePolycide Gate MOSFETGate MOSFET
n+n+
SiO2
PolySilicon
Silicide
p
Silicides: WSi 2, TiSi2, PtSi2 and TaSi
Conductivity: 8-10 times better than Poly
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Sheet ResistanceSheet Resistance
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Modern InterconnectModern Interconnect
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Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process
5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric
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Modern InterconnectModern Interconnect
90nm process
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INTERCONNECTINTERCONNECT
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InterconnectInterconnectModelingModeling
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The Lumped ModelThe Lumped ModelVout
Drivercwire
VinClumped
Rdriver Vout
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The Lumped RCThe Lumped RC--ModelModelThe Elmore DelayThe Elmore Delay
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The Elmore DelayThe Elmore DelayRC ChainRC Chain
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Wire ModelWire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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The Distributed RCThe Distributed RC--lineline
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StepStep--response of RC wire as a response of RC wire as a function of time and spacefunction of time and space
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (
V)
x= L/10
x = L/4
x = L/2
x= L
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Driving an RCDriving an RC--lineline
Vin
Rs Vout(rw,cw,L)
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RCRC--ModelsModels
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CMOS LogicCMOS Logic
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Combinational vs. Sequential LogicCombinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
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Static CMOS CircuitStatic CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to eitherVDD or Vssvia a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit style, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.