EE 330 Integrated Circuit - Chongli Cai Electrical Engineer · EE 330 Integrated Circuit Sequential Airbag Controller Chongli Cai Ailing Mei ... EE 330 Final Project Spring 2012 Chongli

EE 330 Integrated Circuit

Sequential Airbag Controller

Chongli Cai

Ailing Mei

04/2012

EE 330 Final Project Spring 2012 Chongli Cai; Ailing Mei

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Content……………………………………………………………...page

Introduction ....................................................................................3

Design strategy ..................................................................................3

Input, Output and Registers in the System ..........................................4

Initialization Block..............................................................................5

Sensor-airbag Control and Seat-airbag Control Blocking .....................8

Checking Airbag state Block ...............................................................9

Clock generator block .........................................................................9

Test bench and Simulation Result ..................................................... 10

Schematic and Layout ...................................................................... 14

Verilog Synthesis with RTL Compiler ......................................... 14

Import Schematic to Cadence Virtuoso after Synthesis ............. 14

powerplanning ......................................................................... 15

Placement ................................................................................ 15

Routing .................................................................................... 16

Filler cells ................................................................................. 16

Layout ...................................................................................... 17

Conclusion ....................................................................................... 18


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Introduction

In this project, we design a digital system to control sequential deployment of the multiple

airbags in the car. In the system, there are two inputs which are 9-bits impact sensors and 3-bits

weight sensors. In addition, we also include 1-bit reset and 1-bit clock signal in the digital system.

The output of the system is an 8 bits wide data. Each bit represents the state of each airbag. We

divided the whole system into 4 blocks to design, which are initialization block, sensors-airbag

control and seat-airbag control block, checking airbag state block, and clock generator block.

Design strategy

In our analysis, the state of each airbag depends on both corresponding weight sensor and impact

sensor. So we divide it into two parts to design and then combine the two result together (using

AND logic). In the first part, we ignore the effect of weight sensor and only consider the impact

sensor. That is, we always assume there are people who are greater than 60lb seating at all three

seats in this part. For example, triggering impact sensor S1 will cause airbag B1 and B2 open. In

the second part, we ignore the effect of impact sensor and only consider the seat sensor. For

example, the passenger in the seat 1 is corresponding to the airbag B2 and B4 open. Finally, we

will combine the results of the two parts using logic AND. That is, only if each airbag satisfy

both the two conditions in the two parts (results are both logic “1”), it can be in the open state.

Since the output of the system is an 8 bits data, in order to be convenient for arithmetic we

convert both 3 bits weight sensors input and 9 bits impact sensors input to 8 bits data storing in

registers.

Since there is a 5ms delay for each adjacent airbag open, the output clock frequency is 200Hz

which is too slow. In the test-bench the clock is 2M Hz, therefore we also design a clock divider

to generate the 200Hz frequency. In addition, also make the generated 200Hz clock is

synchronous with the impact sensor. That is, the first relative airbag can be open immediate once

the impact sensors are triggered and do not need to wait to the next positive edge of clock. This

is also an improvement of the system.


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Input, Output and Registers in the System

“reg [7:0] seat_airbag [0:2]”

Decode 3-bits seat input to 3 memory cells with 8-bits wide. Each memory cell represents the

airbags which are related to the corresponding seat.

“reg [7:0] sensor_airbag [0:9]”

Decode 9 bits sensor input to 9 memory cells with 8 bits wide. Each memory cell represents

the airbags which are related to the corresponding impact sensor.

“ reg [7:0]seat_active_airbag

It stores all the active airbag without considering the state of impact sensor

“ reg [7:0] sensor _active_airbag”

It stores all the active airbag without considering the state of weight sensor

“ reg [7:0] next_active_airbag [0:7]”

It includes 8 memory cells with 8 bits wide. Each memory cell is corresponding to an airbag

and each bit of the memory cell represents the state of each airbag on the next trigger edge if

the current airbag is triggered. For example, next_active_airbg[0]=00000110 represents that

the airbag B2,B3 will be triggered at next edge if B1 is triggered currently.


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“ check _active_airbag”

It is a temporary register and used to store the current sensor_active _airbag. It is only used in

the block which functions as finding the next active airbag.

“ reg [12:0] clk_count”

It is a counter used to generate a slower clock.

“ reg clk_200”

Generated 200Hz clock

“reg clk_trigger”

Enable of the generated clock

Initialization Block

Figure (2)


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Since there is always a driver in the driver position, the two airbags B1, B3 can always be

triggered. So, the initial value for register “ seat_active_airbag” is “00000101”.

All impact sensors are in the deactivated state, so the initial value for register

“sensor_active_airbag” is “00000000”.

Memory cells “ seat_airbag” initialization

Figure (3)

Each memory cell is corresponding to one position (3 memory cells array)

Seat 1 has two airbag B2 and B4 initial value for “seat_airbag [0]” is “00001010”



Memory cells “ seat_airbag” initialization

Figure (4)

Seat 1

Seat 2

Seat 3


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Each memory cell is corresponding to one sensor (9 memory cells array)

S1 can active airbag B1, B2 initial value for “seat_airbag [0]” is “00000011”

S2 can active airbag B1 initial value for “seat_airbag [1]” is “00000001”

S3 can active airbag B2 initial value for “seat_airbag [2]” is “00000010”





S8 can active airbag B7, B8 initial value for “seat airbag [7]” is “11000000”

S9 can active airbag B7, B8 initial value for “seat airbag [8]” is “11000000”

Memory cells “ next_active_airbag” initialization

Figure (5)

Each memory cell is corresponding to one airbag (8 memory cells array)

Airbag B1 is adjacent to B2 and B3 initial value for “next_active_airbag [0]” is “00000110”

Airbag B2 is adjacent to B1 and B4 initial value for “next_active_airbag [1]” is “00001001”

Airbag B3 is adjacent to B1, B4 and B5 initial value for “next_active_airbag [2]”

is“00011001”


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is“00100110”


is“01100100”


is“10011000”


is“10010000”


is“01100000”

Sensor-airbag Control and Seat-airbag Control Blocking

Figure (6)

Register “sensor_active_airbag” stores the active airbag with only considering the impact sensor

state and do not consider the weight sensor state. The system will check each impact sensor

sequentially. Once the system detects that one impact sensor is triggered, then it will use OR

logic to store its corresponding airbags into the register “sensor_active_airbag”.

Register “seat_active_airbag” stores the active airbag with only considering the seat sensor state

and do not consider the impact sensor state. The system will check each weight sensor

sequentially. Once the system detects that one weight sensor is triggered, then it will use OR

logic to store its corresponding airbags into the register “seat_active_airbag”.


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Once sensor is triggered, it will cause a positive triggered for 200Hz clock.

Checking Airbag state Block

Figure (7)

For the final result, we need to consider both impact sensors and weight sensors. So, we need to

use AND gate to include both two conditions and store it to the register “airbag” for the output of

the system. Next, the system needs to determine the state of airbags at next trigger edge. The

system stores the data in the register “sensor_active_airbag” into the temporary register

“check_active_airbag”. Then the system will check the state of current airbag sequentially. Once

the system detects an airbag is in the open state, it will use OR gate to store its directly adjacent

airbags (in the open state) into register “sensor_active_airbag”.

Clock generator block

Figure (8)


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In the test-bench of the system, it gives a clock with 2MHz which is much faster than the

clock (200Hz) we need. So it needs to design a clock divider to generate the 200Hz clock

from 2MHz. In addition, we use the “clock_triiger” register to enable the generated 200Hz

clock in order to control the starting point of counting time. The benefit is that the airbags

can open immediate once the impact sensors are triggered.

Test bench and Simulation Result

Test bench

Since there are many possible combinations for the triggered impact sensors, we just choose

several combinations to do test bench and simulation randomly.

The following is the test-bench for sensor S1 and S7 are triggered for both seat 1 has passenger

and no passenger condition.

Figure (9)


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Simulation Result

Case 1: S5 is triggered

If all three seats have passengers

5 0

5 0

10 5

15 10

Table (1)

Figure (10)

If there is no passenger in the seat 1

5 not open

5 not open

10 5

15 10

Table (2)

Figure (11)

S5

S5


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Case 2: S1 and S7 are triggered


0 0

5 5

5 0

5 0

Table (3)

Figure (12)

If there is no passenger in the Seat 2

0 0

5 5

Not open 0

Not open 0

Table (4)

Figure (13)

S1

S7

S7

S1


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Case 3: S3 is triggered


Table (5)

Figure (14)

If there is no passenger in the seat 3

5 0

10 5

15 not open

20 not open

Table (6)

Figure (15)

5 0

10 5

15 10

20 15

5 0

10 5

15 10

20 15

S3

S3


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Schematic and Layout

Verilog Synthesis with RTL Compiler

Figure (16)

Import Schematic to Cadence Virtuoso after Synthesis

Figure (17)


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powerplanning

Figure (18)

Placement

Figure (19)


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Routing

Figure (20)

Filler cells

Figure (21)


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Layout GDS import layout form Encounter to Virtuoso

Figure (21)

DRC result

Figure (22)


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Conclusion Our design satisfied all the function required. Our Verilog code passes the test. All the

simulation Results are identical as the theoretical results. The layout has passed the DRC.

EE 330 Integrated Circuit - Chongli Cai Electrical Engineer · EE 330 Integrated Circuit Sequential Airbag Controller Chongli Cai Ailing Mei ... EE 330 Final Project Spring 2012 Chongli

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