EE 210. LOGIC DESIGN LAB. - toile-libre.orgmyreader.toile-libre.org/uploads/My_525172a33a5cd.pdf · 2 EE 210: Logic Design Lab. ... NAND and NOR gates. II-2 Materials & Components

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EE 210.

LOGIC DESIGN LAB.

(1st semester 1426-27)

Dr. Messaoud Boukezzata Office: EE 11

Phone: 063 8000 50 Ext 3152

College of Engineering

Electrical Engineering Department

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EE 210: Logic Design Lab. (1st semester 1426-27)

Instructor: Dr. Messaoud Boukezzata

Office: EE 11

Phone: 063 8000 50 Ext 3152

A- Course Outline:

Weeks Topic Date

1st Exp. 1: Introduction to Logic Lab. & Kits 24/09/05

2nd

Exp. 2: Introduction to Logic Gates 01/09/05

3rd

Exp. 3: Minimization of Boolean functions 08/10/05

4th First Mid-Term Exam 15/10/05

5th Exp. 4: Xilinx Software Tutorial 22/10/05

6th Exp. 5: Design Full Adder & 4-bit Full Adder 12/11/05

7th Exp. 6: Design 4-bit Adder/subtractor 19/11/05

8th Second Mid-Term Exam 26/11/05

9th Exp. 7: Decoders 03/12/05

10th Exp. 8: Introduction to Flip-Flops 10/12/05

11th Exp. 9: Counters 17/12/05

12th Final Exam 31/01/06

B- Marks Distribution:

Quizes, Attendance& Experiment preparation 10

1st midtermexam 25

2nd

midterm exam 25

Final exam 40

Total marks 100

C- References:

1- Text Book: M. Morris Mano, Digital Design, Int‟l 3rd

Edition, Prentice Hall (2002).

2- Lab. Notes: “EE 210: Logic Design Lab.”, edited by KSU, (2nd

semester 1424-25).

Instructor Vice-Dean for academic affairs

Dr. Messaoud Boukezzata Dr. Abdul Rahman Al-Marshood



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Preface

For the first time, we have constructed and started the Lab. experiments in the

Electrical Engineering Department of Qassim University, on the basis of what it is done

in similar department in the King Saud University of Riyadh. However, some

experiments are well adapted to be more representative to the Lab. possibilities. Of

course, these rearrangements have maintained intact the heart of the subject and the main

aim of each session. The only lack that we should fill up in the near future is to provide a

recent version of the Xilinx software, needed for acquiring high level of simulations

skills. The student version of ISE 4.2i is not sufficient to implement a correct simulation

design due to its limit function. We have tried to upgrade this version via internet site of

Xilinx foundation (www.xilinx.com/downloads), by downloading new files offered but

the student version is given free not upgradeable. So, we think that the best solution is to

purchase a commercial version adapted to educational uses as ISE 7.0 which may be the

best solution. That‟s exactly what is we have finally opted to do with the permission of

our higher responsibles: Dr. Sulayman Al Yahia, the Dean of the college of Engineering,

and Dr. Abdulrahman Al Marshoud, the Vice-Dean of the College for academic affairs &

Head of the Electrical department.

We think that the student will find in this laboratory notes a helpful document for

his Lab. Reports and a complement manual for the course text book in order to

understand some details of chapters missed or not found in the course sessions.

We hope that all these efforts will not be interrupted after the first start-working

of Lab. sessions (EE 210) as programmed, but followed by other efforts, other

improvements, and other acquisitions for enabling the logic design laboratory to reach its

outstanding state.

Finally, we would like to thank Dr. Sulayman Al Yahia for his ambition and his

determination to push the College of Engineering to reach a well confirmed level of

technical science, and to thank Dr. Abdulrahman Al Marshoud for his enthusiasm, his



http://www.xilinx.com/downloads

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perseverance and his obstinate approach for doing always what it is requested in the best

manner and in due time.

Buraydah: The 5/11/1426 H (07/12/2005)

Dr. Messaoud Boukezzata Associate Professor

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Session 1.

INTRODUCTION TO LOGIC DESIGN LAB. & KITS

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EE 210: Logic Design Lab. Session 1.

INTRODUCTION TO LOGIC DESIGN LAB. AND KITS

I-1 Objectives:

The first session is devoted to explore and to know the logic design laboratory

environment prior to experience practical duties.

I-2 Materials & Components Needed:

Logic Design Kit, logic IC's, Computers and their simulation capabilities and divers logic

components.

I-3 Digital IC's and logic gates overview:

I-3-1 What is the IC?: An IC is an electronics circuit miniaturized and fabricated

in a chip of an area of some cm square and encapsulated in divers standard shapes of

packages. In our Lab. Experiments we should need to IC's of 14, 16 or more DIP pins

(Dual-In line Package).

Figure I-1: Example of 2 IC‟s with a different number of pins



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I-3-2 Biasing: In the 74 series 14-pins we should find, in some times, the ground

Gnd is connected to 0 V through the pin number 7 and to Vcc = 5 Volts through the pin

number 14, but in other times Gnd to pin 11 and Vcc to pin 4 (as in the case of 7478 Dual

JK Flip-Flop) and also in another times Gnd to pin 10 and Vcc to pin 5 (as in case of 7493

4-bit binary counter).

I-3-3 Handling: (make attention to static discharge and always try to do your

manipulations without destroying these fragile IC‟s. So, keep care with them).

I-3-4 Interconnections: According to the circuit design, interconnections are well

defined and must be implemented in their good positions, otherwise, short circuit will be

dangerous for all the kit laboratory including all the gates to be used.

I-3-5 Pins assignment: See p.439 of the text book for pin assignment of some

most used logic IC‟s in this lab. An example of a 3-input NAND is given in the following

figure.

Figure I-2: Another example of an IC with pins assignment for 7411

I-3-6 Inputs and outputs: not always in the same places, it depends on the IC logic

diagram and function.

I-3-7 Logic state: 0 (low) and 1 (high) are the logic states for common

experiments.

I-4 Introduction to Logic Lab. Kit:

I-4-1 Circuits wiring: Each student should have 63 colored wires of different

lengths (very small, small, long and very long). According to the position and the

connected points to be wired you should use the appropriate lengths for the circuit wiring.

I-4-2 Unconnected (floating inputs): It depends of the circuit under test. The

output should not change when floating inputs take 1 or 0.

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I-4-3 Power supply: 5 Volts indicated as Vcc.

I-4-4 Display: Displayed results are given by LED‟s or seven segment display.

I-4-5 Testing: When finished, implementation is tested in order to confirm

theoretical results which must be the same, otherwise errors are expected to be found and

removed from the implementation.

I-5 Logic lab. testing instruments, Components and tools:

Figure I-3: Presentation of the kit lab. which will be used in our sessions.

I-6 Review Questions:

Try to identify different elements of the 74 IC‟s family, keep with you for

frequent uses an appendix which should regroups all of the used IC‟s.

I-7 Next Experiment Assignment:

Read the procedure of Session 2 and prepare the following:

The truth table of simple gates as AND, OR, NOT, NAND, NOR, XOR, and

XNOR.

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Take in mind the difference of pin assignment between 2-input, 3-input, and

4-input gates.

I-8 Appendix:

Figure I-4: The most used of digital gates in IC package

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Session 2.

INTRODUCTION TO LOGIC GATES

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INTRODUCTION TO LOGIC GATES

II-1 Objectives:

Study the function and verify the truth table of AND, OR, NOT, NAND and NOR gates.

II-2 Materials & Components Needed:

Logic Design Kit, 7400, 7402, 7404, 7408 and 7432 IC‟s, LED and connecting wires

II-3 Procedure:

Construct the truth tables for the following gates and diagrams and verify its

operation:

II-3-1) NOT: First, use a 7404 chip and build the circuit below (Figure II-1).

Verify its truth table.

Figure II-1: Test of the inverter gate. Table II-1: Truth table of

the inverter gate.

Second, connect to inverters in cascade.

What will be final output?



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Figure II-2: Test of two inverters. Table II-2: Truth table of

two inverters.

II-3-2) AND: First, use a 7408 chip and build the circuit as it is shown in the

below figure.

Verify its truth table.

Figure II-3: Test of AND gate. Table II-3: Truth table of

AND gate.

Second, connect the three AND gates with respect to the diagram given below.

Figure II-4: Logic circuit with AND gates.

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Table II-4: Truth table of the tested AND logic circuit.

II-3-3) OR: Use a 7432 chip and build the circuit below. Verify its truth table.

Figure II-5: Test of OR gate. Table II-5: Truth table of

OR gate.

II-3-4) NAND: First, use a 7432 chip and build the circuit below. Verify its truth

table.

Figure II-6: Test of NAND gate. Table II-6: Truth table of

NAND gate.

Second, keep one of the wires floating (disconnect) and check the output. Is the

floating input considered low or high?.

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II-3-5) NOR: Use a 7402 chip and build the circuit below. Verify its truth table.

Figure II-7: Test of NOR gate. Table II-7: Truth table of

NOR gate.

II-3-6) XOR: Use a 7486 chip and build the circuit below. Verify its truth table.

Figure II-8: Test of XOR gate. Table II-8: Truth table of

XOR gate.

II-4 Review Questions:

II-4-1. Using Boolean Algebra, show how could you implement the following

gates using ONLY NOR gates.

i) NOT, ii) AND, iii) OR.

II-4-2. Draw the circuit of the following Boolean equation using basic gates:

F(A,B,C) = AB + C‟.

II-4-3. Construct the truth table of the following circuit:

Figure II-9: Simple logic test circuit gate.

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Table II-9: Truth table of the tested logic circuit.

II-5 Next Experiment Assignment:


The truth table for the given Boolean equation.

Draw its schematic equivalent circuit very neatly.

Minimize the circuit to only two literals then draw the minimized circuit.

Session 3.

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MINIMIZATION OF BOOLEN FUNCTIONS


MINIMIZATION OF BOOLEAN FUNCTIONS

III-1 Objectives:

Boolean functions minimization and implementation

III-2 Materials & Components Needed:



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Logic Design Kit, 7400, 7404, 7410‟s, LED and connecting wires

III-3 Procedure:

III-3-1) Obtain the Boolean function F(A, B, C) of the circuit given below.

Figure III-1: Training test with multi-level simple logic gates.

III-3-2) Construct its truth table (you should use an extra sheet to draw this table,

and you should take A, B, C as inputs and F as final output).

Fill the table given below (you should take attention to the connections between

elements and you should also expect to use different colors of wires for minimize errors).

Then, connect the above circuit and verify its truth table with previous step.

How many IC components we should need when the implementation is done only

with 7400 and 7410 together, and when the inverters were taken from a 7404 IC.?

A B C A‟ B‟ C‟ AB‟C‟ A‟BC AC F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Table III-1: Truth table of the previous circuit.

III-3-3) Minimization of the Boolean function to only a minimum of literals:

Simplify this circuit by using the map method.

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III-3-4) Find the logic diagram of the simplified Boolean function F(A, B, C) by

using only one 7410 IC.

III-3-5) Suppose you have obtained the simplified circuit by using the appropriate

technique and you have found a circuit similar to what is shown in the following figure

(Fig.III-2).

Connect the simplified circuit without disconnecting the first one, already done in

previous step.

Again, verify its truth table.

III-3-6) Compare the results obtained in III-3-2) and III-3-5).

III-3-7) What do you observe if inverters 7404 are available?

Figure III-2: Minimized circuit obtained by k-map method.

A B C B‟ AB‟ AC F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Table III-2: Truth table of the simplified circuit.

IV- Review Questions:

Verify the truth table of the logic circuit shown below.

Simplify its Boolean function to only three literals.

Redraw the diagram of the minimized circuit.

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Show how could you verify your results theoretically and experimentally.

Figure III-2: Home work training test with multi-level simple logic gates.

V- Next Experiment Assignment:

Install Xilinx Software in your computer (or use the software already installed in some of

the platforms in the computer center). List all problems you might face during

installation.

Session 4.

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XILINX SOFTWARE TUTORIAL


XILINX SOFTWARE TUTORIAL

IV-1 Objectives:

This tutorial steps the student through using the Xilinx Foundations Software to

implement a simple logic design such as session 1 of these Lab. experiments.



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IV-2 Materials & Components Needed:

Logic Design Kit, PC with Xilinx already installed.

IV-3 Example Design Problem:

A majority voter has three 1-bit inputs (A, B, C) and one 1-bit output (M) as seen in the

following figure. The output M takes on the majority value of the three inputs. The truth

table shown below fully illustrates its function. Whenever two or more inputs are „0‟ then

the output M is „0‟. Whenever two or more inputs are „1‟ then the output M is „1‟.

Figure IV-1: Bloc diagram of the presented problem.

Table IV-1: Truth table of the majority voters.

IV-4 Solution to Design Problem:

According to the truth table given above and using K-map method, we can easily find the

Boolean equation, one solution of the majority voter problem. So, we can give the gate

representation.

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Figure IV-2: Home work problem.

IV-5 Xilinx Software:

The Xilinx Foundations software used in this session can be installed from a copy which

comes with your class textbook. To do the requested tasks in this session, follow the steps

as explained during the Lab. experimentation.

IV-6 Review Questions:

* use XOR gates in your design.

IV-7 Next Experiment Assignment:

Read the procedure of the next Session and prepare the following:

Construct the truth table for the full adder.

Using Xilinx Software design and simulate the full adder circuit.

Provide your schematic design and simulation results on hard copies.

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Session 5.

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FULL ADDER IMPLEMENTATION &

SIMULATION


FULL ADDER IMPLEMENTATION AND SIMULATION

V-1 Objectives:

In this Lab., you will compile and simulate a 4-bit full adder using an HDL language

program.



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V-2 Materials & Components Needed:

VHDL Simulator, Computers and a Technical Data-book reference for Logic Design

Gates

V-3 Procedure:

V-3-1 Background: According to the example given bellow (see figure 1), we

should first write the HDL program and second try to run it using a Verilog simulator.

Figure V-1-a: Full adder logic circuit.

Figure V-1-b: Schematic of the 4-bit full adder.

V-3-2 HDL Program: For figure 1-a, the program is given as follow:

//** add4.v File **.

//** Full Adder **. module fulladder(sum, c_out, x, y, c_in);

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output sum, c_out;

input x, y, c_in;

wire a, b, c;

xor (a, x, y);

xor (sum, a, c_in);

and (b, x, y);

and (c, a, c_in);

or (c_out, c, b);

endmodule

Now, if you feel be able to write the program for the second figure (Fig. 1-b) you will go to

experience it.

//** 4-Bit Adder **.

module FourBitAdder(sum, c_out, x, y, c_in);

output [3:0] sum;

output c_out;

input [3:0] x, y;

input c_in;

wire c1, c2, c3;

fulladder fa0(sum[0], c1, x[0], y[0], c_in);

fulladder fa1(sum[1], c2, x[1], y[1], c1);

fulladder fa2(sum[2], c3, x[2], y[2], c2);

fulladder fa3(sum[3], c_out, x[3], y[3], c3);

endmodule

//*******************************************

// VeriLogger Pro: Basic Verilog Simulation

//*******************************************

//**add4test.v File ***************************

module testbed();

reg c_in;

reg [3:0] y;

reg [3:0] x;

wire c_out;

wire [3:0]sum;

FourBitAdder A1(sum, c_out, x, y, c_in);

initial

begin

x = 4'b0001; y = 4'b0001; c_in = 1'b0;

#25 x = 4'b0001; y = 4'b0010;

#25 x = 4'b0010; y = 4'b0011;

#25 x = 4'b0001; y = 4'b1111;

#25 x = 4'b0001; y = 4'b1111; c_in = 1'b1;

#25 x = 4'b1000; y = 4'b1111; c_in = 1'b0;

#25 x = 4'b0001; y = 4'b0001; c_in = 1'b1;

#25 x = 4'b0001; y = 4'b0010;

#25 x = 4'b0010; y = 4'b0011;

#25 x = 4'b0011; y = 4'b1111;

#25;

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end

initial

#250 $finish;

endmodule

V-3-3 Simulation: As you can see, this used version of simulation program can‟t

support more than six lines, so we will choose to run another program according to this

limitation.

module fulladd4(sum, c_out,a,b,c_in);

output [3:0] sum;

output c_out;

input [3:0] a,b;

input c_in;

assign {c_out, sum} = a + b + c_in;

initial

begin

$monitor(“time %0d ns, A= %b, B= %b, C= %b, C_IN= %b,

C_OUT= %b, SUM %b”, A, B, C_IN, C_OUT, SUM)

end

endmodule

V-3-4 Application: Follow the procedure application explained directly during the

Lab. session

V- Review Questions:

Try to review the theoretical aspects of the adder – subtractor logic circuit. How could

you use the same chip (IC 7483) for constructing the diagram which can perform the

addition and the subtraction without major modifications?

V- Next Experiment Assignment:

You need the following components for the preparation of the next experiment:

- 7483

- 7486.

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Session 6.

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DECODERS


DECODERS

VI-1 Objectives:

Implementation of decoders applications.

VI-2 Materials & Components Needed:

Logic Design Kit, logic IC type 7447 (BCD to seven-segment display) and 74138 (3-to-8

lines decoder), and wire connections.



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VI-3 Summary of theory:

The decoder is a combinational logic circuit that converts binary information from n

input lines to a maximum 2n unique output lines. The decoders are used whenever an

output or group of outputs is to be activated on the occurrence of a specific input

combination. They are so useful for many practical applications such as seven segment

display interfacing and implementation of some logic circuits as it is considered a

minterm generator.

The 74138 decodes one of eight lines dependant on the conditions of the three binary

select inputs and the three enable inputs. Two active-low and one active-high enable

inputs reduce the need for external gates or inverters when expending.

VI-4 Procedure:

1. Using the built-in Seven-Segment Display in the lab. kit, display the numbers

from 0 to 9. (input switches, D is the MSB –Most Significant Bit- and A is the LSB

–Low Significant Bit-).

2. Connect the 74138 decoder as shown in its data sheet specifications given in the

following figure and verify its truth table.

3. Design, implement and test a full adder using 74138 with some gates. You can

take into consideration what you have taken in the course notes (use 4 inputs

NAND gates).

Figure VI-1: Presentation of the 3 x 8 (74138) IC decoder.

VI-5 Review Questions:

* As you have studied the circuit of the decoder you can anticipate the study of a

multiplexer logic circuit. To identify different elements of the 74151 IC‟s, keep with you

for frequent uses an appendix which should regroups all information concerning this

circuit.

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VI-7 Next Experiment Assignment:


How to connect the 16-pin of the IC to the other elements of the circuit, and to

know what is the function of the selection inputs, data inputs, enable input and

the outputs.

Think to have one frequently used application of the 8-to-1 line multiplexer

including the 74151 IC type.

Session 7.

DESIGN WITH MULTIPLEXERS

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DESIGN WITH MULTIPLEXERS

VII-1 Objectives:

In this experiment, you will design a combinational circuit and implement it with

multiplexers, as explained in the following paragraphs. The multiplexer to be used is an

IC type 74151, shown in the figure given below. The internal construction of the 74151 is

similar to the diagram presented here.

VII-2 Materials & Components Needed:

Logic Design Kit, logic IC type 74151 and wire connections.

VII-3 Example Design Problem – Shares Voting:



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A small corporation has 10 shares of stock, and each share entitles its owner to

one vote at a stockholder‟s meeting. The ten shares of stock are owned by four people as

follows:

Mr. W: 1 share

Mr. X: 2 shares

Mr. Y: 3 shares

Mrs. Z: 4 shares

Each of these persons has a switch to close when voting yes and to open when voting no

for his or her shares.

It is necessary to design a circuit that displays the total number of shares that vote yes for

each measure.

VII-4 Solution to Design Problem:

We need a seven-segment display and a decoder to display the required number. If all

shares vote no for a measure, the display should be blank. (Note that binary input 15 into

the 7447 blanks all seven segments.) If 10 shares vote yes for a measure, the display

should show 0. The eight inputs are designated D0 through D7. The selection lines (C, B,

and A) select the particular input to be multiplexed and applied to the output. A strobe

control S acts as an enable signal. The function table specifies the value of output Y as a

function of the selection lines. Output W is the complement of Y. For proper operation,

the strobe input S must be connected to ground.

Figure VII-1: Presentation of the 8-to-1 (74151) IC multiplexer.

VII-5 Experiment circuit:

Use four 74151 multiplexers to design the combinational circuit that converts the inputs

from the stock owners‟ switches into the BCD digit for the 7447.

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Connect the circuit using the configuration given above with respect to the following

specifications:

a) In the first 74151:

- Connect S2, S1, S0 to A, B, C respectively, and,

- I0 = I1= I4 = I5 = D, and,

- I2 = I3= I6 = I7 = D‟ respectively.

b) In the second 74151:

- Connect S2, S1, S0 to A, B, D respectively, and,

- I0 = I1= I3 = I5 = I7 = C, and,

- I2 = I6 = D‟, and,

- I4 = D respectively.

c) In the third 74151:

- Connect S2, S1, S0 to A, D, C respectively, and,

- I0 = I1= I3 = I7 = B, and,

- I4 = B‟, and,

- I2 = I6 = D, and,

- I5 = D; and, respectively.

d) In the fourth 74151:

- Connect S2, S1, S0 to B, C, D respectively, and,

- I0 = I1= I3 = I6 = I7 = A, and,

- I4 = A‟, and,

- I5 = D, respectively.

The decoder and the seven-segment display, you can use those built-in directly from the

Kit Lab.

Test the work of the circuit. Obviously, if you observe any errors try to correct them.

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Figure VII-2: Logic circuit with 74151 IC multiplexer.

VII-6 Review Questions:

* To the combinational logic circuit side, we have another side which is the

sequential logic circuits. The first element of the sequential circuit type is a flip-flop.

Revise your course notes and see how which IC from the 74 family‟s can function as a

flip-flop. What is the different type of flip-flops we can find in our frequent uses.

VII-7 Next Experiment Assignment:


Design and implement a binary counter by using flip-flops.

Write an HDL the program of the obtained circuit.

Use the testbencher.pro to run your program.

Give the final results of simulation.

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Session 8.

INTRODUCTION TO FLIP-FLOPS


INTRODUCTION TO FLIP-FLOPS



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VIII-1 Objectives:

In this experiment, we can construct, test and investigate the operation carried out by flip-

flops. We should see the extreme importance of these kinds of logic circuits in the

construction of counters, registers and memories.

VIII-2 Materials & Components Needed:

- Logic Design Kit.

- logic IC type 7474 (Dual D-type edge-triggered Flip-Flop).

- 7476 (Dual JK Master-Slave Flip-Flop).

- Wires.

VIII-3 Summary of theory:

A flip flop is known as a sequential logic element. It is, not surprisingly, a fundamental

building block for creating sequential logic circuits. Some examples of this type of circuit

include shift registers and counters. These types of circuit depend not only on a set of

inputs, but also their past inputs to work correctly. For example, let us say you want to

design a circuit that will count from zero to three, in steps of one, every time a switch is

pressed. A simple switch can only have two possible states. It can either be switched on,

or switched off. Yet each time the switch is pressed, we want the circuit to display a

different output state.

For example:

Press switch once. The output changes from 0 to 1.

Press switch again. The output changes from 1 to 2.

Press switch again. The output changes from 2 to 3.

From this example it can be seen that the circuit will only work correctly if it somehow

'remembers' its previous state. Flips flops have the ability to remember their past history

and are often referred to as bistable devices.

VIII-4 IC Flip-Flops:

IC type 7474 consists of two D positive-edged-triggered flip-flop with preset and clear.

Similarly, the IC type 7476 consists also of two JK master-slave flip-flops with preset

and clear. The pin assignment for each flip-flop is shown in the following figures.

mk:@MSITStore:C:/Program%20Files/Digital%20Works/Digital.chm::/PopUpBistableDevice.htm

39

Figure VIII-1: internal structure of 7447 BCD-to-7-segments display decoder

VIII-5 Experiment circuit:

First, connect the 7474 IC to the lab. kit using only one D Flip-Flop as represented in

the figure shown below.

Verify the function table of this Dual D-type edge-triggered Flip-Flop.

Compare the obtained results with theoretical data as what you have seen in the

course sessions.

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Figure VIII-2: Pin assignment of Dual D-type edge-triggered Flip-Flop 7474

Second, repeat the same procedure with the 7476 IC which is given in the next figure.

Verify the function table of the Dual JK Master-Slave Flip-Flop.

Compare the results.

Figure VIII-3: Pin assignment of Dual JK-type edge-triggered Flip-Flop 7476

VIII-6 Review Questions:

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Review the internal structure of different 74 IC‟s family that can function as counters.

Note the specificity of each type of these counters.

VIII-7 Next Experiment Assignment:

Read the procedure of Session 9 and design a two decade counter with seven-

segment displaying system.

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Session 9.

COUNTERS



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COUNTERS

IX-1 Objectives:

Design, simulation and implementation of a non-binary counter using Xilinx software

package and Digilab educational kit.

IX-2 Materials & Components Needed:

Logic Design Kit, logic IC type 7474 (Dual D-type edge-triggered Flip-Flop), 7490

(Decade counter), and 7408 AND gates.

IX-3 Summary of theory:

The counter is a sequential circuit that goes through a prescribed sequence of states upon

the application of the input pulses. It is normally built using flip-flops connected in

cascade with a certain configuration depending on the counting sequence required. The n-

bit counter needs n flip-flops and it can have a binary sequence of less than 2n states.

The BCD or Decimal counter is a binary counter that counts from 0000 state to 1001 state

then goes back to 0000 state.

IX-4 Design procedure of experiment circuit:

- First, we suggest to construct a counter which can count from 0 to 99.

- Second, to cover the two decades of counting, our purpose will concern the use of

two decade counters 74LSLS90, an IC type 7474 (Dual D-type edge-triggered

Flip-Flop), and some AND gates 7408.

- For displaying the counting rhythm, we need two seven-segment displays.

- And of course finally, some wires for connection.

The monolithic 74LS90 counter contains four master-slave flip-flops and additional

gating to provide a three stage binary counter for which the count cycle length is divided

by 5. To use their maximum count length, the B input is connected to QA output. The

input count pulses are applied to input A.

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Figure IX-1: Pins assignments of the 74LS90 decade counter

Figure IX-2: Functional block diagram of the 74LS90 decade counter

Not forget to use the following information given in the reset/count function table of the

74LS90 as presented below.

Reset inputs Output

Preset-1 Preset-2 Clear-1 Clear-2 QD QC QB QA

1 1 0 x 0 0 0 0

1 1 x 0 0 0 0 0

x x 1 1 1 0 0 1

x 0 x 0 Count Count Count Count

0 x 0 x

0 x x 0

x 0 0 x

Table IX-1: Reset/count function table of 74LS90

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IX-5 Experiment circuit:

For the Lab. circuit, because the only counter available is the 7493, we should rearrange

this experimentation in order to introduce this IC in replacement of the 7490 expected to

be used in this session 9.

The clock pulses are obtained from the generator built-in and its cycle time may be

changed as desired.

Also, the display system is furnished with the kit lab. and no need to the 7447 for

decoding the binary bits to 7-segments display.

Figure IX-3: Pins assignments of the 4-bit binary 74HC93 counter

Figure IX-4: Functional block diagram of the 4-bit binary 74HC93 counter

When all connections of the circuit is finished, and similarly as you have done with the

74LS90, do not forget to use the following information given in the reset/count function

table of the 74HC93 as presented below.

Reset inputs Output

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Preset-1 Preset-2 QD QC QB QA

1 1 0 0 0 0

0 x Count

Count x 0

Table IX-2: Reset/count function table of 74HC93

Connect the counter circuit as designed in the figure given below.

Verify carefully your connections before the use of power supply.

Test your counter.

Verify its good function.

To connect the rearranged circuit, try to differentiate the mode function between

the 7490 and the 7493.

Use the reset/count function table as given by the manufacturer data book or other

technical documentation notes.

Draw the two reset/count function tables for both 7490 and 7493.

Compare the two tables.

Figure IX-5: Two decades counter circuit

XI-6 Review Questions:

Design, construct, and test a counter that goes through the following sequence

of binary states: 0, 1, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, and back to 0 to repeat.

Note that binary states 4, 5, 8, and 9 are not used. The counter must be self-

starting; that is, if the circuit starts from any one of the four invalid states, the

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count pulses must transfer the circuit to one of the valid states to continue the

count correctly.

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Appendix

LAB.’s EXAMS MODEL

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EE 210: Logic Design Lab. Exams Model.

FIRST MID-TERM EXAM

1) Obtain the Boolean function F(A, B, C) of the above circuit.

2) Construct its truth table.

3) How many IC components we should need when using (7400 and 7410 together), and

when the inverters were taken from a 7404 IC?

4) Simplify this circuit by using the map method.

5) Find the logic diagram of the simplified Boolean function F(A, B, C) by using only

one 7410 IC.

6) Connect the obtained simplified circuit without disconnecting the original circuit and

verify its truth table.

7) Compare the results obtained in 2) and 6).

8) What do you observe if inverters 7404 are available?

Dr. Messaoud BOUKEZZATA



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SECOND MID-TERM EXAM

This circuit has A and B as the inputs and a LED as the output. A, and B are 4 -bit

numbers. When the LED is lighted red, his state is 1, otherwise it means that his state is

0.

a) What is the first problem that you find when you want to construct this circuit on

the Lab. Kit? (1 pt).

b) Suppose you have only 3 IC‟s, one type 7402, one 7408, and one 7486. Construct

the above circuit. (1 pt)

c) What is the condition on the values of Ai and Bi which will give a red light of the

LED. (3 pt)

d) So, what is the function of this circuit? (2 pt)

e) Find the Boolean function F(Ai, Bi) i = 0, 1, 2, 3 corresponding to the state one at

the output. (4 pt)

f) Now, the available IC‟s are only 7402, 7404, and 7408, redraw the same circuit

but using just what you have. (4 pt)

g) Can you implement this last circuit on the Lab. Kit? (1 pt)

h) If we remove A2, A3, and B2, B3, reconstruct the new circuit. (4 pt)




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THIRD MID-TERM EXAM

This circuit has been detailed in the course session but drawn with another output gate:

i) What is this gate used in the output?

j) So, what is the function of this circuit?

k) Draw the version studied in the course session.

l) Among the following IC numbers, find the correct IC number which corresponds

to the given circuit: 74 00, 7408, 74 32, 74 86, 74 47, 74 74, 74 151, 74 138,

7493.

m) Give the name of each IC cited above.

n) What is the difference in function between 74 151 and 74 138.




52


FINAL-TERM EXAM

Date: Tuesday, 1st /01/1427 H

Duration: 9,00 – 12,oo AM

Ex. 01): suppose you have these to circuits:

- Construct the truth table for the two circuits given above.

- What do you remark?

Ex. 02): From the figure presented below:

a) Is this counter synchronous or asynchronous?

b) Why?

c) What is its limit of counting?

d) Draw its function table and its graph pulse timing.

Ex. 03): From the figure presented below:

a) What is the difference between this figure and the figure presented in (Ex. 02)?



53

b) What is its limit of counting?

c) Draw its function table and its graph pulse timing.

Ex. 04): in this circuit, we have fours different components.

a) What is the role of each of them.

b) Why we have two 7490.

c) Why we have two 7447.

d) What is the function of the AND gate 7408.


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MINIMIZATION OF BOOLEAN FUNCTIONS

Initial complicated Circuit:

III-3-1) Obtain the Boolean function F(A, B, C) of the circuit given below.

III-3-2) Construct its truth table (you should use an extra sheet to draw this table).

Then, connect the above circuit and verify its truth table with previous step. How many

IC components we should need when the implementation is done only with 7400 and

7410 together, and when the inverters were taken from a 7404 IC.?

A B C A' B' C' AB'C' A'BC AC F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



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Final minimized circuit:

III-3-3) Minimization of the Boolean function to only a minimum of literals:

Simplify this circuit by using the map method.

III-3-4) Find the logic diagram of the simplified Boolean function F(A, B, C) by

using only one 7410 IC.

III-3-5) Suppose you have the simplified circuit as shown in the following figure,

connect the simplified circuit without disconnecting the other original one. Again, verify

its truth table.

A B C B' AB' AC F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

III-3-6) Compare the results obtained in III-3-2) and III-3-5).

III-3-7) What do you observe if inverters 7404 are available?

EE 210. LOGIC DESIGN LAB. - toile-libre.orgmyreader.toile-libre.org/uploads/My_525172a33a5cd.pdf · 2 EE 210: Logic Design Lab. ... NAND and NOR gates. II-2 Materials & Components

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