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CMOS Device, Inverter, CMOS Device, Inverter, Combinational circuit Logic and LayoutCombinational circuit Logic and Layout
Part 3 Part 3 Combinational Logic GatesCombinational Logic Gatesgg(textbook chapter 6)(textbook chapter 6)
19/18/2008 GMU, ECE 680 Physical VLSI Design
Combinational vs. Sequential Logic
Combinationali O tI
Combinationali
OutInLogicCircuit
OutIn LogicCircuit
C bi ti l S ti l
State
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
2
p f(In) p ( , )
9/18/2008 GMU, ECE 680 Physical VLSI Design
Static CMOS Circuit
At every point in time (except during the switching y p ( p g gtransients) each gate output is connected to eitherVDD or Vss via a low-resistive path.
Th t t f th t t ll ti th lThe outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on therelies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
Transistor Sizing a Complex CMOSTransistor Sizing a Complex CMOS Gate
A
B
C4
8
3
6
D
C
4
8
6
6
OUT = D + A • (B + C)
A 2
D
B C
1
2 2
149/18/2008 GMU, ECE 680 Physical VLSI Design
Fan‐In ConsiderationsFan In Considerations
DCBA
B
A CL
C3
Distributed RC model(Elmore delay)
D
C
C3
C2
C
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a f i f f i d i ll i hD C1 function of fan‐in – quadratically in the worst case.
159/18/2008 GMU, ECE 680 Physical VLSI Design
tp as a Function of Fan‐Inp
1250
Gates with a fan‐in 1000
quadratic
(psec)
greater than 4 should be avoided.
500
750
tpHL tp
tpLH
t p
250linear
fan‐in
02 4 6 8 10 12 14 16
16
tp as a Function of Fan‐Outp
All t h th
tpNOR2
All gates have the same drive current.
tpNAND2
(psec)
tpINV
t p Slope is a function of “driving strength”
2 4 6 8 10 12 14 16eff fan‐out
17
eff. fan out
Dynamic CMOSDynamic CMOS
• In static circuits at every point in time (except when y p ( pswitching) the output is connected to either GND or VDD via a low resistance path.
f i f i 2 ( N P ) d i– fan‐in of n requires 2n (n N‐type + n P‐type) devices
• Dynamic circuits rely on the temporary storage of• Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.– requires on n + 2 (n+1 N‐type + 1 P‐type) transistors
189/18/2008 GMU, ECE 680 Physical VLSI Design
Dynamic GateDynamic Gate
MpClk
Out Out
Clk Mp
In1In2 PDN
In3
CLA
BC
3
MeClk
Clk
B
Me
Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
199/18/2008 GMU, ECE 680 Physical VLSI Design
Dynamic GateDynamic Gate
offMpClk
Out Out
Clk Mpon 1
off
((AB)+C)In1In2 PDN
In3
CLA
BC
((AB)+C)
3
MeClk
Clk
B
Me
offon
Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)
209/18/2008 GMU, ECE 680 Physical VLSI Design
Properties of Dynamic GatesProperties of Dynamic Gates
• Logic function is implemented by the PDN onlyg p y y– number of transistors is N + 2 (versus 2N for static complementary CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)
• Non‐ratioed ‐ sizing of the devices does not affect the logic levels
• Faster switching speeds– reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)– reduced load capacitance due to smaller output loading (Cout)
– no Isc, so all the current provided by PDN goes into discharging CL
219/18/2008 GMU, ECE 680 Physical VLSI Design
Properties of Dynamic Gatesp y
• Overall power dissipation usually higher than static CMOS– no static current path ever exists between VDD and GND (including P )(including Psc)
– no glitching– higher transition probabilities– extra load on Clk
• PDN starts to work as soon as the input signals exceed V V V d V l VVTn, so VM, VIH and VIL equal to VTn
– low noise margin (NML)
N d h / l t l k
22
• Needs a precharge/evaluate clock
9/18/2008 GMU, ECE 680 Physical VLSI Design
Issues in Dynamic Design 2: Charge Sharing
Clk Mp
Charge stored originally on CL is redistributed (shared) over CL and CAleading to reduced robustness
CLA
Outleading to reduced robustness
Clk
CA
CB
B=0
Me
239/18/2008 GMU, ECE 680 Physical VLSI Design
Charge Sharing ExampleCharge Sharing Example
f
Clk
A AOut
CL=50fFA A
B B B !BCa=15fF C =15fFB !B
CC
a
Cc=15fF
Cb=15fF
Cd=10fF
Clk
249/18/2008 GMU, ECE 680 Physical VLSI Design
Charge SharingCharge Sharingcase 1) if ΔVout < VTn