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Memory ClassificationMemory ClassificationMemory Architectures The Memory Core Periphery Periphery Reliability Case Studies
2GMU, ECE 680 Physical VLSI Design
Semiconductor Memory Classificationy
Read-Write MemoryNon-VolatileRead-Write
MemoryRead-Only Memory
EPROM
E2PROM
RandomAccess
Non-RandomAccess Mask-Programmed
Programmable (PROM)
FLASHSRAM
DRAM
Programmable (PROM)
FIFO
LIFODRAMShift Register
CAM
3GMU, ECE 680 Physical VLSI Design
Memory Timing: Definitionsy g
Read cycle
Write cycle
y
READ
Write cycleRead access Read access
WRITE
Write accessData valid
DATA
Data written
DATA
4GMU, ECE 680 Physical VLSI Design
Memory Architecture: DecodersM bits M bits
S0 S0Word 0
Word 1
Word 2 Storagecell
S0
S1
S2A0
A1
Word 0
Word 1
Word 2 Storagecell
0
Word N2 2Nwords
SN2 2AK2 1
SWord N2 2
Decoder
Word N2 1K 5 log2N
SN2 1 Word N2 1
Input-Output(M bits)
Intuitive architecture for N x M memoryToo many select signals: K l N
Decoder reduces the number of select signals
Input-Output(M bits)
Too many select signals:N words == N select signals K = log2N
5GMU, ECE 680 Physical VLSI Design
Array‐Structured Memory Architecture
Bit line2L 2 KStorage cell
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Dec
oder
Word line
AK
AK1 1R
owAL 2 1
M.2K
A0
M.2
Sense amplifiers / Drivers Amplify swing torail-to-rail amplitude
0
AK2 1Column decoder
Input-Output
Selects appropriateword
p p(M bits)
6GMU, ECE 680 Physical VLSI Design
Hierarchical Memory ArchitectureBlock 0
Rowdd
Block i Block P 2 1
address
Columnaddress
Blockaddress
Globalamplifier/driver
Controlcircuitry
Global data busBlock selector
Advantages:Advantages:1 Sh t i ithi bl k1 Sh t i ithi bl k
I/O
1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings
7GMU, ECE 680 Physical VLSI Design
Block Diagram of 4 Mbit SRAMClock
generatorZ ‐addressbuffer
X ‐addressbuffer
Subglobal row decoderBlock 30 128 K Array Block 0
Predecoder and block selectorBit line load
Subglobal row decoder
Global row d d
Subglobal row decoderBlock 31 Block 1
decoder
Transfer gateColumn decoder
Sense amplifier and write driver Local ro decoder
CS, WEbuffer
I/Obuffer
Y ‐addressbuffer
X ‐addressbuffer
x1/x4controller
Sense amplifier and write driver Local row decoder
Static power dissipation -- Want R L largeBit lines precharged to V DD to address t p problemp
43GMU, ECE 680 Physical VLSI Design
SRAM Characteristics
44GMU, ECE 680 Physical VLSI Design
Page 663
3‐Transistor DRAM Cell
WWL
BL 1 BL 2
RWL
WWL
WWL
M3
RWL
VDD
VDD -VT
BL 1
XM1 XM2
C S
ΔVVDD -VTBL 2
No constraints on device ratiosReads are non‐destructiveValue stored at node X when writing a “1” = V VValue stored at node X when writing a 1 = VWWL ‐VTn
45GMU, ECE 680 Physical VLSI Design
3T‐DRAM — Layout
BL2 BL1 GND
RWLM3M3
M2
WWLM1
46GMU, ECE 680 Physical VLSI Design
Area: 50% of 6‐T SRAM
1‐Transistor DRAM CellWL
BL
WLWrite 1 Read 1
M1
CS
VDD 2 VTX GND
V
CBL
sensing
BLVDD
VDD /2 VDD /2
Write: C S is charged or discharged by asserting WL and BL.
BL
Write: C S is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
V BL VPRE– VBIT VPRE–CS
CS CBL+------------= =V
Voltage swing is small; typically around 250 mV.
47GMU, ECE 680 Physical VLSI Design
DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read‐out.
DRAMmemory cells are single ended in contrast to SRAM cells DRAM memory cells are single ended in contrast to SRAM cells.
The read‐out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.
Unlike 3T cell 1T cell requires presence of an extra capacitance that must be explicitly Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD