ECE 667 - Synthesis & Verification 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Retiming.

ECE 667 - Synthesis & Verification1

ECE 667ECE 667

Synthesis and Verificationof Digital Systems

Retiming


RetimingRetiming

Outline:

• Problem– sequential synthesis

• Formulation

• Retiming algorithm


Optimizing Sequential Circuits by Optimizing Sequential Circuits by Retiming Gate-level NetlistRetiming Gate-level Netlist

Netlist of gates and registers:

Various Goals:– Reduce clock cycle time– Reduce area

• Reduce number of latches (registers)

InputsInputs

OutputsOutputs


RetimingRetimingProblem

– Pure combinational optimization can be myopic since relations across register boundaries are disregarded

Solutions– Retiming: Move register(s) so that

• clock cycle decreases, or number of registers decreases and

• input-output behavior is preserved

– Peripheral retiming: Combine retiming with combinational optimization techniques

• move latches out of the way temporarily• optimize larger blocks of combinational logic


Circuit RepresentationCircuit Representation

[Leiserson, Rose and Saxe (1983)]

Circuit representation: G(V,E,d,w)– V set of gates– E set of wires– d(v) = delay of gate/vertex v, (d(v)0)– w(e) = number of registers on edge e, (w(e)0)


Circuit RepresentationCircuit Representation

ExampleExample:: Correlator Correlator

CircuitCircuit

(x, y) = 1 if x=y0 otherwise

Operation delayOperation delay

33

++ 7 7Every cycle in the graph has at least one register,

i.e., there are no combinational loops.

00

33 33

00

0000

0022

Graph (Directed)

77

aa bb

++

HostHost


PreliminariesPreliminaries

For a path p :

Clock cycle c:

1

0

0

)()(

)()(

k

ii

k

ii

ewpw

vdpd endpoints) (includes

: ( ) 0max { ( )}p w p

c d p

For the correlator circuit: c = 13For the correlator circuit: c = 13

Can we reduce it to 7 ? Can we reduce it to 7 ? How ?How ?

Path with Path with

w(p)=0w(p)=000

33 33

00

0000

0022

77

0 11

0 1 1

ke ee

k kv v v v


• Movement of registers – from input to output of a gate or vice versa

• Does not affect gate functionalities

• A mathematical definition: retardation – r: V Z, an integer vertex labeling

– wr(e) = w(e) + r(v) - r(u) for edge e = (u,v)

Basic OperationBasic Operation

Retime by 1

Retime by -1


In the example, r(u) = -1, r(v) = -1 results in

• For a path p: s t, wr(p) = w(p) + r(t) - r(s)

• Retardation – r : VZ, an integer vertex labeling

– wr(e) = w(e) + r(v) - r(u) for edge e = (u,v)

– A retiming r is legal if wr(e) 0, eE (prove it !)

Basic OperationBasic Operation

vu0

3 3

0

00

02

7

0

vu0

3 3

0

11

1

7


Retiming for Minimum Clock CycleRetiming for Minimum Clock Cycle

Problem Statement: (minimum cycle time)

Given G (V, E, d, w), find a legal retiming r so that

is minimized

Retiming: 2 important matrices• Register weight matrix

• Delay matrix

: ( ) 0max { ( )}rp w p

c d p

( , ) min{ ( ) : }p

pW u v w p u v

( , ) max{ ( ) : , ( ) ( , )}p

pD u v d p u v w p w u v


Retiming for Minimum Clock CycleRetiming for Minimum Clock Cycle

WWV0 V1 V2 V3V0 V1 V2 V3

V0V0V1V1V2V2V3V3

0 2 2 20 2 2 20 0 0 00 0 0 00 2 0 00 2 0 00 2 2 00 2 2 0

c c p, if d(p) p, if d(p) then w(p) then w(p) 1 1

DDV0 V1 V2 V3V0 V1 V2 V3

V0V0V1V1V2V2V3V3

0 3 60 3 6 13 1313 13 3 63 6

131310 13 10 13 3 3

101077 10 13 10 13 77

W = register W = register path path weight weight matrixmatrix (minimum # latches on all (minimum # latches on all paths between u and v)paths between u and v)

D = D = pathpath delay matrix delay matrix (maximum delay on all (maximum delay on all paths paths between u and v)between u and v)

v2v2v1v1

v0 00

33 33

00

0000

0022

77v3v3

Delays exceeding Delays exceeding 7 shown in 7 shown in redred


Conditions for Legal RetimingConditions for Legal RetimingAssume that we are asked to check if a retiming exists for a clock cycle

Legal retiming: wr(e) 0 for all e. Hence

wr(e) = w(e) + r(v) - r(u) 0 orr (u) - r (v) w (e)

For all paths p: u v such that d(p) , we require wr(p) 1

– Thus1

0

1

10

0

1 ( ) ( )

[ (

( ) ( ) (

) ( ) ( )]

( ) ( )

)

( )

k

r r ii

k

i i ii

k

w p w e

w e r v

w p r

r v

w p r v v

r u

r

v

Or take the least w(p) (tightest constraint) r(u)-r(v) W(u,v)-1

Note: this is independent of the path from u to v, so we just need to apply it to u, v such that D(u,v)


• All constraints in difference-of-2-variable form • Related to longest/shortest path problem

Solving the ConstraintsSolving the Constraints

Correlator: Correlator: = 7

Legal: Legal: r(u)-r(v)r(u)-r(v)w(e)w(e)

0)()(0)()(0)()(0)()(2)()(

03

32

31

21

10

vrvrvrvrvrvrvrvrvrvr

1)()(1)()(1)()(1)()(1)()(1)()(1)()(1)()(

23

13

32

12

02

31

01

30

vrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvr

Timing D>7:Timing D>7:r(u)-r(v)r(u)-r(v)W(u,v)-1W(u,v)-1


V0V0V1V1V2V2V3V3

0 2 2 20 2 2 20 0 0 00 0 0 00 2 0 00 2 0 00 2 2 00 2 2 0

V2V2v1v1

v0v0 00

33 33

00

0000

0022

77v3v3


V0V0V1V1V2V2V3V3

0 3 60 3 6 13 1313 13 3 63 6

131310 13 10 13 3 3

101077 10 13 10 13 77


• Do shortest path on constraint graph: (O(|V|3 )).• A solution exists if and only if there exists no negative weighted cycle.

Solving the ConstraintsSolving the Constraints

Legal: Legal: r(u)-r(v)r(u)-r(v)w(e)w(e)

0)()(0)()(0)()(0)()(2)()(

03

32

31

21

10

vrvrvrvrvrvrvrvrvrvr

1)()(1)()(1)()(1)()(1)()(1)()(1)()(1)()(

23

13

32

12

02

31

01

30

vrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvr

Timing D>7:Timing D>7:r(u)-r(v)r(u)-r(v)W(u,v)-1W(u,v)-1

A solution:A solution: r(v0) = r(v3) = 0, r(v1) = r(v2) = -1

r(1)r(1)r(0)r(0)

r(3)r(3)r(2)r(2)

00

11 11

11

11

11

-1-1

-1-1

-1-1

0,-10,-1

0,-10,-1

00

00-1-1

22

Constraint graphConstraint graph


RetimingRetimingTo find the minimum cycle time, do a binary

search among the entries of the D matrix (0(V3

logV))

RetimeRetime

Retimed correlator:Retimed correlator:

v0v0

V2V2v1v1

00

33 33

00

0000

0022

77

Clock cycleClock cycle = 3+3+7=13= 3+3+7=13

aa bb

++

HostHost

Clock cycle = 7Clock cycle = 7

aa bb

++

HostHost


V0V0V1V1V2V2V3V3

0 2 2 20 2 2 20 0 0 00 0 0 00 2 0 00 2 0 00 2 2 00 2 2 0


V0V0V1V1V2V2V3V3

0 3 60 3 6 13 1313 13 3 63 6

131310 13 10 13 3 3

101077 10 13 10 13 77


1. Relaxation based: – Repeatedly find critical path; – retime vertex at end of path by +1 (O(VElogV))

2. Also, Mixed Integer Linear Program formulation

Retiming: two more AlgorithmsRetiming: two more Algorithms

++11

uuCritical pathCritical path

vv


Relaxation Algorithm - RationaleRelaxation Algorithm - Rationale


Relaxation Algorithm Relaxation Algorithm


Relaxation Algorithm – step 1Relaxation Algorithm – step 1

Retime for Retime for = 13 = 13



Retime for Retime for = 13 = 13



Retimed for Retimed for = 13 = 13


Relaxation Algorithm – summaryRelaxation Algorithm – summary(Retiming for (Retiming for = 13)= 13)


Retiming for Minimum AreaRetiming for Minimum Area(Minimum # Latches)(Minimum # Latches)

Goal: minimize the number of registers used

:

:

min ( )

( ( ) ( ) ( ))

( ) ( ( ) ( ))

( ( ) ( ))

( )(# ( ) # ( )

( )

r re E

e u v

e E e u v

u v

v V

Vv V

N w e

w e r v r u

w e r v r u

N r v r u

N r v fanin v fanout v

N a r v

where av is a constant for each node v.


Minimize:

Minimum Registers - FormulationMinimum Registers - Formulation

( )vv V

a r v

Subject to:Subject to: wr(e) = w(e) + r(v) - r(u) 0

• Reducible to a flow problem

ECE 667 - Synthesis & Verification 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Retiming.

Documents

synthesis verification

legal retiming r

clock cycle legal retiming

retiming outline

peripheral retiming

minimized retiming

edge e

red slide