EE141 1 667 - Synthesis and Verification ECE 697B (667) ECE 697B (667) Fall 2004 Fall 2004 Synthesis and Verification of Digital Circuits Design Styles and Methodologies Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003 Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003
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ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Circuits
ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Circuits. Design Styles and Methodologies. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003. Digital Circuit Implementation Approaches. Custom. Semicustom. Cell-based. Array-based. Standard Cells. - PowerPoint PPT Presentation
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EE1411
ECE 667 - Synthesis and Verification
ECE 697B (667)ECE 697B (667)Fall 2004Fall 2004
Synthesis and Verificationof Digital Circuits
Design Styles and Methodologies
Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003
EE1412
ECE 667 - Synthesis and Verification
Implementation ChoicesImplementation Choices
Custom
Standard CellsCompiled Cells Macro Cells
Cell-based
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches
EE1413
ECE 667 - Synthesis and Verification
The Custom Approach The Custom Approach
Intel 4004
Courtesy Intel
EE1414
ECE 667 - Synthesis and Verification
Transition to Automation and Regular StructuresTransition to Automation and Regular Structures
Breathing Some New Life in PLAsBreathing Some New Life in PLAsRiver PLAs A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing.
PRE-CHARGE
PR
E-
CH
AR
GE
PRE-CHARGE
PR
E-C
HA
RG
E
BUFFER
BUFFER
BU
FF
ER
BU
FF
ER
PRE-CHARGE
PR
E-C
HA
RG
E
BUFFER
BU
FF
ER
PRE-CHARGE
PR
E-
CH
AR
GE
BUFFERB
UF
FE
R
• No placement and routing needed. • Output buffers and the input buffers
of the next stage are shared.
Courtesy B. Brayton
EE14116
ECE 667 - Synthesis and Verification
Experimental ResultsExperimental Results
Layout of C2670
Network of PLAs, 4 layers OTC
River PLA,2 layers no additional routing
Standard cell, 2 layers channel routing
Standard cell,3 layers OTC
0.2
0.6
1
1.4
0 2 4 6 area
dela
y
SC N PLA R PLA
Area: RPLAs (2 layers) 1.23 SCs (3 layers) - 1.00, NPLAs (4 layers) 1.31 DelayRPLAs 1.04SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.
Also: RPLAs are regular and predictable
EE14117
ECE 667 - Synthesis and Verification
MacroModulesMacroModules
25632 (or 8192 bit) SRAMGenerated by hard-macro module generator
EE14118
ECE 667 - Synthesis and Verification
““Soft” MacroModulesSoft” MacroModules
Synopsys DesignCompiler
EE14119
ECE 667 - Synthesis and Verification
““Intellectual Property”Intellectual Property”
A Protocol Processor for Wireless
EE14120
ECE 667 - Synthesis and Verification
Semicustom Design FlowSemicustom Design Flow
HDLHDL
Logic SynthesisLogic Synthesis
FloorplanningFloorplanning
PlacementPlacement
RoutingRouting
Tape-out
Circuit ExtractionCircuit Extraction
Pre-Layout Simulation
Pre-Layout Simulation
Post-Layout Simulation
Post-Layout Simulation
StructuralStructural
PhysicalPhysical
BehavioralBehavioralDesign Capture
Des
ign
Iter
atio
nD
esig
n It
erat
ion
EE14121
ECE 667 - Synthesis and Verification
The “Design Closure” ProblemThe “Design Closure” Problem
Courtesy Synopsys
Iterative Removal of Timing Violations (white lines)
EE14122
ECE 667 - Synthesis and Verification
Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design