ECE 415/515 –ANALOG INTEGRATED CIRCUIT DESIGN FULLY-DIFFERENTIAL OPAMP DESIGN AND SIMULATION © Vishal Saxena
ECE 415/515 –ANALOG INTEGRATED CIRCUIT DESIGN
FULLY-DIFFERENTIAL OPAMP DESIGN AND SIMULATION
© Vishal Saxena
OPAMP DESIGN PROJECT
VCM
vin/2
-vin/2
R1
R1
R2
R2
CL
CL
VCMvout
VCM
vin
CL
RL
vout
(a) (b)
ECE415/EO ECE515
© Vishal Saxena 2017
FULLY-DIFFERENTIAL (FD) OPAMPS
• Differential output is 𝑣𝑜𝑢𝑡 = 𝑣𝑜𝑝 − 𝑣𝑜𝑚 for differential
input 𝑣𝑖𝑛 = 𝑣𝑖𝑛𝑝 − 𝑣𝑖𝑛𝑚
• Common-mode (CM) output is 𝑣𝑜𝑢𝑡,𝐶𝑀 =𝑣𝑜𝑝+𝑣𝑜𝑚
2
• Output CM-level must be held constant to a well-
defined value (VCM)
• Common-mode feedback (CMFB) loop to control the output CM-level
• Implemented using continuous-time (CT) or using switched-capacitor (SC) circuits
CMFB
VCM
VCMFB
CL
CLvinm
vinp
vop
vom
CMFB: BASIC IDEA
CMFB loop compensation CM equivalent circuit
CMFB
VCM
VCMFB
CL
CLvinm
vinp
vop
vom
VDD VDD
vinp vinm
vopvom
VCMVCMFB
VDD
vin,CMM1 M2
M3 M4
M5 M6
VbiasnVbiasn
Cc,CM
VCM
vo,CM=M1,2
M5,6
M3,4
1
2
(a) (b)
CM
Detector
Cc,CM
VCMFBvop+vom
2
vop+vom
2
CMFB
CMFB
CM
Detector
RESISTIVE CM-DETECTOR
• Resistance (RCM) averaging circuit senses 𝑣𝑜𝑢𝑡,𝐶𝑀 =
𝑣𝑜𝑝+𝑣𝑜𝑚
2
• A capacitive averaging network
(CCM) in parallel for high-frequency
averaging
• Mitigates bandwidth limitation due to RCMCin,p
• 𝑣𝑜,𝑐𝑚 =𝑣𝑜𝑝+𝑣𝑜𝑚
2
2𝐶CM
2𝐶CM+𝐶
1
• 𝑖𝑐1 =𝑔𝑚𝑐1
2𝑣𝑜,𝑐𝑚 − 𝑉𝐶𝑀 Resistive CM-detector
with error amplifier CM equivalent circuit
vo,CM
(b)
CCM
VCM
VCMFB
RCM CCM
vop
vom
RCM/2
2CCM
vo,CM
VCM
ACM ACM
RCM
(a)
VCMFB
VDD VDD
Mc1 Mc2
Mc4
VCMFB
Vbiasn
Mc3
Mc0
VCMvo,CM
RESISTIVE CM-DETECTOR: COMPENSATION 1
• Miller compensation of the CMFB loop using Cc,CM
• Two ways to place the compensation cap between nodes 1 and 2.
CMFB loop compensation CM equivalent circuitUnlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
vinp vinm
vopvom
VDD
vin,CMM1 M2
M3 M4
M5 M6
Vbiasn
Vbiasn
vo,CM
M1,2
M5,6
M3,4
1
2
(a) (b)
RCM CCM
VCM
VCMFB
RCM CCM
vop
VCMFB
vom
Cc,CM
RCM/2
2CCM
vo,CM
VCM
VCMFB
Cc,CM
ACM
ACM
RESISTIVE CM-DETECTOR: COMPENSATION 2
• Note that zero-nulling resistor is not shown in these slides, but is used in
designs
CMFB loop compensation CM equivalent circuitUnlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
vinp vinm
vopvom
VDD
vin,CMM1 M2
M3 M4
M5 M6
Vbiasn
Vbiasn
vo,CM
M1,2
M5,6
M3,4
1
2
(a) (b)
RCM CCM
VCM
VCMFB
RCM CCM
vop
VCMFB
vom
RCM/2
2CCM
vo,CM
VCM
VCMFB
Cc,CM
Cc,CM/2 Cc,CM/2
ACM
ACM
DUAL-DIFF-PAIR (DDP) CM-DETECTOR
▪ 𝑖𝑐1 =𝑔𝑚𝑐1
2(𝑣𝑜𝑝+𝑣𝑜𝑚
2) − 𝑉𝐶𝑀
▪ =𝑔𝑚𝑐1
2
𝑣𝑜𝑝
2−
𝑉𝐶𝑀
2+
𝑔𝑚𝑐1
2
𝑣𝑜𝑚
2−
𝑉𝐶𝑀
2
▪ =𝑔𝑚𝑐1
4𝑣𝑜𝑝 − 𝑉𝐶𝑀 +
𝑔𝑚𝑐1
4(𝑣𝑜𝑚 − 𝑉𝐶𝑀)
Diff-pair Diff-pair
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VCMFB
VCM VCMvomvop
5
25
2
5
2
5
2
Vbiasn
VCMFBVCM
vop
vom
Symbol
(a) (b)
5
2 5
2
Mc11
2
Mc01
2
ACM
Quiz: Diff-How does the dual diff-pair (DDP) look in CM-equivalent circuit?
DUAL-DIFF-PAIR CMFB COMPENSATION
CMFB loop compensation
CM equivalent circuitUnlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
vinp vinm
vop
vom
Cc,CM/2
VCM
VCMFB
VDD
vin,CMM1 M2
M3 M4
M5 M6
Vbiasn
Vbiasn
Cc,CM
Cc,CM/2
VCM
vo,CM
M1,2
M5,6
M3,4
1
2
(a) (b)
ACM
ACM
ASIDE: TWO-STAGE LOOP STABILITY (1)
• Two-stage feedback loop should ensure overall negative feedback
• Only one gain-stage can be negative
• Two possible configurations by interchanging polarities
Cc
Gm2
Gm1
C1
C2
vd
vd
vin
vin
voutvout
ASIDE: TWO-STAGE LOOP STABILITY (2)
• From loop-analysis, the negative transconductance should have larger Gm for
stability (Important!)
Cc
Gm2
Gm1
C1
C2
vout
Cc
Gm2
Gm1
C1
C2
vout
+ve gain
-ve gain
-ve gain
+ve gain
Doesn’t work if
Gm2>Gm1
• Results in LHP poles if Gm2>Gm1 • Results in RHP pole(s) if Gm2>Gm1. Unstable!
CMFB LOOP STABILITY (1)
CM equivalent circuit
VDD
vin,CM
Vbiasn
Cc,CM
VCM
vo,CM
M1,2
M5,6
M3,4
1
2
(a)
ACMCc,CM
Gmc
Gm1
C1
C2
(b)
• We have 𝐺𝑚𝑐 < 𝐺𝑚1 by design
(Ic0=I0/n)
• Gm1 should have negative
polarity for stability!
• Gmc would have positive gain
across it
• Overall negative feedback in
the CMFB loop
Reduced circuit
Gm1>Gmc
CMFB LOOP STABILITY (2)
CM equivalent circuit
VDD
vin,CM
Vbiasn
Cc,CM
VCM
vo,CM
M1,2
M5,6
M3,4
1
2
(a)
ACMCc,CM
Gmc
Gm1
C1
C2
(b)
• CMFB unity-gain frequency
𝜔𝑢,𝐶𝑀𝐹𝐵 ≈𝐺𝑚𝑐𝐶𝐶,𝐶𝑀
• Note that here Gmc≡gm1 and
Gm1≡gm2 in the pole-splitting
equations, as we had gm2>gm1 in
the pole-splitting derivation
• The CMFB loop-gain
𝐴𝑣,𝐶𝑀 = 𝐺𝑚𝑐𝑅𝑐𝐺𝑚1𝑅1
• Should be large enough to ensure
small DC error
Reduced circuit
Gm1>Gmc
SIZING OF THE CMFB ERROR AMPLIFIER
• The error amplifier circuit should be
a replica of the gain stage
• Bias current Ic0 and widths are
scaled down to save power (Ic0=I0/n)
• Both the stages should have the
same current density
•𝐼0/2
𝑊3,4=
𝐼𝑐0/2
𝑊𝑐3,4
• Ensures that M3,4 and Mc3,4 will have
the same VSG values
• Otherwise, any mismatch in bias
voltages will lead to systematic offset
in the CMFB loop
VDD VDD
vip vim
vopvom
M1 M2
M3 M4
VCMFB
M0
Vbiasn
VDD VDD
VCMMc1 Mc2
Mc3 Mc4
Mc0
VbiasnI0 Ic0
RCM
CCM
RCM
CCM
vop
vom
vo,CM
SIZING OF THE DDP CM-DETECTOR
• Same ideas for the DDP
CM-detector
• Both stages should have
the same current density
•𝐼0/2
𝑊3,4=
𝐼𝑐0/2
𝑊𝑐3,4
• Ensures that M3,4 and
Mc3,4 will have the same
VSG values
• Otherwise, any mismatch
in bias voltages will lead
to systematic offset in the
CMFB loop
VDD VDD
vip vim
vopvom
M1 M2
M3 M4
VCMFB
M0
VbiasnI0
VDD VDD
VCM VCMvomvop
Vbiasn
Mc1
Mc0Ic0
1
2Ic0
1
21
2
1
2
Mc3
COMPARISONResistive CM Detector
• Unrestricted input range
• Rail-to-rail operation ☺
• RCM loads the differential gain stage
and reduces its gain
Dual-Diff-Pair CM Detector
• Limited by input CMR of the diff-pair
• Allows very limited voltage swing
• Only small capacitive load ☺
VDD VDD
VCMFB
VCM VCMvomvop
5
25
2
5
2
5
2
Vbiasn
(a)
5
2 5
2
Mc11
2
Mc01
2
CCM
VCM
VCMFB
RCM CCM
vop
vom
vo,CM
ACM
RCM
TWO-STAGE FULLY-DIFFERENTIAL
OPAMPS
TWO-STAGE FD OPAMP
• What is the best strategy to set the CM-level at the output of both gain stages?
Block Diagram
VDD VDD
vim vip
vom1
M1 M2
M3 M4
M0L M0R
Vbiasn
VDD
vop
M5
M6
vop1
VDD
vom
M7
M8
I0I0 I2I2
Cc,DMCc,DM
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
TWO-STAGE FD OPAMP CMFB (1)
• Employ individual CMFB loops for each of the gain stages (robust scheme)
• 1st stage (high-gain) mustn’t be loaded → Dual diff-pair CM-detector
• 2nd stage should allow large output swing → Resistive CM-detector
Block Diagram
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
CMFB1
VCM1
VCMFB1
CMFB2
VCM2
VCMFB2
TWO-STAGE FD OPAMP CMFB (2)
• What are the reasonable voltages for VCM1 and VCM2?
• VCM1 sets the bias for the second gain stage (=Vbiasp in our example)
• VCM2 is the output CM-level and is dictated by the overall application circuit
• VDD/2 is commonly used to allow maximum output swing
Block Diagram
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
CMFB1
VCM1
VCMFB1
CMFB2
VCM2
VCMFB2
TWO-STAGE FD OPAMP CMFB (3)
VDD VDD
vim vip
vom1
M1 M2
M3 M4
M0L M0R
Vbiasn
VDD
vop
M5
M6
vop1
VDD
vom
M7
M8
I0I0 I2I2
Cc,DMCc,DM
Cc,C
M1/2
VC
M1
Cc,C
M1/2
CCM
VCM2
VCMFB2
RCM
CCM
vo,CM
RCM
VCMFB1
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
CMFB1
VCM1
VCMFB1
CMFB2
VCM2
VCMFB2
Block Diagram
TWO-STAGE FD OPAMP: SINGLE-LOOP CMFB (1)
• What if we just have one CMFB loop wrapped around both the gain stages?
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
CMFB
VCM
VCMFB
Block Diagram
VDD VDD
vim vip
vom1
M1 M2
M3 M4
M0L M0R
Vbiasn
VDD
vop
M5
M6
vop1
VDD
vom
M7
M8
I0I0 I2I2
Cc,DMCc,DM
VCMFB
VCM
RCM
CCM
vomvop RCM
CCM
Vbiasn
TWO-STAGE FD OPAMP: SINGLE-LOOP CMFB (2)• 3 low-frequency poles in the CM-
equivalent circuit
• Need to compensate like a three-stage
Opamp (higher complexity)
• Solution: Get rid of one of the high-
impedance nodes to move the pole to
higher frequencies
VDD
vip M1,2
M3,4
M0
Vbiasn
VDD
M5,7
M6,8
Cc,DM
VCMFB
2
RCM/2
2CCM
VCM
ACM
1
3
Common-mode Equivalent Circuit
TWO-STAGE FD OPAMP: SINGLE-LOOP CMFB (3)• Use diode-connected load in the
error amp
• low gain, ACM~1
• Only two low-f poles ☺
• Loop provides large CMFB gain
• DM compensation caps compensate
the CMFB as well
• Only control knob is n: Ic0=I0/n
• See notes for detailed analysis
• Use same current density in the error
amp, as the two gain stages
• Not as robust against PVT variationsCommon-mode
Equivalent Circuit
VDD
vip M1,2
M3,4
M0
Vbiasn
VDD
M5,7
M6,8
2Cc
VCMFB
2
RCM/2
2CCM
1
VDD VDD
VCMMc1 Mc2
Mc3 Mc4
Mc0
VbiasnIc0
I0 I2
TWO-STAGE CLASS-AB FD OPAMPS (1)VDD VDD
vim vip
vom1
M1 M2
M3 M4
M0L M0R
Vbiasn
VDD
vop
M5
M9
vop1
Cc,DMVDD
M8
VDD
vom
M10
M14
Cc,DMVDD
M13
M7
M6
M12
M11
I2
I0Ix
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
Block Diagram
• Note the crisscross biasing for the pseudo Class-AB (push-pull) output stage
• Diode-connected M7,12 are added to decouple VGS9,14 from M6,11
• Ix is minimized to save power (but use same current density in all branches)
TWO-STAGE CLASS-AB FD OPAMPS (2)• 1st stage CM-level can be set
using the DDP CM-detector
• How to set the output CM-
level for the 2nd stage?
• Note that the previous CMFB
method was suitable only for
Class-A stage!
• Need creative ways of controlling the output CM-level
VDD VDD
vim vip
vom1
M1 M2
M3 M4
M0L M0R
Vbiasn
VDD
vop
M5
M9
vop1
Cc,DMVDD
M8
VDD
vom
M10
M14
Cc,DMVDD
M13
M7
M6
M12
M11
I2
I0Ix
Cc,C
M1/2
VCM1
Cc,C
M1/2
VCMFB1
CLASS-AB STAGE CMFB METHODS• Several methods have been developed and tried
• Passive feedback using resistors
• CMFB based on Current-injection
• Triode-device based CMFB
• You can come up with your own!
CLASS-AB CMFB: CURRENT INJECTION (1)
vop
vom
vp
vm
vom1
vop1
Cc,DM
Cc,DM
CMFB2
VCM2
CMFB1
VCM1
VCMFB1
VCMFB1
• Two-independent CMFB loops
• Inject or remove DC current from the output stage to set its out CM-level
• Elegant scheme
Block Diagram
CLASS-AB CMFB: CURRENT INJECTION (2)VDD VDD
vim vip
vom1
M1 M2
M3 M4
M0L M0R
Vbiasn
VDD
vop
M5
M9
vop1
Cc,DMVDD
M8
VDD
vom
M10
M14
Cc,DMVDD
M13
M7
M6
M12
M11
2I2
I0
VDD VDD
M16 M15
vopvom
CCM
RCM
CCM
RCM
Cc,CM/2Cc,CM/2
VCMFB1
VCMFB2
1.5I2
VCM2
0.5I2 0.5I2
2I2
1.5I2
I0
• A ¼ current branch injects/removes current into/from the output nodes to
control their CM-level
• 3:1 DC current split for I2 used to avoid potential instability (see paper)
CLASS-AB CMFB: TRIODE-DEVICE (1)
• TBD
FULLY-DIFFERENTIAL OPAMP
SIMULATION
CMDM PROBE
• Located in Spectre library: AnalogLib→cmdmprobe
• Variable CMDM needs to be set in he model
▪ -1 measures differential mode response
▪ +1 measures common mode response
• In IC615, diffstbprobe is available which handles unbalanced differential circuits
better than the cmdmprobe.
• More information on the differential probes and the STB analysis algorithm can be
found in [4].
FULLY DIFFERENTIAL CIRCUIT ANALYSIS• Use CMDM probe for differential analysis [1, 3]
• Placement of the CMDM probe should break the differential as well the common-mode loop(s).
Vcmfb
CMFB
vCM
vop
vom
R2
R2
R1
R1 CL
CL
“analogLib/cmdmprobe”
CMDM = -1 measures DM
CMDM = 1 measures CM
FD CIRCUIT ANALYSIS SETUP 1• For internal loops, isolate those loops
individually and perform STB analysis
▪ Ensure overall DC feedback for accurate biasing, and ensure that all loops are compensated
▪ CMDM1 measures only the first-stage CM response
▪ CMDM2 measures overall DM response and second-stage CM response
Vcmfb1
CMFB1
vCM
vop
vom
R2
R2
R1
R1 CL
CL
vop1
vom1
A1 A2
Vcmfb2
CMFB2
CMDM1 CMDM2
CC
CC
Two-stage Opamp STB Analysis
FD CIRCUIT ANALYSIS SETUP 2• cmdmprobes placed outside DM
loop, only in CMFB loops
▪ CMDM1 measures only the first-stage CM response
▪ CMDM2 measures only the second-stage CM response
▪ But need another CMDM3 probe to measure DM loop stability
▪ Results match with iprobe results very well.
Vcmfb1
CMFB1
vCM
vop
vom
R2
R2
R1
R1 CL
CL
vop1
vom1
A1 A2
Vcmfb2
CMFB2
CMDM1 CMDM2
CC
CC
Two-stage Opamp STB Analysis
CMDM3
Fully Differential Opamp Schematic
Two-stage fully differential opamp Class AB output stage for large voltage swing With individual CMFB. 1st stage CMFB compensated
37
STB Analysis Using Method 1
Be noted that the nulling resistors should be connected before the inputs of cmdmprobe in the 1st CMFB loop, or it will generate incorrect results.
© Vishal Saxena and Venkatesh Acharya
38
STB Analysis Using Method 2
Need one extra cmdmprobe to measure DM loop comparing to method 1.
DM LOOP BODE PLOTS M1&M2
Differential Mode loop gain and phase margin plots Same results obtained by using Method 1 and Method 2
Method 1
1st Stage CMFB Loop Bode Plots
Method 2
2ND STAGE CMFB LOOP BODE PLOTS
Method 1 Method 2
SIMULATION SETUP
Use previous oppt (operating point) in the stb analysis
BODE PLOT SETUP
Results → Direct Plot → Main Form
DM TRANSIENT
Unity- gain inverting amplifier transient response with a 200mV differential step
(rise/fall time=0.1ns, pulse with=100ns)
CM TRANSIENT
Unity- gain inverting amplifier transient response with a 100mV common mode step (rise/fall
time=0.1ns, pulse with=100ns)
FULLY-DIFFERENTIAL OPAMP CMFB
EXAMPLES
REFERENCES1. The Designer’s Guide to SPICE and Spectre: http://www.designers-
guide.org/books/dg-spice/
2. Spectre User Simulation Guide, pages 160-165: http://www.designers-
guide.org/Forum/YaBB.pl?num=1170321868
3. M. Tian, V. Viswanathan, J. Hangtan, K. Kundert, “Striving for Small-Signal
Stability: Loop-based and Device-based Algorithms for Stability Analysis of
Linear Analog Circuits in the Frequency Domain,” Circuits and Devices, Jan
2001. http://www.kenkundert.com/docs/cd2001-01.pdf
4. https://secure.engr.oregonstate.edu/wiki/ams/index.php/Spectre/STB