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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Decoders
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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

Dec 31, 2015

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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices. Decoders. Previous…. Programmable Logic Devices PLAs PALs. Decoder. Multiple-input/multiple-output device. Inputs ( n ) are less than outputs ( m ). Converts input code words into output code words. - PowerPoint PPT Presentation
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Page 1: ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

ECE 3110: Introduction to Digital Systems

Chapter 6 Combinational Logic Design Practices

Decoders

Page 2: ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

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Previous…

Programmable Logic Devices PLAs PALs

Page 3: ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

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Decoder

Multiple-input/multiple-output device. Inputs ( n ) are less than outputs ( m ). Converts input code words into output

code words. One-to-One mapping :

- Each input code produces only one output code.

Input codes :- Binary Code- Your Code !

Output Codes1-out-of-m code Gray Code BCD Code

enable inputs

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Binary Decoder

n-to-2^n decoder : n inputs and 2^n outputs. Input code : n bit Binary Code. Output code : 1-out-of-2^n , One output is asserted for each

input code. Example : n=2, 2-to-4 decoder

Note “x” (don’t care) notation.

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Binary 2-to-4 decoder

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MSI 2-to-4 decoder

Input buffering (less load) NAND gates (faster)

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74x139 : Logic Symbol -Truth Table

G Y0

Y1

Y2

Y3

A

B

• Active Low Enable, Active Low outputs

• Truth Table Logic Symbol

Inputs OutputsG_L B A Y3 Y2 Y1 Y0 1 x x 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1

G_L

A

B

Y0_L

Y1_L

Y2_L

Y3_L

1/2 74x139

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Complete 74x139 Decoder

Page 9: ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

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3-to-8 decoder

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74x138 3-to-8-decoder symbol

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Decoder cascading

4-to-16 decoder

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More cascading

5-to-32 decoder

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Implementing the Canonical Sum

The binary decoder generates all minterms of n-variable logic function.

The canonical sum ( sum of minterms ) of a logic functions is obtained by adding all minterms of that function:

-Match the order of input bits-Activate Enable inputs

Example :

G2A

Y0

Y1

Y2

Y3

A

B

Z

Y

74x138

Y4

Y5

Y6

Y7CX

G2B

G1

FX Y Z

( , , ), ,

2 4 7F

+5V

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Logic design using Decoders

Advantages : - Flexibility- Multiple-output Logic functions

Disadvantages :- Complexity : for large number of inputs ( 5-variable Function with 3 minterms ! F= AB’CD’E + A’BC’DE+A’BCDE’ )

A practical alternative : PLD’s

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Decoder applications

Microprocessor memory systems selecting different banks of memory

Microprocessor input/output systems selecting different devices

Microprocessor instruction decoding enabling different functional units

Memory chips enabling different rows of memory depending on

address Lots of other applications

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Next…

Encoders

Reading Wakerly CH-6.5