E322

EEE / NTU X. ZHOU / 1995

E322/D(M4) – ENGINEERING DESIGN III

Design of a Semi-Custom IC

Dr Zhou Xing

School of Electrical and Electronic Engineering

Nanyang Technological University

SESSION 1995/96


Objectives ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Goal 1 — to study the various approaches to the design of a semi-custom IC

• To identify the characteristics used to categorize the different types of VLSImethodologies into full custom, semi-custom and standard design

• To classify a given IC into one of the above groups• To evaluate and decide on the most optimal design method to implement the

IC for a given case study• To describe the different stages of the design cycle• To identify an ASIC family• To summarize the main features of an FPGA architecture• To describe the FPGA development cycle

❏ Goal 2 — to deal with the design issues of a particular FPGA design fora 4-bit microprocessor

• To design the simple 4-bit microprocessor circuit using the basic buildingblocks available in the FPGA design tool environment

• To generate a test plan to test the circuit• To demonstrate familiarity with the various CAD packages used in the three

main stages of design entry, design verification and design implementation


Scope of the Course ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Microelectronic IC design

ASIC design

FPGA

Semi-custom IC design

4-bit microprocessor

❏ How do I implement (on hardware) a 4-bit microprocessor using FPGAsemi-custom IC design approach?

❏ How do I choose an appropriate design methodology if given aparticular system specification?


Structure of the Course ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Thinking

Q/A

NotesProject

Reading

Lecture

Group discussion

Design exercise

Quiz

Examination

Assignment


Outline of the Course ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Session 1

• Lecture (50')

Microelectronic ICand ASIC design

Break (10')

• Group discussion(50')

Break (10')

• Grouppresentation (50')

• Summary (10')

❏ Session 2

• Lecture (50')

Semi-customdesign and FPGA

Break (10')

• Group discussion(50')

Break (10')

• Grouppresentation (50')

• Summary (10')

❏ Session 3

• Design exerciseand discussion(50')

4-bitmicroprocessor

Break (10')

• Class discussion,Q/A (60')

Break (10')

• Quiz (50')


Assessment ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Continuous assessment

• Attendance

• Group discussion/presentation

• Assignments

• Quiz (45 minutes, close book)

• Design exercise (1 week)

❏ Final examination

• 2 hour, open book (two choose one)


Assignments ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Assignment 1

• List important terminologies, key concepts, methods of analysis, figures ofmerit and number ranges, etc., or anything else which you learned from thiscourse or other references

• Due: End of last session

❏ Assignment 2

• Ask a hypothetical question relevant to the subject of this course, and giveyour brief answer

• Due: Two days before the last session


Outline ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏✔ Microelectronic IC Design

❏ ASIC Design

❏ Semi-Custom IC Design

❏ Field-Programmable Gate Array

❏ 4-Bit Microprocessor Implementation


Spectrum of Approaches to Electronic Systems ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

The “Big Picture”

Physics Engineering

Behavioral

Structural

Functional

DD

MC Timing Switch Gate RTL

Electrical

Behavioral

Drift-diffusion

Relaxation-time approx

Monte Carlo

Quantummechanical

Semiclassical Device Circuit Logic

SystemCircuitDevice

RT

A

------------------

. . .

. . .

. . .

. . .

------------------

------------------

------------------

➚➚

➚

➚

➚

➚→

→

→


Motivation ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Question: Why so many levels of abstraction?

Electronic System:A “black box” which performs a

certain function based on the laws ofphysics of the “electrons”

S y s t e m

e lect ron

Input Output

❏ Answer:

“Everything should be made as simple as possible,

but not any simpler.”— Albert Einstein


The Art–Science Dichotomy of Design Activities ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Art

Science

Design

Perspective Tools

Innovation

Science

Decision making

Transformation

Art Human

Machine

KBES

CAD

? – Creativity

– Productivity

– Productivity

❏ Decision-making perspective: a creative process involving individualtalent, intuition, experience, etc.

❏ Transformation perspective: a process of successive transformationsof specifications from one domain (abstraction level) to another


Two Fundamental Approaches of a Design ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Top-down Bottom-up

Behavior

Synthesis Analysis

Vo

Vi

Vo

Vi

Structure Behavior

Vi

Vo

❏ Analysis

• Application of well-known principles to predict the behavior of a system

❏ Synthesis

• Selection of a solution from a number of alternatives based on a set of criteria

• An ensemble of answers waiting for the right question


Design Decisions ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

● What design decisions are to be made? ● How are they made?

❏ Software/hardware trade-offs

• Affect the flexibility of the product (need to modify the design in the future)

❏ Processing technology

• Figure of merit: gate delay, power consumption, noise immunity, logic capacity

❏ Implementation style

• Standard cells, gate arrays, programmable logic devices, etc.

❏ Choice of hardware algorithms

• Functional module designs in ROMs, RAMs, PLAs, etc., where regularity in thestructure can be captured and exploited in a procedural fashion

Note The first three decisions are largely influenced by marketing considerations such as designstandards, compatibility requirements, expendability, product lifetime, and other economic factors,which can be determined before the actual design starts. In contrast, It may be necessary to delaythe fourth decision due to uncertainties in meeting physical constraints such as chip area, powerconsumption, I/O bandwidth, or system partitioning.


Hierarchical Design Approach ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ To combat complexity — “divide-and-conquer”

❏ Hierarchical approach

• Partition various aspects of VLSI circuits into abstraction levels

• Define the order among these levels

❏ Methodology

• A particular ordered sequence of steps linking these abstraction levels

❏ Implementation

• A set of CAE design tools

• Efficient implementation depends on:

– How well its underlying principles reflect the nature of VLSI circuitry

– How well its external expressions supports the implementation efforts


Levels of Abstraction in Digital and Analog Design ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

High

Low

Digital Analog

Behavioral

RTL/Gate

Switch/Timing

Electrical

Nonideal Functional

Behavioral

Ideal Functional

Electrical

Laplace/Z transfer functions,Data-flow diagrams, …

Op-amps, switches,integrators, comparators, …

Finite bandwidth, gain,input/output resistances, …

VHDL

Equivalent RC

Matrix solution

Event-driven

Electrical circuitsHigh

Low

Level Cost Accuracy

High

Low


VLSI Design Hierarchy ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Abstraction

Functionalmodules

System

Architecture

Registertransfer

Logic

Switch

Layout

Hierarchy Supporting Tools

Binding of data flowfunctional modules,microinstructions

Space-time behavioras instruction, timingand pin assignmentspecifications

Global organizationof functional entities

Primitive operationand control methods

Boolean functionof gate circuits

Electrical propertiesof transistor circuits

Geometric constraints

High

Low

Schematic entry, synthesis programs,simulation and verification programs,PLA tools

Layout editor/compactor, netlistextractor, design rule checker,floor-planning, placement androuting programs

Flow charts, diagramshigh-level languages

HDLs, floor-planning, blockdiagrams, area and clock cycleestimators

Systhesis, simulation, verification,and test analysis programs,resource utilization evaluators

Libraries, module generators,schematic entry, test generators

RC extraction programs, timingverification and electrical analysis


Microelectronic Technologies ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Microelectronic technologies

Printedcircuit

Film

Flexibleboard

Plasticmolded

Thick Thin Silicon

MOS Bipolar MOS Bipolar

GaAs onsilicon

Surfacemounttechnology

Hybrid

Monolithic

GalliumarsenideSolid

board




❏✔ ASIC Design

❏ Semi-Custom IC Design




Silicon Manufacturing Alternatives ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Silicon manufacturing alternatives

Standard components Application specific ICs

Fullcustom

Semi-custom

Siliconcompilation

Gatearray

Analogarray

Masterslice

Standardcell

Programmablelogic devices

PLA FPGA

Fixedapplication

Applicationsby programming

Hardwareprogramming

Softwareprogramming

MicroprocessorEPROM, EEPROMPLD

PLAROM

Logicfamilies

TTLCMOS

PROM PAL PGA


Comparison of Traditional SIC Design and ASIC Design ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Attribute SIC Design ASIC Design

Goal/Direction Chips to systems Systems to chips

Cost constraint Component count Design effort

Performance limitation Functional unit design Data communication

Major design alternatives Major components (processors) Design styles (GA, SC, FC)

Coupling between design steps Loose Tight

Testability requirement Nodes accessible at board level Must be incorporated early

Verification Breadboarding Simulation

Prototyping Usually in-house In cooperation with vendor

Last-minute changes Less costly Costly

Design guidance Informal Strong methodology

Tools Less CAE dependent CAE intensive


Why Use ASIC ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

CCoossttss

Bet te rper formance

Higherrel iabi l i ty

Lowernon-recurr ing

cost

F a s t e rTurn -a round

t i m e

T igh te rsecur i ty

Others …


The ASIC Challenge ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

— A process of integrating systems into chips

❏ ASIC — A mixture of aspects ofdesign approach,implementation technology,market orientation, andsubsequent productrequirements

❏ Central to meeting thischallenge — A betterunderstanding of the algorithmcharacteristics, majorarchitecture concepts,implementing technology, and,most important, theirinteractions

Algorithm Technology

Architecture

II nn tt ee rr aa cc tt ii oo nn


Historical Perspective of the ASIC Technology ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Before VLSI The VLSI Era The ASIC Era

Algorithm

• data structure• parallelism• concurrency• synchronization

Technology

• fabrication• device physics• circuit techniques

Architecture• functional unit• memory• interconnect network• operating systems

digial logicinstructionset


Architecture

• systolic array• RISC

• hierarchical design methodology• CAE systems


Architecture

ASIC design


Impact of ASIC on System Design ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

II CC

Materialproperties

Processtechnology

Devicecharacteristics

Circuittechniques

High-levelabstraction

Structuralorganization

Integration of knowledge

SS yy ss tt ee mm

dd ee ss ii gg nn ee rrA p p l i c a t i o n

e n g i n e e r

V L S Id e s i g n e r

● Gap: the disparity between our capabilityto fabricate and our capability to design

CAE tool

developers

Silicon

foundriesASIC

vendor

● Interfaces: difficult to define due to theevolving nature of ASIC technology andthe diversity in application areas


The ASIC Design and Manufacturing Process ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Simulation (functional)Net and test vectors

Idea

ASIC product

Specification

Schematic diagram

Layout

Simulation(functional and timing)

Testing

Foundry

Designcentre

3

2

1


The Essential Steps and Components of ASIC CAD ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Select technology

Schematic entry

Simulation

Route

Re-simulation

Manufacture

Celllibrary

Electricalrules

Geometricrules

Technology files


Comparison of ASIC Design Styles ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Full custom Semi-custom Silicon compilation

bottom-up application-specific top-down

❏ Full custom

• A chip is designed from scratch to meet a particular need

• The emphasis is on achieving best electrical performance and minimum area

• It is appropriate for chips having large production runs

❏ Silicon compilation

• Given a description of the system, mask and test information are produced

• The output is either a simple combinational circuit or a finite state machine

• Most silicon compilers are not silicon-area efficient

• It is appropriate for small volume runs

• It may be used to generate simple cells to build up standard cell libraries


Typical Turn-Around Times ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ “Time-to-market” — the time taken for prototypes to be available and, later, thetime for production quantities to start arriving

Typical turn-around times for samples to be delivered by foundries

Year Gate array Standard cell Full custom

1984 6–8 weeks 12–16 weeks 18 months

1986 3–4 weeks 8–12 weeks 10 months

1988 1 week 6–10 wees 15 weeks

• The time for production models to arrive is usually longer, often 10–20 weeks.


Relative Merits of ASIC Implementation Styles ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

designfreedom/effort

unconstrained

mask layout

interconnect

programming

design turn-around timeproduction volume

programmable logic devices

semi-custom design

full custom design

PAL

PLA

Gate array

Megacell

Standard cell

Microprocessor

Performance (FTR)


Choice of Design Methodologies ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

??Designfreedom/effort

Productionvolume

Turn-aroundtime

Security

Interconnectiondensity

Reliability

Performance

??


Group Discussion 1 ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

VLSI Design Methods

Topic 1

• Identify characteristics used tocategorize the different designmethodologies

• Describe the VLSI design hierarchyand the hierarchical designapproach

Topic 2

• Identify the main components of atypical design flow

• Define and explain front-end andback-end design activities

ASIC Design

Topic 3

• Describe the characteristics andbenefits of ASIC design as opposedto the standard IC design

• Identify and define different ASICfamilies

Topic 4

• What design decisions are made inchoosing a particular ASIC designstyle

• How they are made




❏✔ ASIC Design

❏✔ Semi-Custom IC Design




Semi-Custom Design Styles ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Gate array

• A chip containing a prediffused but unconnected pattern of gates. Inter–connection of the gates is made by one or more customized masks

❏ Analog array

• A partially prefabricated chip containing either analog basic circuit elements ordiscrete analog devices, which are interconnected into an analog circuit by acustomized mask

❏ Master slice

• A prefabricated chip consisting of a mix of gate and analog arrays, allowingsystems containing both analog and digital functions to be customized

❏ Standard cell

• Software defined logic or analog circuit functions as building blocks to form therequired system. There is no prefabrication. Similar in concept to PCB

❏ Programmable logic devices (not strictly ASIC)

• A range of logic gates and latch functions which can be programmed


Gate Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Concept: Array of gates + pads

❏ General concerns

• What logic/gate configuration to use?

• How many pads are required?

• What is the best floor plan (layout) to provide adequate signal routing andpower distribution?


Analog Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Early analog arrays

discrete bipolar devices

Transistorsdiodes

resistors amplifiers

oscillators

filtersmetallization

mask

• No library of layouts

• Manual trial-and-error process

❏ Two classes

• With complete function cells

– op-amps, unity-gain buffer amplifiers, capacitors, switches

• With subcells

– diff-amp + output buffer = op-amp


Master Slice ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Concept: Gate array + Analog array = Master slice

❏ General concerns

• Ratio between the amount of digital to analog circuitry

• Type of analog circuitry

• Size of the gate array


Criteria for Selecting an Array and Vendor ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Service offered

• speed, quality, size of the library, range and sophistication of the software,time for prototyping and production

❏ Technical specifications of the array

• array size, functions, pad numbers, speed of operation, package range

❏ Cost

• non-recurring engineering (NRE) costs

❏ Second sourcing

• product lifetime (if long), product cost (if high)


Advantages and Disadvantages of Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Advantages

• Lower cost (sharing of processing cost)

• Faster prototyping

❏ Disadvantages

• Large chip area for routing (~75%)

• Low gate utilization (~50%)

• Circuit utilization (due to standard size)


Selected Array Suppliers ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Company GA AA/MS Company GA AA/MS

AMD/MMI ✔ National/Fairchild ✔

AMCC ✔ NCR ✔

Cherry ✔ NEC ✔

Fujitsu ✔ Philips/Signetics ✔

Gain Electronic Corp. ✔ (GaAs) Plessey/Ferranti ✔

GE/RCA ✔ Raytheon ✔

Gigabit Logic ✔ (GaAs) Semi Process Inc. ✔

Gould/AMI ✔ Siemens ✔

Harris ✔ Taxas Instruments ✔

Hitachi ✔ SGS/Thomson ✔ ✔

LSI Logic ✔ Toshiba ✔ ✔

Linear Technology ✔ TriQuint ✔ (GaAs)Micro Circuit Engineering ✔ Univeral Semiconductors ✔ ✔

Micro Linear Corp. ✔ Vitesse Semiconductor ✔ (GaAs)Motorola ✔ VLSI Technology ✔


Standard Cells ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Design concept

Standard cell Systeminterconnect

S iLib

(mapping)

❏ Basic approaches

• Channelled cells — alternate rows of cells and channels

• Channel-less type — whole chip area covered by cells, the routing occurringabove them in the top two layers of interconnect metal

❏ Cell library

• Size: Standard (small logic), macro cell, mega modules, megacells, supercells

• Type: – Fixed: 8-bit synchronous counter

– Parameterized: n-bit counters, shift registers, PLAs, RAMs, ROMs,microprocessors (bit slice machine)

– Pads


Advantages and Disadvantages of Standard Cells ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Advantages

• More flexible to include digital as well as analog functions

• More compact design (less routing area, improved speed)

• More sophisticated systems can be built (using parameterized cells,microprocessors)

❏ Disadvantages

• Up-front cost — no inherent sharing of processing cost (some sharing insoftware library and processing in a multi-project wafer)

• Costs in additional mask-making, software, and workstation resources


Selected Standard Cell Suppliers ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

AMCC

Fujitsu

GE/RCA/AWA

Could/AMI

Harris

Hitachi

International Micro Products

Intel

LSI Logic

Micro Circuit Engineering

Motorola

National/Fairchild

NCR

NEC

Plessey/Ferranti

Philips/Signetics

Siemens

Silicon Systems

Texas Instruments

SGS/Thomson

Toshiba

VLSI Technology

Zymos


Programmable Logic Devices ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Arrays PLDs Std Cells

Standard productsHardware System→ Software System→(vendor) (vendor)(can be programmed in-house)

❏ Risks in changing to ASIC (for small manufacturers)

• Investment in NRE costs • Confidentiality design concepts

• Lack of last-minute design changes

❏ Advantages of turning to PLDs (even for large organizations for prototyping)

• Fast programming of devices

• No NRE charges

• Low equipment costs

• Immediate in-circuit checking

❏ Disadvantages

• Limited size (< 10,000 equivalent gates)

• Not as flexible as gate arrays, standard cells, or full custom

• Large devices can be expensive (several hundred dollars per chip)


Development of Programmable Logic Devices ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Technologies

• Metal fusible link technology

• Polysilicon fuse technology

• Antifuse technology

• Ultraviolet erasable and electrically erasable methods employed in ROMs

• Dynamic matrix switching methods (LCA)


Programmable Gate Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Concept:

Gate Array

PLA

• Array element

– Simple PLDs (macrocells) – Configurable logic circuits (PLA)

• Routing

– Internal bus structure – Switching matrix

❏ Examples

• Altera: Macrocells interconnected by internal bus

• Xilinx: Logic cell arrays (LCAs) routed by switching matrix


Classes of Programmable Gate Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Class 1 AND (fixed)AND (variable)AND (variable)

OR (variable)AND (fixed)AND (variable)

Class 2 AND OR

AND OR

Inverter/NOT inverterInverter/NOT inverter with feedback

Class 3 AND OR

AND OR

RegisterRegister with feedback

Class 4 AND OR

AND OR

Other logic (e.g., XOR) registerOther logic register with feedback

❏ Other names (“programmable logic devices ASICs”)

• EPLD (erasable PLD)

• PLC (programmable logicsequencer)

• MAX (multiple array matrix)

• FPAD (field programmableaddress decoder)


Selected Programmable Logic Device Vendors ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Actel Semiconductors

Advanced Micro Devices

Altera Corp.

Atmel Corp.

Cypress Semiconductor

Exel Microelectronics

Gazelle Microcircuits

Gould Semiconductors

Harris Semiconductors

Intel

Lattice Semiconductor Corp.

Monolithic Memories

National/Fairchild

Panatech Semiconductors

Philips/Signetics

PLX Technology

Samsung Semiconductor

Seeq Technology Inc.

Seiko Semiconductor

SGS/Thompson

Sprague Solid State

Texas Instruments

VLSI Technology

Wafer Scale Integration

Xilinx Inc.




❏✔ ASIC Design


❏✔ Field-Programmable Gate Array



Field Programmable Gate Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ FPGA — A device in which thefinal logic structure can be directlyconfigured by the end user withoutthe use of an IC fabrication facility

❏ Two major aspects

• Interconnection resources:wire segments andprogrammable switches

• Architecture design:structure and content of logicblocks

❏ Two distinct features

• Instant manufacturing turn-round(minutes)

• Negligible prototyping costs(~$100)

A Conceptual FPGA


Types of Programmable Devices ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ MPGA: Mask programmable — by the manufacturer (“hard-wired”)

❏ FPGA: Field programmable — by the end user (“switch”)

Attributes MPGA FPGA

Prototype cost high low

Production time long short

Operation speed fast slow

Logic density high low

Area requirement small large

Yield high low


Major Issues in FPGA Development ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ General architecture

❏ Programming technology

❏ Logic optimization

❏ Technology mapping

❏ Logic block architecture

❏ Interconnection resources

❏ Placement and routing


FPGA Implementation Process ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

----------------------------

Technology Mapping

Initial Design Entry

Logic Optimization

Placement

Routing

Programming Unit

------------------------------------------------------

CAD

Configured FPGA

--------------------------

Approach / Goal

• Area optimization – minimize total number of blocks• Delay optimization – minimize the number of stages of logic blocks

• Optimize area and/or speed of the final circuit

• Minimize the total length of interconnect

• Assigns wire segments• Chooses programmable switches

• Configure the FPGA chip

• Schematic • VHDL • Boolean expression


Programming Technologies ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Programming element (“switch”)

• Entities that allow programmable connections between wire segments

• Configurable in one of two states: ON or OFF

❏ Programming technologies

• Static RAM cells

• Anti-fuses

• EPROM and EEPROM transistors

❏ Desired properties of the programming element

• Consume as little area as possible

• Have a low ON resistance and a very high OFF resistance

• Contribute low parasitic capacitance to the wiring resources

• Can be reliably fabricated in large quantities on a single chip

• Other features: Non-volatile and re-programmable


Logic Optimization and Technology Mapping ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Logic Optimization

Technology Mapping

original network

optimized network

optimized circuit

----------------------------Logic Synthesis

---------------------------- ----------------------------

----------------------------

❏ Logic optimization

• Technology independent

• Redundancy removal

• Common subexpression elimination

• Don’t-care exploitation

❏ Technology mapping

• Technology and architecturedependent

• Optimized circuit considering botharea and delay

• Library-based

• Lookup table

• Multiplexer-based


Logic Block Architecture ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Area

Functionality

area/block

number of pins/block

number of blocks neededto implement a circuit

number of connections between blocks

Total area (logic block + routing)10~30% 70~90%

Logic Block Functionality vs Area-Efficiency

LOGICBLOCK

Routing

Delay

Area Architecture

Functionality


Interconnection Resources ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ General purpose interconnect

❏ Direct interconnect

❏ Horizontal/vertical routing channel

❏ Wiring segment

❏ Feed-through

❏ Routing switch (matrix)


Placement and Routing ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Placement

Routing

----------------------------

---------------------------- -----------------------

optimized circuit

Programming Unit

-----------------------

❏ Placement

• Assign each Logic Cell to a specificlocation in the FPGA

• Well developed techniques

• Similar to other technologies

❏ Routing

• Achieve interconnections among theLogic Cells by selecting wiresegments and routing switches

• Routing architectures

– Row-based FPGA: only horizontalrouting channels

– Symmetrical FPGA: both verticaland horizontal routing channels


Generic FPGA Development Cycle ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Manufacturing/Delicery/Maintenance

Requirement/planning

Design Entry

• Computer-aided structual design

• Behavioural method of design description

• Hierarchical mixed-mode design entry

Design Implementation• Design merge

• Partition (technology mapping)

• Placement and routing

• FPGA configuration

• Functional simulation

• Timing simulation (after implementation)

• Hardware testing

Design Verification


Major Elements of Xilinx Logic Cell Arrays ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Xilinx FPGA — Logic Cell Array (LCA) (SRAM-based, unlimited configurability)

Configurable Logic Block(CLB)

Programmable Interconnect(Switching Matrix)

Configurable I/O Block(IOB)

CombinatorialLogic Function

Flip-Flop

I O

CLB

SwitchMatrix

CLB

CLB CLB

IOB

IO

T SCLK

Pad

• Combinational logic

• Flip-flops

• Output registered orcombinatorial

• High-speed direct

• Flexible general-purpose

• Low-skew long lines

• Internal 3-state buffer

• Input, output, orbidirectional

• Registered orcombinatorial

• 3-state output


Xilinx Development System ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

VIEWDRAW

abc.WIR

abc.1

Filewrite

abc.AKA

WIR2XNF

XNFMAP

abc.XNF

abc.MAP

MAP2LCA

④

③

➀

abc.LCA

A P R

abc.LCA(routed) ➁

MAKEBITS

abc.BIT

XCHECKER

DEMO BOX

Design Entry

Design Implementation

Partitionedfile

Download

Bitstreamfile

Placed &routed file

abc.VSM

③

➀

EXPORT

Functional Simulation

Design Verification

VIEWSIM

VIEWSIMwirelist file

VIEWSIMwaveform file

abc.WFM

VIEWWAVE

abc.SEESavefile

abc.XNF

LCA2XNF

with reference& display info

Timing Simulation

abcth.XNF

BAX

V S M

abcth.VSM

VSMUPD

abcth.VSM

VIEWSIM abcth.WFM

④

➁

VIEWWAVE

with hierarchicalnet connect info

XNF2WIR

abcth.1


Selected FPGA Vendors ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Actel Semiconductors

Advanced Micro Devices

Algotronix

Altera Corp.

Concurrent Logic

Crosspoint

Cypress Semiconductor

Plessey

Plus Logic

Quicklogic Corp.

Texas Instruments

Xilinx Inc.


Group Discussion 2 ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Semi-Custom Design

Topic 1

• Define and describe different semi-custom design styles

• Discuss the major advantages anddisadvantages of each of the designstyle

Topic 2

• Compare different types ofprogrammable logic devices

• Describe the concept ofprogrammable gate arrays

FPGA Development

Topic 3

• Summarize the main components ofthe FPGA architecture

• Describe the activities in each majorstep of the FPGA developmentcycle

Topic 4

• Describe the general architectureand major steps in the Xilinx FPGAdesign environment

• Relate the major design steps in theProject (M3) to those of the genericdevelopment cycle




❏✔ ASIC Design


❏✔ Field-Programmable Gate Array

❏✔ 4-Bit Microprocessor Implementation


Four-Bit Microprocessor Implementation ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

— Relate a specific example to what you have learned

❏ System specification

• What is required?

❏ Choice of methodology

• What are the alternatives?

• Why choosing FPGA?

❏ Design flow

• How to design?

• What are the major concerns at each stage of the design?


One Flip-Flop Per State Method ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ From state diagram — determine the connections of the flip-flops

• Each flip-flop represents one state

• Input is determined from the previous state “AND” the input function switches(FC3 FC2 FC1 FC0)

• May use a hierarchical approach — each instruction is a sub-block

❏ From timing diagram — determine the output signals

• Outputs of the CNTRL logic block are a combination (“OR”) of the differentstates of all the instructions

• Decode each output of the CNTRL logic block from the timing diagram

❏ Features

• Simple in design, but waste of flip-flops

• Difficult to modify the design — “hard-wired” (i.e., laid down permanently inthe processor’s electrical circuitry)


Next-State and Output Equations ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

T0

T1

T2

T3

T4

T5 T7 T9

------------------------------------------

------------------------------------------

------------------------------------------

------------------------------------------

------------------------------------------EO

EI

L A

LB

ALU

LO

RST

F1 F0 = 1 0

❏ Next-state equation

T0 = RST + T5 + T7 + T9

T3 = T2 F1 F0

:

❏ Output equation

LO = T5 + T7 + T9

:


Firmware — Microprogrammed Control System ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Hardware Firware Software

High-level program“Microprogram”Hard-wired circuitry

❏ Microprogram — a set of control instructions written in microcode

• The idea was conceived more than 30 years ago, soon after the advent of thefirst computers

• In principle, any computer (mainframe to PC) can be designed with amicroprogrammed control system

• Microprogramming a computer (firmware) is not the same as programming amicrocomputer

❏ Microprogramming

In most modern computers the routing of information is controlled at the lowestlevel by a microprogram: a set of stored instructions that functions in place of acompletely “hard-wired” control system

— David A. Patterson


4-Bit Microprocessor Using PLA/ROM and Counter ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

CNTRL Block Using PLA/ROM

PLAor

ROM

3-BitCounter

ABC

RST

CLK

C0C1C2RST

FC3

FC2

FC1

FC0

OE2–OE0

LO2–LO0

M, F1, F0

Cin, Ro, RenCS

• RST: Reset the 3-bit counter as well asenable chip-select pin (CS) of the PLA

• CLK: Clock a divide-by-seven counter(outputs C2 C1 C0: 000 to 110)

• PLA/ROM input: FC3 FC2 FC1 FC0 andC2 C1 C0

• Every instruction cycle is made up ofseven clock periods

• For single-operand instruction (NOT),‘Enable Output Register’ can be repeaedto avoid complicated decoding

• Boolean expression for the PLA/ROMcan be decoded from the timing diagramfor each instruction

• PLA is prefered to a ROM if the numberof instructions to be implemented isfewer than 16


Types of Cycles and the Truth Tables ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Table 1: Types of Cycles and the Corresponding Output Signals

Cycle OE2 OE1 OE0 LO2 LO1 LO0 M F1 F0 Cin Ro RenT 0 Enable Output RegisterT 1 Enable Input BufferT 2 Load A RegisterT 3 Load B RegisterT 4 Enable ALUT 5 Load Output Buffer

Table 2: Truth Table for an Instruction

FC3 FC2 FC1 FC0 C2 C1 C0 Tx OE2 OE1 OE0 LO2 LO1 LO0 M F1 F0 Cin Ro Ren


Design Cycle — Revisited ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Assuming the design is implemented using Xilinx XC3000 FPGA

❏ Design methodology

• What design approach is chosen to implement the 4-bit microprocessor?and why?

• What design stages will be going through?

❏ Design implementation

• How to reduce (optimize) the number of states?

• How many configurable logic blocks (CLB) would be needed to implementyour design?

❏ Design verification

• How to simulate your design using, e.g., the VIEWSIM simulator?

• What is the expected output waveform given a particular input pattern?


Design Exercise ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

With reference to the 4-bit microprocessor specification in the Project Manual (M3),design the control circuitry of the CNTRL logic block for the following instructions [youmay choose at least one from each of the groups (a) and (b)]:

(a) NOT, AND, OR, XOR; (b) ADD, SUB, RRC, RLC

using the following two approaches:

I. One flip-flop per state:(1) Draw the state and timing diagrams(2) Write the next-state and output equations(3) Draw schematic diagrams using D flip-flops to implement each state and output signals

II. PLA and 3-bit divide-by-seven counter:(1) Define the types of cycles by filling in Table 1(2) Decode the output signals for each instruction by filling in Table 2(3) Based on Table 2, draw “stick diagram” of the PLA to implement the CNTRL logic

General questions:(1) Show how a new instruction (e.g., INCA) can be added for each of the two design methods(2) Draw conclusions on the advantages and disadvantages of the two design styles


Summary ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

❏ Design

• Approaches, methodologies, decisions, hierarchy, process

❏ Classification

• Manufacturing technologies, design methodologies

❏ Comparison — Major figures of merit to consider

• Cost: development, manufacturing, non-recurring engineering, …

• Performance: speed, power, density, reliability, …

• Schedule: prototyping, turn-around time, CAD tools, second sourcing, servicequality and speed, …

• Others: production quantity, design freedom, last-minute change, security, …

❏ FPGA (Xilinx) — concept, features, design cycle, implementation, …

❏ Design example — relate to all of the above


Key to Successful Completion of the Course ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

Lecture

ReadingDiscussion

TT hh ii nn kk ii nn gg

Understanding

Expanding

• •

•


Compilation of the Questions from Design Group D24 ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

• At present, we are using very-large-scale integration (VLSI). ULSI and wafer-scale integration (WSI) are beingconsidered to replace VLSI. Do you think that WSI can replace VLSI despite of its disadvantages? and when doyou think WSI will replace VLSI technology?

• What skill/knowledge an engineer must possess when designing circuit using different design methodologies?

• What are the front-end and back-end design activities in the design cycle?

• What are the most important factors/criteria affecting the selection of a particular methodology for use in acompany?

• What are the advantages and disadvantages of various ASIC test approaches?

• ASIC designs are getting more and more complex. How should we go about doing it?

• An IC is to be designed. Highlight the design steps that will be applied to obtain the final design.

• Give examples of the different types of ASIC families and describe briefly the advantages and architecture of oneof the types.

• With today’s technologies, to buy a sophisticated standard off-the-shelf IC is very easy or to fabricate a full-customIC is already simplified. Why is there a need to have a semi-custom solution and why it is so popular?

• What is the disadvantages of using full-custom ICs and what is the solution to it?

• What are the definitions of gate array, analog array, master slice, standard cell, programmable logic devices?List the pros and cons.

• What are the advantages and disadvantages of using master slice analog semi-custom ICs?


Compilation of the Questions from Design Group D24 ENGINEERING DESIGN III DESIGN OF A SEMI-CUSTOM IC

• What are the advantages and disadvantages of MPGA and FPGA? Which is a wiser choice to use?

• The time frame from first to second to third generation of FPGAs is approximately six years. Explain why andwhat might happen in the next 6 years.

• The details of the FPGA development cycle, given in the document of Design Module, was insufficient to show thesoftware and hardware that a new designer has no idea of utilizing its various tools. The question is how thevisualization of FPGA development system like? What is the function of its system, in terms of hardware andsoftware?

• List some debugging hardware tools of a FPGA-based system.

• Can a field programmable electrical system be implemented on one chip?

• Why do we need FPGA and how we can use it?

• What are the software tools needed for the future development of FPGA?

• What are the future trends of the Field Programmable Gate Array (FPGA)?

• Compare FPGAs and PLDs.

• If you are a designer, what are the criteria to choose among different types of semi-custom ASIC? and how areyou going to choose an appropriate type for your design?

• Since there are many kinds of user-programmable logic devices (e.g., FPGA, PLD & PAL), their characteristicsand architectures vary widely as well. So is there any proposal/solutions to integrate the programming of allthese devices with just one package/software?

E322

Documents

eee ntu

cntrl logic

programmable

bit microprocessor

end design

bit microprocessor

schematic

gate arrays