200 978-4-86348-010-0 2009 Symposium on VLSI Circuits Digest of Technical Papers 19-3 Dual-Power-Path RF-DC Multi-Output Power Management Unit for RFID Tags Jun Yi, Wing-Hung Ki, Philip K. T. Mok and Chi-Ying Tsui Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong SAR, China, Email: {eeyi, eeki, eemok, eetsui}@ece.ust.hk Abstract A dual-power-path (DPP) RF-DC topology is employed to design the power management unit for an EPC C1 G2 RFID tag using a 0.18µ µ µm CMOS process with 7 output voltages for signal processing blocks and OTP memory. The DPP technique splits the rectifier and reconfigures the RF-DC circuits depending on the state of input power, which saves storage capacitor size without sacrificing efficiency, or alternatively, improves efficiency without additional capacitance. I. Introduction Improving RF-DC power conversion efficiency and reducing cost are major issues in the design of RFID tags. The upper part of Fig. 1 shows two existing RF-DC topologies [1-5] consisting of a rectifier, a storage capacitor, and with or without a low dropout regulator (LDR). Previous works focused on the rectifier with little attention on LDR efficiency and the storage capacitor. When receiving data-0 from the reader, the tag receives power only for the first part of the Tari (complementary pulse width, CPW) [6], and the energy needed in the second part (PW) has to be stored by charging up the capacitor(s) during CPW. Similar situation happens for backscattering. Let the tag be at the maximum working distance that the input power is just adequate for proper function. For Type-I topology, the received RF energy is converted to DC by a rectifier RECT, or with an LDR in cascade, to supply the load and to charge up a storage capacitor C SI . The minimum C SI is I L ×PW/∆V DD . To keep the area of C SI acceptable for on-chip implementation, [2] and [3] used large ∆V DD , which however is undesirable for loading circuits; [5] considers making I L small, limiting the system function; and [1] used special FeRAM process offering very high capacitance density. This problem becomes increasingly pronounced as more functionalities like security protection and sensing are needed. Type-II topology mitigates the problem by moving the storage capacitor C SII before LDR. With the LDR regulating V DD , ∆V CSII could be relatively large to allow a small C SII , trading off the efficiency of the LDR efficiency. Assume V CSII ramps up and down linearly, the efficiency of the LDR is η LDR-II = α×∆V DD /(V DD +V do + 0.5∆V CSII ) (1) where α=I L /(I L +I LDR ), with the bias current I LDR << I L , and V do is the dropout voltage of the LDR. Since ∆V CSII = (I L +I LDR )×PW/C SII , attaining high efficiency needs a large C SII . II. Proposed Dual-Power-Path Topology Our proposed dual-power-path topology is also shown in Fig. 1, with related waveforms in Fig. 2. The rectifier of the previous topologies that need to drive both resistive load (I L ) and capacitive load (storage capacitor) is split into two sub-rectifiers RECT_P and RECT_S, with RECT_P driving mainly the resistive load and RECT_S driving only the capacitive load. A signal φ DEM from the demodulator circuit controls the configuration. During the CPW phase (φ DEM = "1"), switches MS PA , MS PB and MS SA are closed, and the primary power path (PPP) is activated by connecting the LDR to RECT_P and C P . This research is in part supported by Grant Research Council RGC 614506. The load is supplied by RECT_P directly. At the same time, RECT_S charges up the secondary power path (SPP) storage capacitor C S to V DD +V do +∆V CS . Once the PW phase starts the RF power becomes zero, but φ DEM changes from "1" to "0" with a delay of t dem which the finite response time of the demodulator. During the duration t dem , reverse leakage currents of the rectifiers drain C S and C P , and C P also supplies the load so the voltage ripple ∆V CP is (I L +I LDR +I leak )×t dem /C P , which will be replenished in the next CPW. With the elapse of t dem , leakage stops immediately by opening MS PA and MS SA . MS PB is also opened, disconnecting LDR from C P . To avoid undesirable charge sharing between C P and C S , MS SB is closed after a very small dead-time. SPP is then enabled and C S is discharged by the load during PW so ∆V CS =(I L +I LDR )×PW/C S . Typically, PW is equal to CPW, and the overall LDR efficiency is η LDR-DPP = α×V DD /(V DD +V do + 0.25∆V CS + 0.25∆V CP ) (2) Ideally, t dem =0 so ∆V CP =0 and C P is not needed. LDR efficiency is improved if ∆V CS =∆V CSII . Conversely, if we keep Fig.1. Existing and proposed RF-DC topologies. Fig.2. Voltage waveforms of DPP topology (left). Ripple voltage ratio versus capacitance saving with equal LDR efficiency (upper right). The maximum capacitance saving versus t dem (lower right). Authorized licensed use limited to: Hong Kong University of Science and Technology. Downloaded on September 7, 2009 at 04:03 from IEEE Xplore. Restrictions apply.