Ds Ss Circuit

A Direct Sequence - Spread SpectrumModulator/Demodulator Design 1

Mohammad SharawiElectronics Engineering

Princess Sumaya UniversityCollege for Technology

( Royal Scientific Society)Amman–Jordan

June 2000

1 c©2000 by Mohammad Sharawi All rights Reserved.No part of this report is to be copied, reproduced, or distributed in anyway, withoutwritten consent of the Author.

1

To Mom, and Dad.

AbstractThis report demonstrates the design of a simplified Direct Sequence-

Spread Spectrum system. Due to the rapid movement towards theMultiple Access Mobile world, i found it interesting to clarify thedesign process of these complicated widely used systems. The aimof this report is to give the reader a rough idea of such systems, andhow to start implementing similar designs. This report is intendedfor educational purposes, the design is based on simplified models,that do not exactly represent real life applications, which incorpo-rate much complex issues. I hope that my design might be of somehelp to those who are seeking knowledge in such field.

Contents

1 Direct Sequence-Spread Spectrum 41.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Pseudo Noise (PN) . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Direct Sequence -

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 The Design of the DS-SS Modulator 82.1 The PN Generator Design . . . . . . . . . . . . . . . . . . . . . 82.2 The Input Word Generator Design . . . . . . . . . . . . . . . . . 102.3 The BPSK Modulator Design . . . . . . . . . . . . . . . . . . . 11

3 The Design of the DS-SS Demodulator 143.1 The Low Pass Filter Design . . . . . . . . . . . . . . . . . . . . . 143.2 The BPSK Demodulator Design . . . . . . . . . . . . . . . . . . 15

4 Conclusion and Further Enhancements 21

2

List of Figures

1.1 PN Generator Block Diagram . . . . . . . . . . . . . . . . . . . . 51.2 DS-SS Transmitter Block Diagram . . . . . . . . . . . . . . . . . 61.3 m(t) and p(t) for a Maximum Length PN generator, with m=3. 61.4 DS-SS receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 The PN Generator Circuit Diagram. . . . . . . . . . . . . . . . 92.2 The PN Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 The 8-bit Word Generator Circuit diagram, with a data rate (pe-

riod of one bit) of 6.666 KHz. . . . . . . . . . . . . . . . . . . . 102.4 The 8-bit Word Signal. . . . . . . . . . . . . . . . . . . . . . . . 112.5 The Spread Signal Word

⊕

PN (Word XNOR PN). The wordsignal at bottom, the Spread signal at top. . . . . . . . . . . . . 12

2.6 The BPSK Modulator Circuit. . . . . . . . . . . . . . . . . . . . 132.7 Sss(t). The DS-SS signal coming out of the Modulator. . . . . . 13

3.1 Sallen-Key Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2 The Filtered output and the output of the Demodulator’s Multi-

plier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3 The filtered output and the output of the Comparator. . . . . . 173.4 A delay of 1–bit is observed, between the transmitted and re-

ceived signals (before being despread). . . . . . . . . . . . . . . 183.5 The inputs to the XNOR gate, after a delay of 1–bit was added to

the PN signal.(down is the PN signal) (up is the incoming signalfrom D–FF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 The original word signal (up), and the received one (down) . . . 193.7 DS-SS receiver circuit diagram. . . . . . . . . . . . . . . . . . . 20

3

Chapter 1

Direct Sequence-SpreadSpectrum

1.1 Introduction

Spread Spectrum techniques were and are still used in military applications,because of their high security, and their less susceptibility to interference fromother parties. In this technique, the same bandwidth is shared by multiple users,without significantly interfering with each other.

The spreading waveform is controlled by a Pseudo-Noise (PN) sequence,which is a binary random sequence. This PN is then multiplied with the originalbaseband signal, which has a lower frequency, which yields a spread waveformthat has a noise like properties. In the receiver, the opposite happens, whenthe passband signal is first demodulated, and then despread using the same PNwaveform. An important factor here is the synchronization between the twogenerated sequences.

In this report, I will try to illustrate the design process of such a system,and then come up with a full circuit design.

1.2 Pseudo Noise (PN)

As we mentioned earlier, PN is the key factor in DS-SS systems. A PseudoNoise or Pseudorandom sequence is a binary sequence with an autocorrelationthat resembles, over a period, the autocorrelation of a random binary sequence[Rap96]. It is generated using a Shift Register, and a Combinational Logiccircuit as its feedback. The Logic Circuit determines the PN words.

In this design i used the so called Maximum–Length PN sequence. It is asequence of period 2m − 1 generated by a linear feedback shift register, whichhas a feedback logic of only modulo–2 adders (XOR Gates). Some properties ofthe Maximum–Length sequences are:

• In each period of a maximum–length sequence, the number of 1s is alwaysone more than the number of 0s. This is called the Balance property.

• Among the runs of 1s and 0s in each period of such sequence, one–halfthe runs of each kind are of length one, one–fourth are of length two,one–eighth are of length three, and so on. This is called the Run property.

4

CHAPTER 1. DIRECT SEQUENCE-SPREAD SPECTRUM 5

1 - 2 - 3 - 4 -PN signal

-

6

6 6 6 6CLK

modulo–2adder

Figure 1.1: PN Generator Block Diagram

• the Autocorrelation function of such sequence is periodic and binary val-ued. This is called the Correlation property1.

A block diagram of a Maximum–Length PN generator is shown in fig.1.1with a 4–bit register and one modulo–2 adder. This has a period of 24− 1 = 15,and it was the configuration used in this design as we will show later.

1.3 Direct Sequence -Spread Spectrum

In Direct Sequence-Spread Spectrum the baseband waveform is multiplied bythe PN sequence. The PN is produced using a PN generator. Frequency of thePN is higher than the Data signal. This generator consists of a shift register,and a logic circuit that determines the PN signal. After spreading, the signalis modulated and transmitted. The most widely modulation scheme is BPSK(Binary Phase Shift Keying). The equation that represents this DS-SS signal isshown in eq.(1.1), and the block diagram is shown in fig.(1.2).

Sss =

√

2Es

Tsm(t)p(t) cos (2πfct + θ) (1.1)

where m(t) is the data sequence, p(t) is the PN spreading sequence, fc is thecarrier frequency, and θ is the carrier phase angle at t=0. Each symbol in m(t)represents a data symbol and has a duration of Ts . Each pulse in p(t) representsa chip, and has a duration of Tc . The transitions of the data symbols and chipscoincide such that the ratio Ts to Tc is an integer [Rap96].

The waveforms m(t) and p(t) are shown in fig.(1.3). Here we notice thehigher frequency of the spreading signal p(t). The resulting spread signal isthen modulated using the BPSK scheme. The carrier frequency fc should havea frequency at least 5 times the chip frequency p(t).

In the demodulator section, we simply reverse the process. We Demodulatethe BPSK signal first, Low Pass Filter the signal, and then Despread the filteredsignal, to obtain the original message. The process is described by the followingequations:

m(t) = Sss(t)× cos (2πfct + θ) (1.2)1For a full derivation of the Correlation property, please refer to [Hay94]


BinarySequence

-mkNON-Returnto ZeroEncoder

-m(t) × -m(t)p(t) BPSK

Modulator-Sss(t)

PN

6p(t)

Oscillator

6fc

Figure 1.2: DS-SS Transmitter Block Diagram

-

6

-

6

m(t)

p(t)1

-1

1

-1

Figure 1.3: m(t) and p(t) for a Maximum Length PN generator, with m=3.

and we know that ,

cos α× cos α =12

[1 + cos (2α)]

this yields,

m(t) =

√

2Es

Tsm(t)p(t)

12[1 + cos(4πfct + θ)] (1.3)

As shown in eq.(1.2)and eq.(1.3) when we multiply two cosine signals together,we will obtain two expressions, one of which has twice the frequency of theoriginal message. And this part can be removed by a LPF. The output ismss(t) as shown in fig.(1.4). My design is based on Coherent Detection BPSK,so we don’t have to worry about carrier synchronization issues.

As for the PN sequence in the receiver, i mentioned earlier that it should bean exact replica of the one used in the transmitter, with no delays, cause thismight cause severe errors in the incoming message. Again, my design is basedon the idea that PN sequences are matched, and actually i am going to use thesame generator for both to ease the design. There are various techniques thatdeals with PN delay problems and mismatches, but i am not going to encounterany in this design.


-Sss(t) BPSKDemodulator

-m(t)LPF -mss(t)

× - ∫ Tb

0-Decision

Device-

mk

OriginalInputData

PN

6p(t)

Oscillator

6fc

Figure 1.4: DS-SS receiver.

After the signal gets multiplied with the PN sequence, the signal despreads,and we obtain the original bit signal m(t), that was transmitted. The blockdiagram of the receiver is shown in fig.(1.4).

This simple straight forward description of DS-SS systems, will allow us todesign the Modulator/Demodulator circuits with some ease. We are going totake advantage of the block diagrams for each one of them.

Chapter 2

The Design of the DS-SSModulator

In this chapter, I am going to illustrate the circuit design and simulationof the DS-SS Modulator(Transmitter). Simulations were conducted using theEWB 5.0 software. Ideal components were used for the ease of the design, andto try to avoid other factors, that might directly affect the performance of thesystem. And since i am going to design a simple circuit for educational purposes,i decided to use the ideal components offered inside the software. Though, onecan substitute for any other non–ideal component and test the results, whichi consider a great practice for someone who wants to know more about thesystem.

2.1 The PN Generator Design

The design of the PN generator is based on the block diagram shown in fig.(1.1).Here we are going to need 4 D–Flip–Flops (FFs), a XNOR gate, and a Clocksource. Since we are using 4 FFs, m=4 and the PN signal will repeat it self every15 clock cycles. I have chosen the CLK frequency, fCLK=100KHz. The periodof the PN chip is TPNchip= 1

100K = 10−5 seconds. The total period of the PNsequence TPN = 15×TPN = 15×10−5 seconds. The period of the Binary Inputsignal (per bit) is going to be Tb= TPN=15×10−4 seconds, that is a frequencyfb= 6.6667KHz.

The Clock signal was taken from an external source (a Function Generator).We can design a clock using an oscillator and a shaper. But we are not going togo into that. The Circuit that resembles this PN is now easily understood. Itis shown in fig.(2.1). The only trick in the design is the clock assignment, andits affect on the incoming Binary Sequence coming from the Word Generator,which is discussed next.

As you notice from this design, the output level from the PN is not 1,-1 aswas indicated in the signal diagram of p(t). Here the output is either a 5V, or0V (Logic Levels). Don’t get confused, i will explain why i used these levelslater on. The output PN sequence is shown in fig.(2.2).

8

CHAPTER 2. THE DESIGN OF THE DS-SS MODULATOR 9

Figure 2.1: The PN Generator Circuit Diagram.

Figure 2.2: The PN Signal.


Figure 2.3: The 8-bit Word Generator Circuit diagram, with a data rate (periodof one bit) of 6.666 KHz.

2.2 The Input Word Generator Design

The Word Generator Circuit design is based on the one designed and illustratedin [SA99]. I am not going to discuss it in detail, but for further informationregarding its design, please refer to the indicated reference.

The Word Generator consists of two ICs, an Inverter, a Clock signal withfrequency of 6.666KHz, and a DC supply. The 74163 IC is a TTL 4-bit binarycounter, and the 74166 is a TTL 8-bit Parallel-In/Serial-Out Shift Register. TheClock signal feeds both ICs as shown in fig.(2.3). The shift register loads thelevels on its inputs when the Parallel Load signal is activated. Then it startsto shift the data, and sends them serially. The Parallel Load signal is takenfrom a 4-bit binary counter, so that after the counter finishes its count cycle,it will issue the RCO1 signal, which is used to trigger the shift counter to ac-tivate the Parallel Load function. By this we will obtain a controllable 8-bitperiodic Word Generator signal. The Signal obtained is shown is fig.(2.4). The8-bit Word is then multiplied by the PN signal. This is shown in the blockdiagram in fig.(1.2). In the block diagram we used a NRZE2 to adjust the Wordlevel voltages. Now, assuming that we are using the NRZE, the out put of themultiplier given the Word signal shown in fig.(2.4) and the PN signal shown in

1Repeated Carry Out. A carry bit that is generated at the end of each cycle.2Non-Return to Zero Encoder, leveling circuit, that allows you to change the 5-0 Volts level

to a 5-−5 level.


Figure 2.4: The 8-bit Word Signal.

fig.(2.2), will be:

–1–1–1–1+1–1+1–1–1+1+1–1+1+1+1 –1–1–1–1+1–1+1–1–1+1+1–1+1+1+1+1+1+1+1+1+1+1+1+1+1+1+1+1+1+1 –1–1–1–1–1–1–1–1–1–1–1–1–1–1–1–1–1–1–1+1–1+1–1–1+1+1–1+1+1+1 +1+1+1+1–1+1–1+1+1–1–1+1–1–1–1

We can see how does the PN signal affects the Incoming word signal that is115 of its frequency. When a −5 is multiplied with a +5 the result is −25. Andwhen a −5 is multiplied by a −5 the result is a +25. I mentioned in the previoussection that the output of the PN is a 0–5 volts, not a −5–5 level. Also, theWord levels are 0–5 not −5–5. This means that i can’t use the multiplicationprocedure here, cause a 0×0 6= 1 . To come over this problem, and to elimi-nate the use of a NRZE for the word signal, i substituted the Multiplier with aXNOR gate. The function of the Gate on the previous signal (PN, and Word)will be as follows:

000010100110111 000010100110111111111111111111 000000000000000000010100110111 111101011001000

These two Zero–One signals are the exact replica of the above −5–5 levels.But here i tried to perform a Digital Multiplication process that exactly resem-bles the analog one, and it did give the same results. The obtained signal isshown in fig.(2.5). Don’t bother from the very small glitches that occur whenthe word signal changes its state from 1–0 or 0–1. These glitches occur due tosome very small timing mismatch, but have no significant effect in this design.

This concludes the design of the 8–bit Word Generator, and the Multiplierthat Spreads the incoming Digital Data coming from the Word Generator usingthe PN signal.

2.3 The BPSK Modulator Design

This section illustrates the design of the BPSK3 modulator. The design isdirectly based on the block diagram shown in fig.(1.2). A more detailed analysisof this design is shown in [SA99]. The design and simulations are based on theuse of ideal components.

The BPSK Modulator is based on the idea of changing the phase of thecarrier signal whenever the incoming Bit changes its state. For example, if the

3Binary Phase shift Keying.


Figure 2.5: The Spread Signal Word⊕

PN (Word XNOR PN). The word signalat bottom, the Spread signal at top.

incoming message changes its state from 0–1, the carrier changes its phase by+180, and if it changes its state from 1–0 the carrier changes its phase by−180. To accomplish this task, we can now add the NRZ Encoder circuit, tomap the 0–5 Volts to −5–5 Volts level. This is done easily by a leveling circuitthat consists of two resistors of equal value, a non–inverting amplifier with again of 2, and a negative supply of −5 Volts. This is shown in fig.(2.6). You caneasily notice that i used an amplifier before and another one after the levelingcircuit. The first one will change the signal levels from 0–5 to 0–10 Volts. Afterleaving the leveling circuit, the level of the signal is −2.5–2.5 Volts ( i will leaveit to the reader to figure out how did i obtained such levels), which is thenapplied to another amplifier with a gain of 2, to yield an output of −5–5 Volts,that will enter the Multiplier circuit.

The signal then enters the Multiplier circuit. Here an ideal Multiplier with again of 1 is used4. The carrier frequency used in this design is 5 times fPNchip,which is 500KHz. Though one can rise the frequency of the signal in Wirelessapplications to end up with a shorter antenna for the device. Anyway, this isn’tour concern in this report. After the Multiplication process, we finally get theSss(t) which is the signal obtained from the output of the Modulator circuit.The output of the DS-SS Modulator is shown in fig.(2.7). Here, a couple of bitsfrom Sss(t) are shown, just to illustrate the frequency changes of the outputsignal.

4In [SA99], one can find a detailed description of the design of a Balanced Modulator usingthe MC1496 IC. This is very important to those who are willing to implement such design


Figure 2.6: The BPSK Modulator Circuit.

Figure 2.7: Sss(t). The DS-SS signal coming out of the Modulator.

Chapter 3

The Design of the DS-SSDemodulator

We have finished the modulator part of our Direct Sequence-Spread Spec-trum system. And we now come to the demodulator part that has the blockdiagram shown in fig.(1.4). As the figure illustrates, the incoming DS-SS signalis multiplied by the carrier in the BPSK demodulator. This gives us the spreadsignal that was initially transmitted, which is now called m(t). This signal has ahigher frequency component that results from the multiplication process as wasindicated in eq.(1.3). This is removed using a LPF1. After the signal is filteredout, it is multiplied by the PN signal to despread it, and obtain the originaltransmitted data. In this chapter we will illustrate the design of the LPF, andthe BPFK demodulator.

3.1 The Low Pass Filter Design

Our LPF is based on the Sallen–Key active filter design method. We will designa second order Butterworth LPF with a cutoff frequency of fcutoff = 105KHz,which is very close to the frequency of the PN signal to be detected after theremoval of the carrier.

The LPF is going to look like the one shown in fig.(3.1). Our duty is to findthe appropriate values for the components shown. As I mentioned earlier, weneed to have fcutoff = 105KHz.

The procedure to design such values is indicated in [EM88]. First, we haveto find the constant K, which can be found by:

K =10−4

fcutoff × C1

If we choose C1 = 10−9F , then K = 0.953. Now with the aid of table(3.1), andchoosing the gain of our filter to be 2, we obtain the following values:R1 = K × 1.126KΩ = 1.07KΩR2 = K × 2.25KΩ = 2.15KΩR3 = K × 6.752KΩ = 6.43KΩR4 = K × 6.752KΩ = 6.43KΩ

1Low Pass Filter

14

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR 15

Figure 3.1: Sallen-Key Filter.

C1 = C1 = 10−9Farads

By this we come to the end of the Sallen–Key Second Order Active filterdesign. The output from the filter is shown in fig.(3.2). In the figure, we can seethe output of the filter having very long rise and fall times. This causes delayin the incoming signal, also the periods aren’t precise. We can overcome thisobstacle by adding a Comparator right after the filter to do the shaping on thefiltered signal. The output of the Comparator is shown in fig.(3.3).

The filtration process affects the period of the incoming bits. To overcomesuch a problem, we add a D-FF with a clock of 200KHz. This will give us bitswith periods of 100KHz, as the ones that were transmitted by the modulator(after being spread). This will add additional delay to the incoming signal, wewill get over this delay in the coming section.

3.2 The BPSK Demodulator Design

In this section we will demonstrate the over all design of the BPSK Demodulatorcircuit. It is based on the Block diagram of the DS-SS receiver shown in fig.(1.4).

The signal entering the receiver is first multiplied by the carrier frequency,to demodulate the spread signal. After the multiplication process we will obtainm(t). This signal contains higher frequency components that are filtered out


Gain 1 2 4 6 8 10R1 1.422 1.126 0.824 0.617 0.521 0.462R2 5.399 2.250 1.537 2.051 2.429 2.742R3 Open 6.752 3.148 3.203 3.372 3.560R4 0 6.752 9.444 16.012 23.602 32.038C1 0.33C C 2C 2C 2C 2C

Table 3.1: Second order Low Pass Batterworth Filter design values (All resistorvalues are in KΩ ).

Figure 3.2: The Filtered output and the output of the Demodulator’s Multiplier.


Figure 3.3: The filtered output and the output of the Comparator.

by our Sallen–Key LPF, which will give us an un–shaped analog signal, as theone shown in fig.(3.3). This is shaped by using a simple Comparator circuit,to obtain a shaped signal like the one shown in fig.(3.3). Another issue risesat this moment, which is the period of each bit. We have to have a matchedperiod like the original signal sent to be able to reconstruct it again, cause anykind of mismatch in the bit period will result in an error in the detected signal,after being despread. So to ensure that we have proper bit periods, i inserteda D-FF with a clock frequency of 200KHz, to reconstruct the proper periods ofthe detected bits. It was inserted after the Comparator.

Comparing the sent and detected spread signals, we will notice that there isa delay of 1–bit between the two, as shown in fig.(3.4). This 1–bit delay has atiming delay of Tdelay = 1

100KHz = 0.01mS. Which means that we have to havethe same amount of delay in the receiver’s PN signal, in order to have an exacttiming (synchronization) edges when being multiplied with the received signal.I added a 1–bit delay to the PN signal, before it entered the Digital Multiplier,i.e. the XNOR gate. The inputs of the XNOR gate after adding the delay areshown in fig.(3.5). The delay of 1–bit of the PN signal was achieved using twoD–FFs, that has inverted Clocks with each other, each of 200KHz.

The signal is then applied to one of the XNOR’s gate inputs, the otherhas the delayed PN sequence. The output of the XNOR gate is the despreadreceived signal, which is an exact replica of the original transmitted one, theword signal. The two signals are shown in fig.(3.6). The delay of 0.01mS is notthat obvious, because the signal period is (period of 1–bit word) 0.15mS, whichis 15 times the delay.

The full circuit diagram of the receiver is shown in fig.(3.7).


Figure 3.4: A delay of 1–bit is observed, between the transmitted and receivedsignals (before being despread).

Figure 3.5: The inputs to the XNOR gate, after a delay of 1–bit was added tothe PN signal.(down is the PN signal) (up is the incoming signal from D–FF).


Figure 3.6: The original word signal (up), and the received one (down) .

Again, all designs and simulations were conducted using the EWB25.0 soft-ware, which gave me the expected results from such a system, and was morethan enough to fulfill the tasks of this report.

2 c©EWB: Electronics Work Bench 5.0, an electronics simulation tool from Interactive Im-age Technologies 1996.


Figure 3.7: DS-SS receiver circuit diagram.

Chapter 4

Conclusion and FurtherEnhancements

This report described the design of a Direct Sequence-Spread Spectrum system,that included the design of the Modulator and Demodulator circuits. The designand simulations were intended to give anyone who is in the Communicationsfield a very rough insight about such systems, which are starting to invade theTelecommunication market. Or to be more precise, they are already in it foryears. But we started to see their wide spread recently. So, this report describeshow to design simple systems based on the idea of DS-SS technique.

The design was a total success. All the circuits functioned properly, and canbe implemented easily to demonstrate the exact behavior of DS-SS systems. Asi mentioned before, this design can be implemented physically, using availablecomponents like the familiar 74XX logic family, and a couple of analog deviceslike resistors, and capacitors.

We verified in this design that DS-SS can be of commercial use, and in fact itis used in our daily used Cell Phones. They are using CDMA1 technique, whichis based on DS-SS. The difference between our design and the commercial oneis that many different factors are taken into account in the ones used, whileour design is just a simplified version that is based on the implementation anddesign of the original basic DS-SS block diagram, for educational purposes.

Finally, i hope that this report has supplied you with some new information,techniques, and ideas, and i wish that you haven’t found any difficulties readingit2. Again, it is intended to be as an educational supplement for any advancedcommunications course, were the student wants to see a practical applicationon what he is studying.

1Code Division Multiple Access2Any comments of any kind are highly appreciable and welcomed. Please do not hesitate

to send me your comment what so ever. As i said, this is a report for educational purposes,so if you have any question, or comment, please send me an e-mail, and i’ll do my best toanswer you. My e-mail is : [email protected]

21

Bibliography

[EM88] E. I. El-Masri. Analog Filter Design. Technical University of NovaScotia, 1988.

[GRM99] Michel Gossens, Sebastian Rahtz, and Frank Mittelbach. The LATEXGraphics Companion. Addison–Wesley, fourth edition, 1999.

[Hay88] Simon Hayken. Digital Communications. John Wiley and Sons, sec-ond edition, 1988.

[Hay94] Simon Hayken. Communication Systems. John Wiley and Sons, thirdedition, 1994.

[KD99] Helmut Kopka and Patric Daly. A Guide To LATEX: Dcument Prepa-ration for Bigenners and Advanced Users. Addison–Wesley, thirdedition, 1999.

[Rap96] Theodore Rapparport. Wireless Communications. Prentice–Hall Inc.,third edition, 1996.

[Raz98] Behzad Razavi. RF Microelectronics. Prentice–Hall Inc., second edi-tion, 1998.

[SA99] Mohammad Sharawi and Husam Abu Ajwah. Digital communicationtraining kit. Technical report, Princess Sumaya University Collegefor Technology, 1999.

[Skl88] Bernard Sklar. Digital Communications. Prentice–Hall Inc., thirdedition, 1988.

[SS94] A. Sedra and K. Smith. Microelectronic Circuits. John Wiley andSons, third edition, 1994.

22

BIBLIOGRAPHY 23

Mohammad SharawiElectronics Engineer

Obtained his B.Sc in Electronics Engineeringwith Honors from Princess SumayaUniversity College for Technology in

Amman–Jordan in Feb 2000.His interests are in RF circuit Design, Digital

Communications, Wireless Systems, andVLSI.

Ds Ss Circuit

Documents

parallel load

original word

bit binary

word xnor

bpsk modulator

ss signal

bit word signal

spread spectrum