SENDING SMS THROUGH BLOCK SPOT AREA IN AN INNOVATIVE MANNER CHAPTER1 Sending SMS through black spot area in an innovative manner 1.1.Aim : main aim of this project is to develop an embedded system to send a message from block spot area using GSM and ZIGBEE. 1.2.Description : Block spot is nothing but an area where we could not find any signal. Even in cities also sometimes we may not have signals inside the room. Through such area sending or calling is tedious. Here our project is useful to create a signal and sending SMS In this work mainly we will use two different frequencies like GSM(1800MHz) and ZIGBEE(2.4GHz). by using these 2 wireless communications first we will create a signal in between zigbee and message will be sent through GSM. 1.3.Operation : In this project we are having 2 embedded developed boards, one contains ZIGBEE and keypad and the other 1
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SENDING SMS THROUGH BLOCK SPOT AREA IN AN INNOVATIVE MANNER
CHAPTER1
Sending SMS through black spot area in an innovative manner
1.1.Aim :
main aim of this project is to develop an embedded system to send a message
from block spot area using GSM and ZIGBEE.
1.2.Description :
Block spot is nothing but an area where we could not find any signal. Even in
cities also sometimes we may not have signals inside the room. Through such area
sending or calling is tedious. Here our project is useful to create a signal and sending
SMS
In this work mainly we will use two different frequencies like GSM(1800MHz)
and ZIGBEE(2.4GHz). by using these 2 wireless communications first we will create a
signal in between zigbee and message will be sent through GSM.
1.3.Operation :
In this project we are having 2 embedded developed boards, one contains
ZIGBEE and keypad and the other contains ZIGBEE and GSM. The first board we will
place at black spot area and the second board we will place in the signal area. Whenever
we will type a message and press an enter button in the first board it will sends the
information to the other zigbee board where a GSM is also arranged and the GSM will
sends the message for the destination mobile
The system uses a compact circuitry built around flash version of at89s52
microcontroller with a non-volatile memory capable of retaining the password data for
over ten years. The user can modify the password. Programs are developed in embedded
c. Isp is used to dump the code into the microcontroller.
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1.4.SOFTWARE:
EMBEDDED ‘C’
RIDE TO WRITE CODE
ISP TO BURN THE CHIP
1.5.HARDWARE:
AT89S52 BASED OUR OWN DEVELOPED BOARD
POWER SUPPLY
ZIGBEE MODULES
GSM MODEM.
MAX232
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1.6.BLOCK DIAGRAM OF TRANSMITER
1.6.block diagram
1.7.RECEIVER :
1.7.reseiver
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MICROCONTROLLER
AT89S52
LCD
zigbee
KEYPAD TO TYPE THE MESSAGE
Crystal
RPS
MICROCONTROLLER
AT89S52 Crystal
RPS
zigbee
MAX232 GSM
SENDING SMS THROUGH BLOCK SPOT AREA IN AN INNOVATIVE MANNER
CHAPTER 2
EMBEDDED MICROCONTROLLER AND HARDWARE2.1.INTRODUCTION:
Micro-controller unit is constructed with ATMEL 89C52 Micro-controller chip.
The ATMEL AT89C52 is a low power, higher performance CMOS 8-bit microcomputer
with 4K bytes of flash programmable and erasable read only memory (PEROM). Its
high-density non-volatile memory compatible with standard MCS-51 instruction set
makes it a powerful controller that provides highly flexible and cost effective solution to
control applications.
Micro-controller works according to the program written in it. The program is
written in such a way, so that the output from the ADC will be converted into its
equivalent voltage and based on the magnitude of the voltage, it calculates the parameter
value. Now this magnitude is again digitalized and fed to LCD display unit through the
latch.
Micro-controllers are "embedded" inside some other device so that they can
control the features or actions of the product. Another name for a micro-controller,
therefore, is "embedded controller". Micro-controllers are dedicated to one task and run
one specific program. The program is stored in ROM (read-only memory) and generally
does not change. Micro-controllers are often low-power devices. A battery-operated
Microcontroller might consume 50 milli watts. A micro-controller has a dedicated input
device and often (but not always) has a small LED or LCD display for output. A micro-
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controller also takes input from the device it is controlling and controls the device by
sending signals to different components in the device
2.2.MICROCONTROLLER (89C52):
2.2.1.Microprocessor has following instructions to perform:
1.Reading instructions or data from program memory ROM.
2.Intrepreting the instruction and executing it.
3.Microprocessor Program is a collection of instructions stored in nonvolatile memory.
4.Read Data from I/O device
5.Process the input read, as per the instructions read in program memory.
6.Read or write data to Data memory.
7.Write data to I/O device and output the result of processing to O/P device.
2.2.2.NECESSITY OF MICROCONTROLLERS:
Microprocessors brought the concept of programmable devices and made many
applications of intelligent equipment. Most applications, which do not need large amount
of data and program memory, tended to be:
Costly: The microprocessor system had to satisfy the data and program
requirements so, sufficient RAM and ROM are used to satisfy most applications .The
peripheral control equipment also had to be satisfied. Therefore, almost all-peripheral
chips were used in the design. Because of these additional peripherals cost will be
comparatively high.
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An example:
8085 chip needs: An Address latch for separating address from multiplex address
and data.32-KB RAM and 32-KB ROM to be able to satisfy most applications. As also
Timer / Counter, Parallel programmable port, Serial port, Interrupt controller are needed
for its efficient applications. In comparison a typical Micro controller 8051 chip has all
that the 8051 board has except a reduced memory as follows.
4K bytes of ROM as compared to 32-KB, 128 Bytes of RAM as compared to 32-KB.
Bulky: On comparing a board full of chips (Microprocessors) with one chip with
all components in it (Micro controller).
Debugging: Lots of Microprocessor circuitry and program to debug. In Micro
controller there is no Microprocessor circuitry to debug. Slower Development time: As
we have observed Microprocessors need a lot of debugging at board level and at program
level, where as, Micro controller do not have the excessive circuitry and the built-in
peripheral chips are easier to program for operation.
So peripheral devices like Timer/Counter, Parallel programmable port, Serial
Communication Port, Interrupt controller and so on, which were most often used were
integrated with the Microprocessor to present the Micro controller .RAM and ROM also
were integrated in the same chip. The ROM size was anything from 256 bytes to 32Kb or
more. RAM was optimized to minimum of 64 bytes to 256 bytes or more.
Typical Micro controller have all the following features:
->8/16/32 CPU ->Instruction set rich in I/O & bit
operations.
->One or more I/O ports. ->One or more timer/counters.
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-> One or more PWM output ->One or more serial communication
ports.
Analog to Digital /Digital to Analog converter ->Network controlled
interface
One or more interrupt inputs and an interrupt controller
2.2.3.Why AT 89C51? :
The system requirements and control specifications clearly rule out the use of 16,
32 or 64 bit micro controllers or microprocessors. Systems using these may be earlier to
implement due to large number of internal features. They are also faster and more reliable
but, the above application is satisfactorily served by 8-bit micro controller. Using an
inexpensive 8-bit Microcontroller will doom the 32-bit product failure in any competitive
market place.
Coming to the question of why to use AT89C52 of all the 8-bit Microcontroller
available in the market the main answer would be because it has 4 Kb on chip flash
memory which is just sufficient for our application. The on-chip Flash ROM allows the
program memory to be reprogrammed in system or by conventional non-volatile memory
Programmer. Moreover ATMEL is the leader in flash technology in today’s market place
and hence using AT 89C52 is the optimal solution.
2.2.4.8052 micro controller architecture:
The 8051 architecture consists of these specific features:
Eight –bit CPU with registers A (the accumulator) and B
Sixteen-bit program counter (PC) and data pointer (DPTR)
Eight- bit stack pointer (PSW)
Eight-bit stack pointer (Sp)
Internal ROM or EPROM (8751) of 0(8031) to 4K (8051)
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Internal RAM of 128 bytes:
1. Four register banks, each containing eight registers
2. Sixteen bytes, which maybe addressed at the bit level
3. Eighty bytes of general- purpose data memory
Thirty –two input/output pins arranged as four 8-bit ports:p0-p3
Two 16-bit timer/counters: T0 and T1
Full duplex serial data receiver/transmitter: SBUF
Control registers: TCON, TMOD, SCON, PCON, IP, and IE
Two external and three internal interrupts sources.
Oscillator and clock circuits.
2.2.4.Functional block diagram of micro controller
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2.2.5.The 8052 oscillator and clock:
The heart of the 8052 circuitry that generates the clock pulses by which all the
internal all internal operations are synchronized. Pins XTAL1 And XTAL2 is provided
for connecting a resonant network to form an oscillator. Typically a quartz crystal and
capacitors are employed. The crystal frequency is the basic internal clock frequency of
the microcontroller. The manufacturers make 8051 designs that run at specific minimum
and maximum frequencies typically 1 to 16 MHz.
2.3.Types of memory:
The 8052 have three general types of memory. They are on-chip memory,
external Code memory and external Ram. On-Chip memory refers to physically existing
memory on the micro controller itself. External code memory is the code memory that
resides off chip. This is often in the form of an external EPROM. External RAM is the
Ram that resides off chip. This often is in the form of standard static RAM or flash
RAM.
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a) Code memory
Code memory is the memory that holds the actual 8052 programs that is to be run.
This memory is limited to 64K. Code memory may be found on-chip or off-chip. It is
possible to have 4K of code memory on-chip and 60K off chip memory simultaneously.
If only off-chip memory is available then there can be 64K of off chip ROM. This is
controlled by pin provided as EA
b) Internal RAM
The 8051 have a bank of 128 of internal RAM. The internal RAM is found on-
chip. So it is the fastest Ram available. And also it is most flexible in terms of reading
and writing. Internal Ram is volatile, so when 8052 is reset, this memory is cleared. 128
bytes of internal memory are subdivided. The first 32 bytes are divided into 4 register
banks. Each bank contains 8 registers. Internal RAM also contains 128 bits, which are
addressed from 20h to 2Fh. These bits are bit addressed i.e. each individual bit of a byte
can be addressed by the user. They are numbered 00h to 7Fh. The user may make use of
these variables with commands such as SETB and CLR.
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2.3.PIN diagram
2.4.Special Function registered memory: Special function registers are the areas
of memory that control specific functionality of the 8052 micro controller.
a) Accumulator (0E0h): As its name suggests, it is used to accumulate the results of
large no of instructions. It can hold 8 bit values.
b) B register (0F0h):The B register is very similar to accumulator. It may hold 8-bit
value. The b register is only used by MUL AB and DIV AB instructions. In MUL AB the
higher byte of the product gets stored in B register. In div AB the quotient gets stored in
B with the remainder in A.
c)Stack pointer (81h): The stack pointer holds 8-bit value. This is used to indicate
where the next value to be removed from the stack should be taken from. When a value
is to be pushed onto the stack, the 8051 first store the value of SP and then store the
value at the resulting memory location. When a value is to be popped from the stack, the
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8052 returns the value from the memory location indicated by SP and then decrements
the value of SP.
d) Data pointer: The SFRs DPL and DPH work together work together to represent a
16-bit value called the data pointer. The data pointer is used in operations regarding
external RAM and some instructions code memory. It is a 16-bit SFR and also an
addressable SFR.
e) Program counter: The program counter is a 16 bit register, which contains the 2 byte
address, which tells the 8052 where the next instruction to execute to be found in
memory. When the 8051 is initialized PC starts at 0000h. And is incremented each time
an instruction is executes. It is not addressable SFR.
f) PCON (power control, 87h): The power control SFR is used to control the 8051’s
power control modes. Certain operation modes of the 8052 allow the 8052 to go into a
type of “sleep mode ” which consume much lee power.
g) TCON (timer control, 88h)
The timer control SFR is used to configure and modify the way in which the
8052’s two timers operate. This SFR controls whether each of the two timers is running
or stopped and contains a flag to indicate that each timer has overflowed. Additionally,
some non-timer related bits are located in TCON SFR. These bits are used to configure the
way in which the external interrupt flags are activated, which are set when an external interrupt
occurs.
h) TMOD (Timer Mode, 89h)
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The timer mode SFR is used to configure the mode of operation of each of the two
timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit
timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers
to only count when an external pin is activated or to count “events ” that are indicated on an
external pin.
i) TO (Timer 0 low/high, address 8A/8C h): These two SFRs taken together
represent timer 0. Their exact behavior depends on how the timer is configured in the
TMOD SFR; however, these timers always count up. What is configurable is how and
when they increment in value.
j) T1 (Timer 1 Low/High, address 8B/ 8D h): These two SFRs, taken together,
represent timer 1. Their exact behavior depends on how the timer is configured in the
TMOD SFR; however, these timers always count up. What is Configurable is how and
when they increment in value.
k) P0 (Port 0, address 90h, bit addressable): This is port 0 latch. Each bit of this SFR
corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is
first written on P0 register. e.g., bit 0 of port 0 is pin P0.0, bit 7 is pin p0.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to low level.
l) P1 (port 1, address 90h, bit addressable):This is port latch1. Each bit of this SFR
corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is
first written on P0 register. e.g., bit 0 of port 0 is pin P1.0, bit 7 is pin P1.7. Writing a
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value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to low level
m) P2 (port 2, address 0A0h, bit addressable):
This is a port latch2. Each bit of this SFR corresponds to one of the pins on a
micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g.,
bit 0 of port 0 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will
send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low
level.
n) P3(port 3,address B0h, bit addressable): This is a port latch3. Each bit of this SFR
corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is
first written on P0 register. e.g., bit 0 of port 0 is pin P3.0, bit 7 is pin P3.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to low level
o) IE (interrupt enable, 0A8h): The Interrupt Enable SFR is used to enable and disable
specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific
interrupts, where the MSB bit is used to enable or disable all the interrupts. Thus, if the
high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt
is enabled by setting a lower bit.
p) IP (Interrupt Priority, 0B8h): The interrupt priority SFR is used to specify the
relative priority of each interrupt. On 8051, an interrupt maybe either low or high
priority. An interrupt may interrupt interrupts. For e.g., if we configure all interrupts as
low priority other than serial interrupt. The serial interrupt always interrupts the system,
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even if another interrupt is currently executing. However, if a serial interrupt is executing
no other interrupt will be able to interrupt the serial interrupt routine since the serial
interrupt routine has the highest priority.
q) PSW (Program Status Word, 0D0h): The program Status Word is used to store a
number of important bits that are set and cleared by 8051 instructions. The PSW SFR
contains the carry flag, the auxiliary carry flag, the parity flag and the overflow flag.
Additionally, it also contains the register bank select flags, which are used to select,
which of the “R” register banks currently in use.
r) SBUF (Serial Buffer, 99h): SBUF is used to hold data in serial communication. It is
physically two registers. One is writing only and is used to hold data to be transmitted out
of 8051 via TXD. The other is read only and holds received data from external sources
via RXD. Both mutually exclusive registers use address 99h.
2 .5.I/O ports:
One major feature of a microcontroller is the versatility built into the input/output
(I/O) circuits that connect the 8051 to the outside world. The main constraint that limits
numerous functions is the number of pins available in the 8051 circuit. The DIP had 40
pins and the success of the design depends on the flexibility incorporated into use of
these pins. For this reason, 24 of the pins may each used for one of the two entirely
different functions which depend, first, on what is physically connected to it and, then, on
what software programs are used to “program” the pins.
PORT 0: Port 0 pins may serve as inputs, outputs, or, when used together, as a bi
directional low-order address and data bus for external memory. To configure a pin as
input, 1 must be written into the corresponding port 0 latch by the program. When used
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for interfacing with the external memory, the lower byte of address is first sent via
PORT0, latched using Address latch enable (ALE) pulse and then the bus is turned
around to become the data bus for external memory.
PORT 1: Port 1 is exclusively used for input/output operations. PORT 1 pins have no
dual function. When a pin is to be configured as input, 1 is to be written into the
corresponding Port 1 latch.
PORT 2: Port 2 may be used as an input/output port. It may also be used to supply a high
–order address byte in conjunction with Port 0 low-order byte to address external
memory. Port 2 pins are momentarily changed by the address control signals when
supplying the high byte a 16-bit address. Port 2 latches remain stable when external
memory is addressed, as they do not have to be turned around (set to 1) for data input as
in the case for Port 0.
PORT 3: Port 3 may be used to input /output port. The input and output functions can be
programmed under the control of the P3 latches or under the control of various special
function registers. Unlike Port 0 and Port 2, this can have external addressing functions
and change all eight-port bits when in alternate use, each pin of port 3 maybe individually
programmed to be used as I/O or as one of the alternate functions. The Port 3 alternate
uses are:
Pin Alternate Use SFRP3.0 - RXD Serial data input SBUFP3.1 - TXD Serial data output SBUFP3.2 - INTO 0 External interrupt 0 TCON.1P3.3 - INTO 1 External interrupt 1 TCON.3P3.4 - T0 External Timer 0 input TMODP3.5 – T1 External timer 1 input TMODP3.6 - WR External memory write pulse -P3.7 - RD External memory read pulse -
2.6.INTERRUPTS:
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Interrupts are hardware signals that are used to determine conditions that exist in
external and internal circuits. Any interrupt can cause the 8052 to perform a hardware
call to an interrupt –handling subroutine that is located at a predetermined absolute
address in the program memory.
Five interrupts are provided in the 8052. Three of these are generated
automatically by the internal operations: Timer flag 0, Timer Flag 1, and the serial port
interrupt (RI or TI) Two interrupts are triggered by external signals provided by the
circuitry that is connected to the pins INTO 0 and INTO1. The interrupts maybe enable or
disabled, given priority or otherwise controlled by altering the bits in the Interrupt
Enabled (IE) register, Interrupt Priority (IP) register, and the Timer Control (TCON)
register. . These interrupts are mask able i.e. they can be disabled. Reset is a non
maskable interrupt which has the highest priority. It is generated when a high is applied
to the reset pin. Upon reset, the registers are loaded with the default values.
Each interrupt source causes the program to do store the address in PC onto the
stack and causes a hardware call to one of the dedicated addresses in the program
memory. The appropriate memory locations for each for each interrupt are as follows:
Interrupt Address
RESET 0000
IE0 (External interrupt 0) 0003
TF0 (Timer 0 interrupt) 000B
IE1 (External interrupt 1) 0013
TF1 (Timer 1 interrupt) 001B
SERIAL 0023
2.7.CRYSTAL OSCILLATOR:
DESCRIPTION:
If a piezoelectric crystal, usually quartz has electrodes plated on opposite faces
and if a potential is applied between these electrodes, forces will be exerted on the bound
charges within the crystal. If this device is properly mounted deformations takes place
within the crystal, and electromechanical system is formed which will vibrate when
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properly excited. The resonant frequency and the Q depend upon the crystal dimensions,
how the surfaces are oriented with respect to its axes and how the device is mounted.
Frequency ranging from few kilohertz to a few megahertz, and Q’s in the range from
several thousand to several hundred thousand, are commercially available. These
extraordinarily high values of Q and the fact that the characteristics of quartz are
extremely stable with respect to time and temperature account for the exceptional
frequency stability of oscillators incorporating crystals.
Figure1: SYMBOL
CHARACTERSTICS
2.7.characteristics
It covers every significant performance characteristics of crystals such as
resonance frequency, resonance mode, load capacitance, series resistance, holder
capacitance, motional inductance and capacitance, and drive level.
Quartz crystals are available in a myriad of shapes and sizes, and can range
widely in performance specifications. These specifications include resonance frequency,
resonance mode, load capacitance, series resistance, holder capacitance, motional
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inductance and capacitance, and drive level. Understanding these parameters and how
they relate to the crystal's performance will allow you to successfully specify crystals for
your circuit application.
A quartz crystal can be modeled as a series LRC circuit in parallel with a shunt
capacitor. Crystals below 30MHz are often specified at the fundamental frequency, but
above 30MHz they are typically specified as 3rd, 5th, or even 7th overtone (overtones
occur only at odd multiples). It's important to know whether the oscillator is operating in
fundamental or overtone mode. An overtone is similar in concept to a harmonic, with the
exception that crystal oscillation overtones are not exact integer multiples of the
fundamental. Selection of overtone is based upon using the lowest possible overtone that
will result in a crystal fundamental frequency below 30MHz. The vendor calibrates a 3rd
overtone crystal at the 3rd overtone, not the fundamental. For example, most crystal
vendors will automatically give you a 3rd overtone 50MHz crystal if you don't specify
fundamental mode or an overtone mode. If you plug a 50MHz 3rd overtone crystal into
an oscillator that expects a fundamental-mode crystal, you are likely to have an oscillator
running at 50/3 or 16.666MHz! If you don't know the frequency mode of your crystal,
contact the designer or the manufacturer of the oscillator circuit.
The majority of clock sources for microcontrollers can be grouped into two types:
those based on mechanical resonant devices, such as crystals and ceramic resonators, and
those based on electrical phase-shift circuits such as RC (resistor, capacitor) oscillators.
Silicon oscillators are typically a fully integrated version of the RC oscillator with the
added benefits of current sources, matched resistors and capacitors, and temperature-
compensation circuits for increased stability. Two examples of clock sources are
illustrated in Figure 1. Figure 1a shows a Pierce oscillator configuration suitable for use
with mechanical resonant devices like crystals and ceramic resonators, while Figure 1b
shows a simple RC feedback oscillator.
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2.8. Basic Components of Embedded System
Embedded Hardware, Embedded Software/Firmware, RTOS or Real Time Kernel
2.9. MEMORY MODELS
2.9.1. MEMORY ORGANIZATION
All 80C52 devices have separate address spaces for program and data memory, as shown
in Figures 1 and 2. The logical separation of program and data memory allows the data
memory to be accessed by 8-bit addresses, which can be quickly stored and manipulated
by an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also be generated
through the DPTR register. Program memory (ROM, EPROM) can only be read, not
written.
There can be up to 64k bytes of program memory. In the 80C51, the lowest 4k
bytes of program are on-chip. In the ROM less versions, all program memory is external.
The read strobe for external program memory is the PSEN (program store enable). Data
Memory (RAM) occupies a separate address space from Program Memory. In the 80C52,
the lowest 128 bytes of data memory are on-chip. Up to 64k bytes of external RAM can
be addressed in the external Data Memory space. In the ROM less version, the lowest
128 bytes are on-chip. The CPU generates read and write signals, RD and WR, as needed
during external Data Memory accesses. External Program Memory and external Data
Memory may be combined if desired by applying the RD and PSEN signals to the inputs
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of an AND gate and using the output of the gate as the read strobe to the external
Program/Data memory.
A.Program Memory
After reset, the CPU begins execution from location 0000H. Each interrupt is
assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to
that location, where it commences execution of the service routine.External Interrupt 0,
for example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its
service routine must begin at location 0003H. If the interrupt is not going to be used, its
service location is available as general purpose Program Memory.
The interrupt service locations are spaced at 8-byte intervals: 0003Hfor External
Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc.
If an interrupt service routine is short enough (as is often the case in control applications),
it can reside entirely within that 8-byte interval. Longer service routines can use a jump
instruction to skip over subsequent interrupt locations, if other interrupts are in use.The
lowest 4k bytes of Program Memory can either be in the on-chip ROM or in an external
ROM. This selection is made by strapping the EA (External Access) pin to either VCC,
or VSS. In the 80C52, if the EA pin is strapped to VCC, then the program fetches to
addresses 0000H through 0FFFH are directed to the internal ROM. Program fetches to
addresses 1000H through FFFFH are directed to external ROM.
If the EA pin is strapped to VSS, then all program fetches are directed to external
ROM. The ROMless parts (8031, 80C31, etc.) must have this pin externally strapped to
VSS to enable them to execute from external Program Memory. The read strobe to
external ROM, PSEN, is used for all external program fetches. PSEN is not activated for
internal program fetches. The hardware configuration for external program execution is
shown in Figure 4. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions
during external Program Memory fetches. Port 0 (P0 in Figure 4) serves as a multiplexed
address/data bus. It emits the low byte of the Program Counter (PCL) as an address, and
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then goes into a float state awaiting the arrival of the code byte from the Program
Memory. During the time that the low byte of the Program Counter is valid on Port 0, the
signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile,
Port 2 (P2 in Figure 4) emits the high byte of the Program Counter (PCH). Then PSEN
strobes the EPROM and the code byte is read into the microcontroller. Program Memory
addresses are always 16 bits wide, even though the actual amount of Program Memory
used may be less than 64k bytes. External program execution sacrifices two of the 8-bit
ports, P0 and P2, to the function of addressing the Program Memory.
B.Data Memory
The CPU in this case is executing from internal ROM. Port 0 serves as a
multiplexed address/data bus to the RAM, and 3 lines of Port 2 are being used to page the
RAM. The CPU generates RD and WR signals as needed during external RAM accesses.
There can be up to 64k bytes of external Data Memory. External Data Memory addresses
can be either 1 or 2 bytes wide. One-byte addresses are often used in conjunction with
one or more other I/O lines to page the RAM, as shown in Figure 5. Two-byte addresses
can also be used, in which case the high address byte is emitted at Port 2. Internal Data
Memory is mapped in Figure 6. The memory space is shown divided into three blocks,
which are generally referred to as the Lower 128, the Upper 128, and SFR space. Internal
Data Memory addresses are always one byte wide, which implies an address space of
only 256 bytes. However, the addressing modes for internal RAM can in fact
accommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH access
one memory space, and indirect addresses higher than 7FH access a different memory
space. Thus Figure 6 shows the Upper 128 and SFR space occupying the same block of
addresses, 80H through FFH, although they are physically separate entities. The Lower
128 bytes of RAM are present in all 80C52 devices as mapped in Figure 7. The lowest 32
bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers
as R0 through R7. Two bits in the Program Status Word (PSW) select which register
bank is in use. This allows more efficient use of code space, since register instructions are
shorter than instructions that use direct addressing. The next 16 bytes above the register
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banks form a block of bit-addressable memory space. The 80C52 instruction set includes
a wide selection of single-bit instructions, and the 128 bits in this area can be directly
addressed by these instructions. The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect
addressing. The Upper 128 (Figure 8) can only be accessed by indirect addressing. Figure
9 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port
latches, timers, peripheral controls, etc. These registers can only be accessed by direct
addressing. Sixteen addresses in SFR space are both byte- and bit-addressable. The bit-
addressable SFRs are those whose address ends in 0H or 8H.
2.9.2.Types of memory:
The 89C52 have three general types of memory. They are on-chip memory,
external Code memory and external Ram. On-Chip memory refers to physically existing
memory on the micro controller itself. External code memory is the code memory that
resides off chip. This is often in the form of an external EPROM. External RAM is the
Ram that resides off chip. This often is in the form of standard static RAM or flash
RAM.
a.Code memory
Code memory is the memory that holds the actual 89C52 programs that is to be
run. This memory is limited to 64K. Code memory may be found on-chip or off-chip. It
is possible to have 4K of code memory on-chip and 60K off chip memory
simultaneously. If only off-chip memory is available then there can be 64K of off chip
ROM. This is controlled by pin provided as EA
b.Internal RAM
The 89C52 have a bank of 256 of internal RAM. The internal RAM is found on-
chip. So it is the fastest Ram available. And also it is most flexible in terms of reading
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and writing. Internal Ram is volatile, so when 89C52 is reset, this memory is cleared.
256 bytes of internal memory are subdivided. The first 32 bytes are divided into 4
register banks. Each bank contains 8 registers. Internal RAM also contains 256 bits,
which are addressed from 20h to 2Fh. These bits are bit addressed i.e. each individual bit
of a byte can be addressed by the user. They are numbered 00h to 7Fh. The user may
make use of these variables with commands such as SETB and CLR.
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CHAPTER 3
ZigBee3.1.INTRODUCTION
ZigBee module. The €1 coin, shown for size reference, is about 23 mm (0.9 inch)
in diameter.
3.1.zigbee
ZigBee is a specification for a suite of high level communication protocols using
small, low-power digital radios based on an IEEE 802 standard for personal area
networks. Applications include wireless light switches, electrical meters with in-home-
displays, and other consumer and industrial equipment that requires short-range wireless
transfer of data at relatively low rates. The technology defined by the ZigBee
specification is intended to be simpler and less expensive than other WPANs, such as
Bluetooth. ZigBee is targeted at radio-frequency (RF) applications that require a low data
rate, long battery life, and secure networking. ZigBee has a defined rate of 250 kbps best
suited for periodic or intermittent data or a single signal transmission from a sensor or
input device.[1] ZigBee based traffic management system have also been implemented.
The name refers to the waggle dance of honey bees after their return to the beehive.[2]