Diploma Project Real Time Motion Estimation on HDTV Video Streams (using the Xilinx FPGA) Supervisor :Averena L.I. Student:Das Samarjit.

Diploma ProjectDiploma Project

Real Time Motion Estimation on Real Time Motion Estimation on HDTV Video Streams HDTV Video Streams

(using the Xilinx FPGA) (using the Xilinx FPGA)

Supervisor :Averena L.I.Supervisor :Averena L.I.StudentStudent :Das Samarjit:Das Samarjit

IntroductionIntroductionIn this project I estimate the motion on HDTV video stream using the fastest motion estimation Algorithm with the FPGA of Xilinx Technology.I also implemented the motion estimation Algorithm to compensate the video frame to achieve better quality with lowest power consumption and flexible platform.Finally I generated the VHDL code for the Data processing unit for it to be implemented inside the FPGA architecture to obtain optimum performance.

Motion Estimation AlgorithmMotion Estimation Algorithm

Frame differencing method.Frame differencing method.Vector quantization methodVector quantization method

Hybrid Video EncodingHybrid Video Encoding

SimplifiedSimplified MPEG-1 EncoderMPEG-1 Encoder

Hybrid Video DecodingHybrid Video Decoding

Simplified MPEG-1 DecoderSimplified MPEG-1 Decoder

Motion EstimationMotion Estimation(Dominant Algorithm(Dominant Algorithm))

Computational Power Distribution (for HDTV Tools)Computational Power Distribution (for HDTV Tools)

Principals of Block Matching Principals of Block Matching Motion EstimationMotion Estimation

Block Matching AlgorithmBlock Matching Algorithm

Block Matching Process-iBlock Matching Process-i

Block Matching Process-iiBlock Matching Process-ii

Block Matching AlgorithmBlock Matching Algorithm

Classification of Motion Classification of Motion EstimationEstimation

Gradient Based Motion Estimation(For Gradient Based Motion Estimation(For Image sequence analysis).Image sequence analysis).

Pel-Recursive Motion Estimation(For Pel-Recursive Motion Estimation(For Image Sequence coding).Image Sequence coding).

Block Matching Motion estimation(Best Block Matching Motion estimation(Best used for Video frame sequence coding).used for Video frame sequence coding).

Frequency Domain Motion estimation (For Frequency Domain Motion estimation (For video Encryption)video Encryption)

The Search AlgorithmThe Search Algorithm

The Tree step search AlgorithmThe Tree step search Algorithm

The 2-D Logarithmic search The 2-D Logarithmic search AlgorithmAlgorithm

Hexagonal Based search AlgorithmHexagonal Based search Algorithm

Motion Estimation Process in Motion Estimation Process in H.264/AVCH.264/AVC

A Fast Integer Pel search to estimate the A Fast Integer Pel search to estimate the motion vector.motion vector.

A fractional pel search to determine the A fractional pel search to determine the motion vector to a higher accuracy.motion vector to a higher accuracy.

Block Diagram of H.264/AVC Block Diagram of H.264/AVC encoderencoder

Motion Compensation with small Motion Compensation with small block sizeblock size

¼ Pixel accurate motion ¼ Pixel accurate motion compensationcompensation

Multiple Reference Picture Multiple Reference Picture motion compensationmotion compensation

Review of reconfigurable array Review of reconfigurable array architecturearchitecture

The Reconfigurable instruction The Reconfigurable instruction cell array architecture (RICA)cell array architecture (RICA)

Design Flow for Algorithm Design Flow for Algorithm implimentation on (RICA)implimentation on (RICA)

Flex WAFE Architecture with FIR Flex WAFE Architecture with FIR Filter DPUFilter DPU

Data stream communicators component Data stream communicators component (LMCs).(LMCs).

Data stream processor component Data stream processor component (DPUs).(DPUs).

Image Algorithm Dependent Global control Image Algorithm Dependent Global control (AC).(AC).

Flex WAFE Architecture with FIR Flex WAFE Architecture with FIR Filter DPUFilter DPU

Flex WAFE Architecture building Flex WAFE Architecture building blockblock

LMC (here data is transferred reorganised LMC (here data is transferred reorganised and stored ).and stored ).

DPU (It processes the data stream DPU (It processes the data stream provided by the LMC).provided by the LMC).

AC (It reacts to the DPU and LMC via AC (It reacts to the DPU and LMC via point to point connection to control the point to point connection to control the algorithm.algorithm.

Comparison between DCT and Comparison between DCT and DWT.DWT.

Performance comparison of ZTE Wavelet coderPerformance comparison of ZTE Wavelet coder

Compression Performance with Compression Performance with respect of human visual system respect of human visual system

HVSHVS

AA BB cc

Test image ROI encodingTest image ROI encoding

A test image used to demonstrate the advantages of ROI A test image used to demonstrate the advantages of ROI codingcoding

Implementation to FPGAImplementation to FPGA

Compairing resources of a FPGA used DCT & Compairing resources of a FPGA used DCT & DWT.DWT.

(a) Xilinx virtex E-Series(a) Xilinx virtex E-Series

(b) Altera’s Apex 20KE series(b) Altera’s Apex 20KE series

No. of CLB used vs. Compression technique

0

1000

2000

3000

4000

DCT DWT

Compression technique

No

. of

CL

B u

sed

No. of CLB used

No. of LE used vs. Compression technique

0

2000

4000

6000

8000

DCT DWT

Compression technique

No

. of

LE

use

d

No. of LE used

(a) (b)

Implimentation of Fast DCT&IDCT Implimentation of Fast DCT&IDCT algorithm using various FPGAalgorithm using various FPGA

Implementation on Xilinx FPGAImplementation on Xilinx FPGA

Performance of Xilinx FPGAPerformance of Xilinx FPGA

Overall ResultOverall Result Observing the result graph we depict that only Xilinx’s Observing the result graph we depict that only Xilinx’s

FPGA is able to process twice the rate required by the FPGA is able to process twice the rate required by the HDTV video stream – which is a remarkable HDTV video stream – which is a remarkable achievement.achievement.

By implementing a very fast DCT algorithm in Xilinx By implementing a very fast DCT algorithm in Xilinx FPGA, I am able to process HDTV frames at a higher FPGA, I am able to process HDTV frames at a higher raterate

So by implementing a very fast DCT algorithm (using the So by implementing a very fast DCT algorithm (using the selected xilinx FPGA) I encrypt therefore encode the selected xilinx FPGA) I encrypt therefore encode the static image of video frame and then I implement the static image of video frame and then I implement the motion estimation algorithm to compensate the video motion estimation algorithm to compensate the video frame to achieve better quality with lowest power frame to achieve better quality with lowest power consumption and time – therefore estimate the motion consumption and time – therefore estimate the motion estimation on HDTV video streams in the real time using estimation on HDTV video streams in the real time using the Xilinx FPGA technology.the Xilinx FPGA technology.