DigitalLogicDesign(EENG2710)

Digital Logic DesignDigital Logic Design

Instructor: Partha GuturuInstructor: Partha Guturu

EE DepartmentEE Department

How will you master Digital How will you master Digital Logic?Logic?

Teaching philosophy-Teaching philosophy- “ “I do not teach my pupils. I provide I do not teach my pupils. I provide

conditions in which they can learn”-conditions in which they can learn”-Albert Einstein Albert Einstein

“ “I hear and I forget. I see and I I hear and I forget. I see and I remember. I do and I understand” - remember. I do and I understand” -

Chinese proverbChinese proverb "Give a man a fish and you feed him for "Give a man a fish and you feed him for

a day. Teach a man to fish and you a day. Teach a man to fish and you feed him for a lifetime." -- Chinese feed him for a lifetime." -- Chinese proverb proverb

What does the data say?What does the data say? Even if you Even if you

are are fascinatingfascinating…..…..

People only People only remember remember the first 15 the first 15 minutes of minutes of what you what you saysay

Percent of Students Paying Attention

Time from Start of Lecture (minutes)

100

50

00 10 20 30 40 50 60

What’s so good about our What’s so good about our approach to learning Digital approach to learning Digital

Logic?Logic?Learner-Centric ApproachLearner-Centric Approach

Life-long learningLife-long learning

Support from Bloom’s WorkSupport from Bloom’s Work

Learning by DoingLearning by DoingPractice, Practice and Practice! Need Practice, Practice and Practice! Need

not be afraid of failuresnot be afraid of failuresNo hostile spectatorsNo hostile spectators““MIT graduates and light bulb” episodeMIT graduates and light bulb” episode

We never forget riding a bike- We never forget riding a bike- because we learn after many because we learn after many failures. failures. I've missed more than 9000 shots in my career. I've lost almost 300 games. 26 times, I've been trusted to take the game winning shot and missed. I've failed over and over and over again in my life. And that is why I succeed - Michael Jordan, American

Living Basketball Legend

Digital Logic Design- What is Digital Logic Design- What is it?it?

Explain the Three TermsExplain the Three TermsDigitalDigital

LogicLogic

DesignDesign

Analog Versus Digital Analog Versus Digital SystemsSystems

Continuous Versus DiscreteContinuous Versus Discrete

Which is more accurate?Which is more accurate?

Design an electronic and a Design an electronic and a mechanical system to perform mechanical system to perform arithmeticarithmetic

What does a digital computer do?What does a digital computer do?

Number SystemsNumber SystemsWhy do you count in terms of ten?Why do you count in terms of ten?

How will this cat count?How will this cat count?

Positional NotationPositional Notation

ArithmeticArithmetic

Conversion from one system to Conversion from one system to anotheranother

Negative number representationNegative number representation

Switching LogicSwitching Logic Why binary?Why binary?

How to design an 1-bit How to design an 1-bit binary adder with binary adder with electro-magnetic and electro-magnetic and mechanical mechanical components?components?

Hint: Use RC-Circuits and ON-OFF Hint: Use RC-Circuits and ON-OFF Switches (Relays)Switches (Relays)

Design the switch Design the switch configuration for sumconfiguration for sum

Design the switch Design the switch configuration for carryconfiguration for carry

Adder DesignAdder Design

Half AdderAi

Half AdderBi

Ci-1

S

C

COR Ci

Si

Full AdderAND

XOR

C

SA

B

Half Adder

System and Register Level

Half Adder

A

BC

S

Ai

Bi

Ci

Full Adder

Ci+1

Si

*Black-box functionalities are specified by truth tables

AND Gate OR Gate XOR Gate

Gate Level

A

B

A

B

Physical Design Level

HAFA

A0

B0

A1

B1

S0S1

A

B

A

B

A

B

A

B

f f f

ff f

C0C1

Physical Design of Switches Physical Design of Switches (Relays)(Relays)

V

SpringSpring

V

Normally Open Switch closing on Excitation i.e. Input = 1 (High)

Normally Closed Switch opening on Excitation i.e. Input = 1 (High)

Design

Symbol

HistoryHistory Till 1600 AbacusTill 1600 Abacus John Napier’s Slide Rule (1600)John Napier’s Slide Rule (1600) Blaise Pascal (1642)- Adding MachineBlaise Pascal (1642)- Adding Machine Charles Babbage (1820)- Mechanical ComputerCharles Babbage (1820)- Mechanical Computer Howard Aiken (Harvard) & George Slibitz (Bell labs)- Howard Aiken (Harvard) & George Slibitz (Bell labs)-

Caculator using relays (1930)Caculator using relays (1930) John Mauchly & Presper Eckert Jr. (Univ. of John Mauchly & Presper Eckert Jr. (Univ. of

Pennsylvania)- ENIAC (Vacuum Tube Computer) 1950Pennsylvania)- ENIAC (Vacuum Tube Computer) 1950 Stored Program Concept (John Von Neumann) and Stored Program Concept (John Von Neumann) and

discovery of transistor (John Bardeeen, Walter H. discovery of transistor (John Bardeeen, Walter H. Brittain and William Shockley)Brittain and William Shockley)

Magnetic Core Memory (J. W. Forrester of MIT)Magnetic Core Memory (J. W. Forrester of MIT) Four generations of computers (late 1940s – late Four generations of computers (late 1940s – late

1970s)1970s)

Course ObjectivesCourse ObjectivesThe main objectives of the course are to facilitate you to The main objectives of the course are to facilitate you to

achieve the highest levels in the Bloom’s 6-level Learning achieve the highest levels in the Bloom’s 6-level Learning Taxonomy so that at you, the end of the course, will be able Taxonomy so that at you, the end of the course, will be able to-to-

KnowKnow whatwhat the digital systems are, the digital systems are, howhow they differ from they differ from analog systems and analog systems and whywhy it is advantageous to use the it is advantageous to use the digital systems in digital systems in many applicationsmany applications..

ComprehendComprehend different number systems including the different number systems including the binary system and Boolean algebraic principlesbinary system and Boolean algebraic principles

ApplyApply Boolean algebra to switching logic design and Boolean algebra to switching logic design and simplification.simplification.

AnalyzeAnalyze a given digital system and decompose it into a given digital system and decompose it into logical blocks involving both logical blocks involving both combinational combinational and and sequential sequential circuit circuit elements.elements.

SynthesizeSynthesize a given system starting with problem a given system starting with problem requirements, identifying and designing the building blocks, requirements, identifying and designing the building blocks, and then integrating blocks designed earlierand then integrating blocks designed earlier

ValidateValidate the system functionality and the system functionality and evaluateevaluate the the relative merits of different designs.relative merits of different designs.

Course InformationCourse InformationProvided on the main webpage for Provided on the main webpage for

the course the course i.e.i.e. Current Teaching link Current Teaching link onon

http://www.ee.unt.edu/~guturu/http://www.ee.unt.edu/~guturu/

Logic Gates & SymbolsLogic Gates & Symbols

Boolean AlgebraBoolean AlgebraAlgebra of logical thought and reason, Algebra of logical thought and reason,

introduced by George Boole in 1849.introduced by George Boole in 1849.Used for simplifications of logical Used for simplifications of logical

functionsfunctionsPostulates- Postulates-

Set K of 2 or more elements, closed under 2 Set K of 2 or more elements, closed under 2 binary operations +, and .binary operations +, and .

Existence of 0 and 1 elementsExistence of 0 and 1 elementsCommutative with respect to + and .Commutative with respect to + and .AssociativeAssociativeExistence of ComplementExistence of ComplementDistributive over + and . a+(b.c) = (a+b).Distributive over + and . a+(b.c) = (a+b).

(a+c); a.(b+c) = (a.b) + (a.c)(a+c); a.(b+c) = (a.b) + (a.c)

Principle of DualtyPrinciple of Dualty If an expression is valid, then dual expression If an expression is valid, then dual expression

is also valid. Dual expression is obtained byis also valid. Dual expression is obtained by Replacing all .’s by +’s and vice versaReplacing all .’s by +’s and vice versa All 1’s by 0’s and vice versaAll 1’s by 0’s and vice versa

without changing the position of the brackets, if any.without changing the position of the brackets, if any.

Exercise 1Exercise 1: See whether it holds for all postulates.: See whether it holds for all postulates.

Exercise 2: Exercise 2: One does not verify the postulates, but One does not verify the postulates, but you can understand their implication using Venn you can understand their implication using Venn Diagrams. You can also check whether the Diagrams. You can also check whether the postulates of Boolean algebra indicate alternate postulates of Boolean algebra indicate alternate ways to design the same switching functionality. ways to design the same switching functionality.

Hint: Hint: Use truth tablesUse truth tables

Fundamental TheoremsFundamental Theorems1.1. Idempotency a + a = a; a.a = aIdempotency a + a = a; a.a = a

2.2. Null elements for “+” and “.” a+1=1; a.0=0Null elements for “+” and “.” a+1=1; a.0=0

3.3. Involution a’’ = a where a’ is a complementInvolution a’’ = a where a’ is a complement

4.4. Absorption a+ab = a and a(a+b) = aAbsorption a+ab = a and a(a+b) = a

5.5. a + a’b = a + b and its duala + a’b = a + b and its dual

6.6. ab + ab’ = a and its dualab + ab’ = a and its dual

7.7. ab + ab’c = ab + ac and its dualab + ab’c = ab + ac and its dual

8.8. DeMorgan’s Theorems: (a+b)’ = a’.b’ and DeMorgan’s Theorems: (a+b)’ = a’.b’ and dual. You can generalize it for more variablesdual. You can generalize it for more variables

9.9. Consensus: ab+a’c+bc = ab + a’c and dualConsensus: ab+a’c+bc = ab + a’c and dual

Exercises using TheoremsExercises using TheoremsSimplify the Boolean functions:Simplify the Boolean functions:

1.1. ab’(ab’+b’c)ab’(ab’+b’c)

2.2. y’(x+y+z)y’(x+y+z)

3.3. (w’+x’+y’+z’)(w’+x’+y’+z)(w’+x’+y+z’) (w’+x’+y’+z’)(w’+x’+y’+z)(w’+x’+y+z’) (w’+x’+y+z)(w’+x’+y+z)

4.4. wy’+wx’y+wxyz+wxz’wy’+wx’y+wxyz+wxz’

5.5. {a(b+c)+a’b}’{a(b+c)+a’b}’

6.6. abc+a’d+b’d+cdabc+a’d+b’d+cd

7.7. Write switching function of full adder and Write switching function of full adder and simplify algebraically.simplify algebraically.

More ExercisesMore Exercises8.8. AD’+A’B’+C’D+A’C’+B’D = AD’+(BC)’AD’+A’B’+C’D+A’C’+B’D = AD’+(BC)’

9.9. XY’+Z(X’+Y+W)=Z+XY’XY’+Z(X’+Y+W)=Z+XY’

10.10. X’Z’+YZ+XY’=Y’Z’+X’Y+XZX’Z’+YZ+XY’=Y’Z’+X’Y+XZ

11.11. X’Y’Z’+XYZ+X’Y’Z’+XYZ+(WZ’)’+X’YZ’+W’XY+XY’Z’=W’XY+XYZ(WZ’)’+X’YZ’+W’XY+XY’Z’=W’XY+XYZ+X’Z’+Y’Z’+X’Z’+Y’Z’

Switching FunctionsSwitching FunctionsCan be generated from truth tablesCan be generated from truth tablesTwo FormsTwo Forms

Sum of Products (SOP)Sum of Products (SOP)Product of Sums (POS)Product of Sums (POS)

Canonical SOP and POS and Min & Max Canonical SOP and POS and Min & Max Term DefinitionsTerm Definitions

Challenge- Find why the POS are Challenge- Find why the POS are constructed using 0 output rows and constructed using 0 output rows and variable represented in true form variable represented in true form when they assume zero values as when they assume zero values as opposed to the intuitive SOP opposed to the intuitive SOP convention.convention.

Shannon’s Expansion Shannon’s Expansion TheoremTheorem

f(x1, x2, … , xn) = x1.f(1, x2, …, xn) f(x1, x2, … , xn) = x1.f(1, x2, …, xn) + + x1’.f(0,x2, … , x1’.f(0,x2, … , xn)xn)

Outline of Proof: Put the two values of Outline of Proof: Put the two values of X1 in both L.H.S and R.H.S.X1 in both L.H.S and R.H.S.

Shannon’s Expansion Theorem Shannon’s Expansion Theorem (Dual)(Dual)

f(x1, x2, … , xn) = ( x1 + f(0, x2, …, f(x1, x2, … , xn) = ( x1 + f(0, x2, …, xn) ). xn) ). ( x1’ + f(0,x2, ( x1’ + f(0,x2, … , xn) )… , xn) )

Outline of Proof: Put the two values of Outline of Proof: Put the two values of X1 in both L.H.S and R.H.S.X1 in both L.H.S and R.H.S.

Application of Shannon’s Application of Shannon’s Expansion TheoremsExpansion Theorems

Expanding arbitrary switching Expanding arbitrary switching functions into corresponding canonical functions into corresponding canonical formsforms

Ex: f(A, B, C) = AB + AC’ + A’CEx: f(A, B, C) = AB + AC’ + A’C f(A, B, C) = A (A + C’)f(A, B, C) = A (A + C’) However, a simpler approach is to use However, a simpler approach is to use

the following dual assertions of the following dual assertions of Fundamental Theorem 6 (mainly Fundamental Theorem 6 (mainly based on the distributivity postulates):based on the distributivity postulates):AB + AB’ = AAB + AB’ = A(A + B)(A + B’) = A (A + B)(A + B’) = A

Concept of Incompletely Concept of Incompletely Specified FunctionsSpecified Functions

Hypothetical Digital Design for Mario, the Hypothetical Digital Design for Mario, the Jump-manJump-man Key pad with Key pad with 0-90-9 digits digits Pressing a prime numberPressing a prime number will make Mario move a stepwill make Mario move a step Pressing any other digit will Pressing any other digit will make Mario jump up a stepmake Mario jump up a step

Design a switching function with output as 1 Design a switching function with output as 1 or 0 depending upon the 4-bit input or 0 depending upon the 4-bit input corresponding to the digits 0-9 in BCD corresponding to the digits 0-9 in BCD (Binary Coded Decimals).(Binary Coded Decimals).

How about the 4-bit BCD numbers How about the 4-bit BCD numbers corresponding to corresponding to 10-1510-15? (“Don’t care term” ? (“Don’t care term” concept)concept)

Function Minimization using Function Minimization using Karnaugh MapsKarnaugh Maps

Relationship between Truth tables, Relationship between Truth tables, Venn Diagrams and Karnaugh maps- a Venn Diagrams and Karnaugh maps- a two variable exampletwo variable example

Three variable Karnaugh mapsThree variable Karnaugh mapsExtension of Kanaugh maps to 4 Extension of Kanaugh maps to 4

variablesvariablesApplication of 4 variable maps to the Application of 4 variable maps to the

7-segment display problem (use don’t 7-segment display problem (use don’t care terms!)care terms!)

5 and 6 variable maps5 and 6 variable maps

Karnaugh Maps (contd.)Karnaugh Maps (contd.) Terminology- Implicants, prime Implicants, Terminology- Implicants, prime Implicants,

essential prime implicants and coveressential prime implicants and cover POS form realization Ex: POS form realization Ex: and 6 variable maps (stacking concept)and 6 variable maps (stacking concept) Design constraints other than cost (Read Design constraints other than cost (Read

2.4.2)-2.4.2)- Propagation DelayPropagation Delay Gate Fan-in and Fan-outGate Fan-in and Fan-out Power ConsumptionPower Consumption Size and WeightSize and Weight

Hazard prevention using the consensus Hazard prevention using the consensus theorem in the reverse direction (Read 2.4.2 & theorem in the reverse direction (Read 2.4.2 & 3.8)3.8)

Quine-McCluskey Tabular Quine-McCluskey Tabular MethodMethodExample Problem: f(A,B,C,D) = Example Problem: f(A,B,C,D) =

m(2,4,6,8,9,10,12,13,15)m(2,4,6,8,9,10,12,13,15)4 steps4 steps

Table Formation separating min-terms Table Formation separating min-terms based on number of 1’sbased on number of 1’s

Succesively forming lists by combining Succesively forming lists by combining adjacent termsadjacent terms

Determining essential prime implicantsDetermining essential prime implicantsFinding the minimal cover using a Finding the minimal cover using a

combination of the prime implicants combination of the prime implicants (including necessarily the essential). (including necessarily the essential).

Quine-McCluskey’s Method Quine-McCluskey’s Method (Contd.)(Contd.)

Covering ProcedureCovering ProcedureDominated row and Dominant colum Dominated row and Dominant colum

removalremoval

Ex: f (A, B, C, D)= Ex: f (A, B, C, D)= m(0,1,5,6,7,8,9,10,11,13,14,15)m(0,1,5,6,7,8,9,10,11,13,14,15)

Cyclic PI (Prime Implicant) chart Cyclic PI (Prime Implicant) chart reductionreduction

Ex: f(A,B,C) = Ex: f(A,B,C) = m(1,2,3,4,5,6)m(1,2,3,4,5,6)

Modular Design of Combinational Modular Design of Combinational LogicLogicBuilding Blocks-Building Blocks-

Decoders (Decoders (e.g.e.g. n-to-2 n-to-2nn decoder) decoder) Commercial (TI) MSI decoders (74138: 3-to-8 and Commercial (TI) MSI decoders (74138: 3-to-8 and

74154: 4-to-16 both active low outputs).74154: 4-to-16 both active low outputs). Minimal DesignMinimal Design Design with Fan-in considerations (Tree-type)Design with Fan-in considerations (Tree-type)

Decoders Applications:Decoders Applications: Logic Design: 4 Alternatives with Active High and Logic Design: 4 Alternatives with Active High and

Low types EX: f (Q, X, P) = Low types EX: f (Q, X, P) = m(0,1,4,6,7) = m(0,1,4,6,7) = (2,3,5)(2,3,5)

Other Examples: BCD to Decimal conversion, 7 Other Examples: BCD to Decimal conversion, 7 Segment Display (Common cathode and anode Segment Display (Common cathode and anode Configurations)Configurations)

Address DecodingAddress Decoding Many decoders have enable input also. Many decoders have enable input also.

(Usage Example: Realization of larger (Usage Example: Realization of larger decoders)decoders)

EncoderEncoderAnother building block opposite of the Another building block opposite of the

decoderdecoderConstraint on #inputs (n) and #outputs (S): Constraint on #inputs (n) and #outputs (S):

22SS >= n >= n4 input examples: 4 input examples:

One-and-only one input line active One-and-only one input line active i.e.i.e. 4-to-2 4-to-2 encoder (incoming mail)encoder (incoming mail)

Output 1 if one and only one of the inputs is 1, Output 1 if one and only one of the inputs is 1, otherwise 0. otherwise 0. i.e.i.e. 4-to-3 encoder. 4-to-3 encoder.

Priority Encoders (EX: TI’s 74147 10-to-4 encoder Priority Encoders (EX: TI’s 74147 10-to-4 encoder has to outputs indicating which active line has has to outputs indicating which active line has highest priority, TI’s 74148 8-to-3 encoder with 2 highest priority, TI’s 74148 8-to-3 encoder with 2 additional outputs EO and GS=EO’ and input EI)additional outputs EO and GS=EO’ and input EI)

Multiplexers and Multiplexers and DemultiplexersDemultiplexers

MultiplexerMultiplexerData selectorData selectorTakes in the data from only one of the Takes in the data from only one of the

multiple inputs)multiple inputs)Demultiplexers Demultiplexers

Data Distributor (opposite of Multiplexer)Data Distributor (opposite of Multiplexer)Sends data out on only one of the output Sends data out on only one of the output

lines. lines. Can we use a multiplexer to implement Can we use a multiplexer to implement

a switching function? (Hint: Use it as a a switching function? (Hint: Use it as a decoder)decoder)

AddersAdders

Ripple Carry Adder- the very first Ripple Carry Adder- the very first designdesign

Carry Look Ahead Adder- Carry Look Ahead Adder- CC00 = X = X00.Y.Y0 0 = G = G00

CC11 = X = X11.Y.Y1 1 +C+C00 .(X .(X1 1 Y Y1 1 ) = G) = G11 + G + G00.P.P11

CC22 = G = G22 + C + C11.P.P2 = 2 = GG22 + G + G11.P.P2 2 + G+ G00 .P .P22.P.P11

G above refers to generation term and P G above refers to generation term and P refers to propagation term. You know:refers to propagation term. You know:

SSii = .(X = .(Xi i Y Yi i ) C) Ci-1 i-1 = P = Pi i CCi-1i-1

Adder Cum SubtracterAdder Cum Subtracter

ADDER (7483)

MUX (74157)

A-Bits B-Bits

C0C4

Subtract

Logic Circuits- A TaxonomyLogic Circuits- A Taxonomy

Logic Circuit

Combinational Logic

Sequential Logic

Synchronous

Asynchronous

Sequential LogicSequential Logic

CombinationalLogic

Memory

X1

XN

Z1

ZM

Y1YLy1 yL

State Model: Two Forms of State Model: Two Forms of RepresentationRepresentation

y

YX/ZInput/Output

State Diagram

Present State

Input

y Y/Z

X

Next State/ output

State Table

Small Class Room ProjectSmall Class Room ProjectRequired to design a two state Memory Required to design a two state Memory

device called device called S-R latchS-R latch which has two which has two inputs S (Set) and R (Reset) such thatinputs S (Set) and R (Reset) such that

When S is 1 and R = 0, the device When S is 1 and R = 0, the device output will become 1, irrespective of output will become 1, irrespective of what was before.what was before.

Similarly, when R=1 and S=0, it will be Similarly, when R=1 and S=0, it will be 00

No change for S=R=0No change for S=R=0S = R = 1 is not allowed, hence output S = R = 1 is not allowed, hence output

can be unpredictable in such a situation.can be unpredictable in such a situation. Inputs? State Diagram?Inputs? State Diagram?

Project ExtensionsProject ExtensionsGated SR Latch (One more input)Gated SR Latch (One more input)Delay latch or D-latchDelay latch or D-latchMaster-slave SR Flip-flopsMaster-slave SR Flip-flopsMaster-slave D-Flip-flopMaster-slave D-Flip-flopMaster slave J-K Flip-flopMaster slave J-K Flip-flop(Note: Flip-flop differs from latch in (Note: Flip-flop differs from latch in

that the clock input triggers state that the clock input triggers state change, though the new state change, though the new state depends on the excitation inputs at depends on the excitation inputs at the clock time. Clock here is the the clock time. Clock here is the control signal)control signal)

D-Latch Timing DiagramD-Latch Timing Diagram

D-Latch Timing ConstraintsD-Latch Timing Constraints

Master-Slave SR Flip-flopMaster-Slave SR Flip-flop

Master-Slave D Flip-flopMaster-Slave D Flip-flop

Master-Slave D Flip-flopMaster-Slave D Flip-flop

JK and T-Flip FlopsJK and T-Flip Flops

JK addresses the restrictions in SRJK addresses the restrictions in SRT (toggle flip-flop) can be constructed T (toggle flip-flop) can be constructed

from JK (How?)from JK (How?)

Sequential Logic DesignSequential Logic DesignTypical applicationsTypical applications Shift RegistersShift Registers

Design (SN 74194)Design (SN 74194)Equations:Equations: CK = clock + s0’ s1’CK = clock + s0’ s1’

SSBB = Q = QCC.s0’ + Q.s0’ + QAA. s1’ + B.s0.s1 . s1’ + B.s0.s1 ApplicationsApplications

CountersCounters DesignDesign ApplicationsApplications

General approach to Sequential logic General approach to Sequential logic Design (with Serial Adder Example).Design (with Serial Adder Example).

Steps in Sequential Logic Steps in Sequential Logic SynthesisSynthesis

State Modeling from verbal State Modeling from verbal description of the problem description of the problem (State diagram and Table)(State diagram and Table)

Minimization of States Minimization of States (Partitioning Method)(Partitioning Method)

State AssignmentState Assignment Transition and output Transition and output

tablestables Decide on memory devices Decide on memory devices

(flip-flops) to use and get (flip-flops) to use and get excitation and output excitation and output functions (logic equations) functions (logic equations) for each memory element for each memory element and output.and output.

Draw the circuit diagram Draw the circuit diagram with basic logic gates and with basic logic gates and flip-flopsflip-flops

NS, Z

PS x=0 x=1

A E,0 D,1

B F,0 D,0

C E,0 B,1

D F,0 B,0

E C,0 F,1

F B,0 C,0

Machine M

Steps in Incompletely Specified Steps in Incompletely Specified Sequential Machine SynthesisSequential Machine Synthesis State Modeling from verbal State Modeling from verbal

description of the problem description of the problem (State diagram and Table)(State diagram and Table)

Minimization of States Minimization of States (Merger graphs/Tables, (Merger graphs/Tables, Compatibility/ Implication Compatibility/ Implication graphs)graphs)

State AssignmentState Assignment Transition and output tablesTransition and output tables Decide on memory devices Decide on memory devices

(flip-flops) to use and get (flip-flops) to use and get excitation and output excitation and output functions (logic equations) functions (logic equations) for each memory element for each memory element and output.and output.

Draw the circuit diagram Draw the circuit diagram with basic logic gates and with basic logic gates and flip-flopsflip-flops

NS, Z

PS I1 I2 I3 I4

A - - E,1 -

B C,0 A,1 B,0 -

C C,0 D,1 - A,0

D - E,1 B,- -

E B,0 - C,- B,0

Machine M

Asynchronous Sequential Asynchronous Sequential CircuitsCircuits

Asynchronous Sequential

Circuits

Pulse Mode Circuits

Fundamental Mode Circuits

A Small Project/Problem

involving Pulse Mode Circuits

You are required to design an automatic toll-collecting machine accepting nickels, dimes, and quarters only. Toll is 35 cents. An electro-mechanical system, already available, accepts the coins sequentially (even if they are all dropped in simultaneously) and generates a pulse on one of the three output lines (x5, x10, and x25) corresponding to the three types of the coins received. A reset pulse xr is also produced by a sensor which senses the passing of the car through the toll gate. Your machine should produce a level output that turns a green light ON whenever 35C or more is received. After the car is passed, the machine should turn the light off and resets your machine to initial state. All overpayments are profit for the toll-collecting authority.

What is the difference?

Fundamental Mode CircuitsFundamental Mode CircuitsExample Problem: An asynchronous Example Problem: An asynchronous

sequential circuit has two inputs x1 sequential circuit has two inputs x1 and x2. Initial input state is x1 = x2 and x2. Initial input state is x1 = x2 = 0. The circuit output is 1 if and = 0. The circuit output is 1 if and only if the input state is x1 = x2 = 1 only if the input state is x1 = x2 = 1 and the preceding input state is x1 = and the preceding input state is x1 = 0, x2 = 1.0, x2 = 1.

X1

X2

Z

1 2 4 5 2 3