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3/3/2006 EECS150 Lab Lecture #7 1

Digital Video

EECS150 Spring 2006 – Lab Lecture #7Brian GawaltGreg Gibeling


Today

Digital VideoAdministrative InfoITU-R BT.601ITU-R BT.656Video EncoderI2C BusMore Information


Digital Video (1)

Pixel ArrayA digital image is represented by a matrix of pixels which include color information.

FramesMotion is created by flashing a series of still frames

1920

1080High-Definition Television (HDTV), 2 Mpx

1152

900Workstation, 1 Mpx

800

600PC/Mac, 1‡2 Mpx

640

480Video, 300 Kpx

352

240

SIF,82 Kpx

High-Definition Television (HDTV), 1 Mpx

1280

720


Digital Video (2)Scanning

Images are generated on the screen by scanning pixel lines, left to right, top to bottomEarly CRTs required time to get from the end of a line to the beginning of the next. Therefore each line of video consists of active video portion and a horizontal blanking interval. Even more time is needed for the CRT gun to transition from the end of the last line to the start of the first, requiring each frame to have a vertical blanking interval.To reduce flicker, each frame is divided into two fields: odd and even


Digital Video (3)

ColorsUsually represented as red, green and blue

In the digital domain we could transmit 8 bits for each RGB component.

Transition from Black & WhiteKept compatible with old TV setsAdded separate color or “Chroma” signals

Y: Luma (Traditional Black and White)Cr: Chroma Red (New color signal)Cb: Chroma Blue (New color signal)


Digital Video (4)

Digital Chroma SubsamplingHuman eye is more sensitive to Luma than Chroma; use this to save space and bandwidth

R0

R2

R1

R3

G0

G2

G1

G3

B0

B2

B1

B3

Y0

Y2

Y1

Y3

CB

CB

CB

CB

CR

CR

CR

CR

Y0

Y2

Y1

Y3

CB 0-1

CB 2-3

CR 0-1

CR 0-1

Y0

Y2

Y1

Y3

CB 0-3

CR 0-3

Y0

Y2

Y1

Y3

CB 0-3

CR 0-3

RGB 4:4:4 Y CR CB 4:4:4 4:2:2 (ITU-601) 4:2:0 (MPEG-1) 4:2:0 (MPEG-2)


Administrative Info (1)

Design Review ProcessWalk your lab TA through the module

Control/DatapathTop-down design with interconnections

Errors will be pointed out, but corrections are left up to youIdeal duration: 10 minutesIt’s a team effort!

Convince us you know what you’re doing!


ITU-R BT.601Formerly, CCIR-601.

Designed for digitizing broadcast NTSC

America’s National Television System Committee

Variations: 4:2:0 Chroma SubsamplingPAL (European) version

Component streaming:line i: CB Y CR Y CB Y CR Yline i+1: CB Y CR Y CB Y CRY

Effective Bits/Pixel:4 components / 2 pixels = 32/2 = 16 bits/pixel

16Effective bits/pixel

8Bits per component

4:2:22:1 in X onlyCoincident

Chromasubsampling

InterlacedScan29.97 /secFrame Rate

720 x 507Active Frame Size


ITU-R BT.656 (1)

DetailsPixels/Line: 858Lines/Frame:525Frames/S: 29.97Pixels/S: 13.5M

ActivePixels/Line: 720Lines/Frame:507

BlankingSAV/EAV: 4B/4BBlack filler

718 719 720 721 0 1 2

359 360 0 1

359 360 0 1

736732( )

368366( )

368366( )

857863)(

Y 71

8

Y 71

9C

360

B Y 72

0C

360

R Y 72

1

C 3

59B C 3

59R Y 73

6(73

2)C

368

(366

)B C

368(

366)

R Y 85

5(86

1)C

428

(431

)B

Y 85

6(86

2)

Y 85

7(86

3)C

0 B Y 0

C 0 R Y 1

C 4

28(4

31)

R

C 0 B Y 0

Y 1

C 0 RC 3

59B Y 71

8

Y 71

9C

359

R

Last sampleof digital active line

Sample datafor O instant

First sampleof digital active lineH

Luminancedata, Y

Chrominancedata, CR

Chrominancedata, CB

Replaced bytiming reference

signal

Replaced bydigital blanking data

Replaced bytiming reference

signal

End ofactive video

Start ofactive video

Timing reference signals

Note 1 – Sample identification numbers in parentheses are for 625-line systems where these differ from those for 525-line systems. (See also Recommendation ITU-R BT.803.)

FIGURE 1Composition of interface data stream

D01


ITU-R BT.656 (2)Odd Field (262 Lines)

Total: 262 Lines6 Vertical Blanking254 Active2 Vertical Blanking

Even Field (263 Lines)Total: 263 Lines7 Vertical Blanking253 Active3 Vertical Blanking


ITU-R BT.656 (3)

SAV HeaderF: Field Select (0: Odd, 1: Even)V: Vertical Blanking FlagH: EAV/SAV Flag (0: SAV, 1: EAV)E[3]=V^H, E[2]=F^H, E[1]=F^V, E[0]=F^V^H

E[0]E[1]E[2]E[3]HVF1’b1

1’b01’b01’b01’b01’b01’b01’b01’b0

1’b01’b01’b01’b01’b01’b01’b01’b0

1’b11’b11’b11’b11’b11’b11’b11’b1

P2P3P4P5P6P7P8P9


Video Encoder (1)

Analog Devices ADV7194Supports ITU-R BT.601/656S-Video and Composite OutputsI2C Control (We will give this to you)


Video Encoder (2)

O

O

O

O

O

O

O

O

O

O

Dir

Clock (27MHz, Just send Clock)1VE_CLKIN

Manual Control (Always 1’b0)1VE_SCRESET

Manual Control (Always 1’b1)1VE_BLANK_B_

Manual Control (Always 1’b1)1VE_VSYNC_B_

Manual Control (Always 1’b1)1VE_HSYNC_B_

Active low reset (~Reset)1VE_RESET_B_

PAL/NTSC Mode Select (Always 1’b0)1VE_PAL_NTSC

I2C Data (For Initialization)1VE_SDA

I2C Clock (For Initialization)1VE_SCLK

Outoing NTSC Video (Use Data, 2’b00)10VE_P

DescriptionWidthSignal


Video Encoder (3)DescriptionDirWidthSignal

Pair of PixelsThe line will return data for this pixel pair

O9InRequestPair

Line of Video (Line[7:0], Field)The ROM will return a pixel from this line

O9InRequestLine

Request Data from ROMDIn will be valid after rising edge

O1InRequest

Requested Data from ROMI32DIn

Reset inputI1Reset

Clock input (27MHz)I1Clock


Video Encoder (4)

AD

V7194

Monitor

Outgoing V

ideo(S

-Video O

ut Cable)

32b NTS

C V

ideo(N

o Blanking)

10b NTS

C V

ideo(C

omplete)

Video Line &

Pair

Address

IOR

egI2C

Clock &

data

I2C C

lock & data

Horizontal &

V

ertical Count

I 2C D

one


Video Encoder (5)

Basic DesignStream EAV, Blank, SAV, Active Lines

Generate EAV/SAV/Blank using a multiplexerRegister output data (Timing reasons)

Request Incoming DataRequest it the cycle before you need itClipping data

Minimum data is 0x10Maximum data is 0xF0Otherwise it will appear to be blanking signals


Video Encoder (6)

TestingTest thoroughly

Simulation is difficult with test ROMTry using values which count, so you can see it

Design your testbench earlyPerhaps one partner should design the module, one should design the testbenchEnsure that you test corner cases

First and last linesOff-by-one errors in counters


I2C (1)

ADV7194 Initialization using I2CRequires only 2 wires

Serial Data (Bidirectional)Clock (Driven by master)

Runs at up to 400kHzBidirectional Communication

Given to youComplicated to get rightHard to debug


I2C (2)

Physical ProtocolData

Open collector bidirectional busDriven by sender

ClockOpen collector unidirectional busDriven by masterMay be pulled low to stall transmission

10kΩ Pullup 10kΩ Pullup

DIn

DO

ut

Ena

ble

DIn

DO

ut

Ena

ble

Endpoint BEndpoint A

Bidirectional Open Collector Bus


I2C (3)Protocol

Start ConditionAddressAddress AcknowledgeData TransferData AcknowledgeStop Condition


I2C (4)

ArbitrationAnyone can drive bus at any time

No central arbiterNo short circuits (Impossible in open collector)

Decentralized ArbitrationCheck data bus against value you’re sendingMismatch means someone else is transmitting

So let them finish, and then try againInherently gives preferences to accesses with more 1’b1s in them


More Information

Checkpoint WriteupDocuments Page of the Website

Video in a Nutshell ADV7194 Datasheet

Complete ADV7194 referenceITU-R BT.656 & ITU-R BT.601 Standards

Complete video standardsI2C Bus Specification

READ THE DATASHEETS!