Digital Design – Datapath Components

Digital Design – Datapath Components

Chapter 4 - Datapath Components

2

Digital DesignDatapath Components

Figure 4.1 4-bit parallel load register: (a) internal design, (b) block symbol, and (c) paths when load=0 and load=1.

D

Q

D

Q

D

Q

D

Q

2x1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

load1 0 1 0 1 0 1 0

D

Q

D

Q

D

Q

D

Q

2x1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

load

= 1

1 0 1 0 1 0 1 0

D

Q

D

Q

D

Q

D

Q

2x1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

1 0 1 0 1 0 1 0

load

= 0

I3 I2 I1 I0load

Q3 Q2 Q1 Q0

(a)(b)

(c)

3


Figure 4.2 Weight sampler implemented using a 4-bit parallel load register.

2.2 pounds

3.1 pounds

Present weight

Saved weight

Save

Weight Sampler

b loadI3 I2I1I0

Q3Q2Q1Q0

Scale

4


Figure 4.3 Internal design of the TemperatureHistoryStorage component, using parallel load registers.

a4 a3a2 a1a0 b4b3b2b1b0 c4 c3 c2 c1 c0

I4I3I2I1I0

Q4Q3Q2Q1Q0

t4t3t2t1t0

I4I3I2I1I0

Q4Q3Q2Q1Q0

I4I3I2I1I0

Q4Q3Q2Q1Q0

TemperatureHistoryStorage

clkRa Rb Rcld ld ld

Cnew line

osc

timer

5

a1

a0

C

x y

2x4

D

load

load

load

load

d0

d1

d2

d3

i0

i1

i0

i1

i2

i3s1

s0

d

T

A

I

Mload

8-bit

e

reg0

reg1

reg2

reg3

4x1

From

the

car’s

cent

ral c

ompu

ter

To the above-m

irror display

8

8

8

8

8

8


Figure 4.4 Above-mirror display design.

6


Figure 4.5 An electronic checkerboard.

LED

loadIQ

3x8 decodere i2 i1i0d7 d6 d5 d4 d3 d2 d1 d0

microprocessor

8from

microprocessorfromdecoder

R7 R6 R5 R4 R3 R2 R1 R0

D

R0 10100010

1

0

1

0

0

0

0

1

lit LED

D

i2,i1,i0

e

clk

000 (R0) 001 (R1) 010 (R2) 011 (R3) 100 (R4) 101 (R5) 110 (R6) 111 (R7)

10100010 10100010 10100010 10100010010000101 010000101 010000101 010000101

7


Figure 4.6 Checkerboard after loading registers for initial checker positions.

LED

R7 R6 R5 R4 R3 R2 R1 R0

lit LED

10100010010000101

10100010010000101

10100010010000101

10100010010000101

8


Figure 4.7 Right shift example: sample contents before and after a right shift, and bit-by-bit view of the shift.

1 1 0 1

0 1 1 00

Register contentsbefore shift right

after shift rightRegister contents

shr_in

9


Figure 4.8 Shift register: (a) implementation, (b) paths when shr=1, and (c) register symbol.

D

Q

D

Q

D

Q

D

Q

2x1

Q3 Q2 Q1 Q0

shr_in

1 0 1 0 1 0 1 0shrD

Q

D

Q

D

Q

D

Q

2x1

Q3 Q2 Q1 Q0

1 0 1 0 1 0 1 0

shr=

1

shrshr_in

Q3 Q2 Q1 Q0

(a)

(c)

10


Figure 4.9 Right rotate example: register contents before and after the rotate, and bit-by-bit view of the rotate operation.

1 1 0 1

1 1 1 0

Register contentsbefore rotate right

after rotate rightRegister contents

11


Figure 4.10 Above-mirror display design using shift registers to reduce the number of lines coming from the car’s computer.

a1a0

c x y

2x4

D

shr

shr

shr

shr

d0

d1

d2

d3

i0

i1

i0

i1

i2

i3

s1s0

d

T

A

I

Mshift

4x1

e

reg0

reg1

reg2

reg3

shr_in

shr_in

shr_in

shr_in

Note: this line is 1 bit, rather than 8 bits like before

8

8

8

8

8

12


Figure 4.12 4-bit register with parallel load and shift right operations.

D

Q

D

Q

D

Q

D

Q

4x1

Q3 Q2 Q1 Q0

shr_in

1 0s1 s1shr_in

Q3 Q2 Q1 Q0

I3 I2 I1 I0231 0231 0231 023

s0

I3 I2 I1 I0

s0

0 0 0 0

s1 s0 Operation0 0 Maintain present value0 1 Parallel load1 0 Shift right1 1 Shift left

13


Figure 4.13 A small combinational circuit maps the control inputs ld, shr, and shl to the mux select inputs s1 and s0.

s1shr_in

Q3 Q2 Q1 Q0

I3 I2 I1 I0

s0ldshrshl

shl_in

I3 I2 I1 I0

Q3 Q2 Q1 Q0

shl_in

shr_in

combi-nationalcircuit

ld shr shl Operation0 0 0 Maintain present value0 0 1 Shift left0 1 0 Shift right0 1 1 Shift right -- shr has priority over shl1 0 0 Parallel load1 0 1 Parallel load -- ld has priority1 1 0 Parallel load -- ld has priority1 1 1 Parallel load -- ld has priority

14


Figure 4.14 Truth table describing operations of a register with left/right shift and parallel load along with the mapping of the register

control inputs to the internal 4x1 mux select lines (left), and a compact version of the operation table (right).

Noteld shr shl s1 s0 Operation0 0 0 0 0 Maintain value0 0 1 1 1 Shift left0 1 0 1 0 Shift right0 1 1 1 0 Shift right1 0 0 0 1 Parallel load1 0 1 0 1 Parallel load1 1 0 0 1 Parallel load1 1 1 0 1 Parallel load

OutputsInputsld shr shl Operation0 0 0 Maintain value0 0 1 Shift left0 1 X Shift right1 X X Parallel load

15


Table 4.1 Four-step process for designing a multifunction register.

Step Description

1Determine mux size

Count the number of operations (don’t forget the maintain present value operation!) and add in front of each flip-flop a mux with at least that number of inputs.

2Create mux operation

table

Create an operation table defining the desired operation for each possible value of the mux select lines.

3Connect mux

inputs

For each operation, connect the corresponding mux data input to the appropriate external input or flip-flop output (possibly passing through some logic) to achieve the desired operation.

4Map control

lines

Create a truth table that maps external control lines to the internal mux select lines, with appropriate priorities, and then design the logic to achieve that mapping

16


Example 4.6 Register with load, shift, and synchronous clear and set/

Step 1: Determine mux size

There are 5 operations -- load, shift left, synchronous clear, synchronous set, and maintain present value.

Step 2: Create operation tables2 s1 s0 Operation0 0 0 Maintain present value0 0 1 Parallel load0 1 0 Shift left0 1 1 Synchronous clear1 0 0 Synchronous set1 0 1 Maintain present value1 1 0 Maintain present value1 1 1 Maintain present value

17

Step 3: Connect mux inputs

Step 4: Map control lines

s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr


Example 4.6 Register with load, shift, and synchronous clear and set.

D

Q

Qn

s1s0

from Qn-1

6 5 4 3 2 1 07s2

01In

clr set ld shl s2 s1 s00 0 0 0 0 0 0 Maintain present value0 0 0 1 0 1 0 Shift left0 0 1 X 0 0 1 Parallel load0 1 X X 1 0 0 Set to all 1s1 X X X 0 1 1 Clear to all 0s

Inputs Outputs Operation

18


A 2-bit adder, which adds two 2-bit numbers, could be designed by starting with the following truth table.

a1 a0 b1 b0 c s1 s00 0 0 0 0 0 00 0 0 1 0 0 10 0 1 0 0 0 10 0 1 1 0 1 10 1 0 0 0 0 10 1 0 1 0 1 00 1 1 0 0 1 10 1 1 1 1 0 01 0 0 0 0 0 11 0 0 1 0 1 11 0 1 0 1 0 01 0 1 1 1 0 11 1 0 0 0 1 11 1 0 1 1 0 01 1 1 0 1 0 11 1 1 1 1 1 0

Inputs Outputs

19


Figure 4.19 Why large adders aren’t built using standard two-level combinational logic -- notice the exponential growth. How many

transistors would a 32-bit adder require?

0

2000

4000

6000

8000

10000

1 2 3 4 5 6 7 8N

Tran

sist

ors

20

0 10 11 1 1111 1111 1111 1111+0110 +0110 +0110 +0110 ---- ---- ---- ---- 1 01 101 10101


Figure 4.17 Adding two binary numbers by hand, column by column.

21


Figure 4.18 Using combinational components to add two binary numbers column by column.

1 1 1 1

0 1 1 0

1 1 0

1 0 1 0 1

+

SUM

scoscoscosco

A:

B:

b aciabciabciab

22


Half-adder Truth Table

a b

co s

a b

co s

Half-adder(HA)

a b co s0 0 0 00 1 0 11 0 0 11 1 1 0

Inputs Outputs

Figure 4.19 Half-adder circuit (left) and block symbol (right).

23


Figure 4.20 Full-adder circuit (left) and block symbol (right).

Full-adder Truth Table

a b ci co s0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Inputs Outputs

a b ci

co s

a b ci

co s

Full adder(FA)

24


Figure 4.21 4-bit adder: carry-ripple implementation with 3 full-adders and 1 half-adder (left), and block symbol (right).

a b

co s

ci a b

co s

ci a b

co s

ci a b

co s

co s3 s2 s1 s0

a3 b3 a2 b2 a1 b1 a0 b0

a3a2a1a0 b3b2b1b0

co s3s2s1s04-bit adderHAFAFAFA

25


Figure 4.22 4-bit adder: carry-ripple implementation with 4 full-adders, with a carry-in input (left), and block symbol (right).

a b

co s

ci a b

co s

ci a b

co s

ci

co s3 s2 s1 s0

a3 b3 a2 b2 a1 b1 a0 b0

a3a2a1a0 b3b2b1b0

co s3s2s1s04-bit adderFAFAFA

a b

co s

ciFA

ci

ci

26


Figure 4.23 Example of adding 0111+0001 using a 4-bit carry-ripple adder.

a b

c o s

ci a b

c o s

ci a b

c o s

ci a b

c o s

0 0 1 1 0

0 0 1 0 1 0 1 1

FAFAFAFA

Output after 4 ns (2 FA delays)

100

0 0 0

a b

c o s

ci a b

c o s

ci a b

c o s

ci a b

c o s

0 0 1 0 0

0 0 1 0 1 0 1 1

FAFAFAFA

110

0 0 1



Output after 2 ns (1 FA delay)

0111+0001

a b

co s

c i a b

co s

c i a b

co s

ci a b

co s

0 0 0 0 0

0 0 1 0 1 0 1 1

FAFAFAFA

111

0 1 1

a b

co s

ci a b

co s

ci a b

co s

ci a b

c o s

0 1 0 0 0

0 0 1 0 1 0 1 1

FAFAFAFA

11

1 1 1

1

(a)

(b)

(c)

(d)

c i

ci

c i

c i

0

0

0

0

27


Figure 4.24 8-bit carry-ripple adder built from two 4-bit carry-ripple adders (left); block symbol (right).

a3a2a1a0 b3b2b1b0

co s3s2s1s04-bit adder ci

a3a2a1a0 b3b2b1b0

co s3s2s1s04-bit adder ci

s7s6s5s4 s3s2s1s0co

a7..a0 b7..b0 ci

s7..s0co8-bit adder

28


Figure 4.25 8-bit DIP-switch-based adding calculator.The addition 2+3=5 is shown.

a7..a0 b7..b0 ci

s7..s0co8-bit carry-ripple adder

0

DIP switches

LEDs

CALC

10

29


Figure 4.26 8-bit DIP-switch-based adding calculator, using a register to block spurious LED outputs.

a7..a0 b7..b0 ci

s7..s0co8-bit adder 0

DIP switches

LEDs

CALCeld

clk8-bit register

10

30


Figure 4.27 Compensating scale: the dial outputs a number from 0 to 7 (000 to 111), which gets added to the sensed weight and then

displayed.

a7..a0 b7..b0 ci

s7..s0co8-bit adder 0

WeightAdjuster

to display

0 12

34567weight

sensor

00000

ld display register1clk

31


Figure 4.28 Combinational shifters: (a) left shifter with block symbol shown at bottom, (b) left shift or pass component, (c) left/right shift or

pass component.

i3 i2 i1 i0

q3q2q1q0

ini3 i2 i1 i0

q3 q2 q1 q0

in0 1 0 1 0 1 0 1

inLinR

i3 i2 i1 i0

q3 q2 q1 q0

sh 0 12 0 12 0 12 0 12shLshR

s0s1

<<1

(a) (b) (c)

32


Figure 4.29 Celsius to Fahrenheit converter.

C

<<18

8-bit adder10000000

8F

0

Example 4.9 Approximate Celsius to Fahrenheit converter.

We want to convert that temperature to Fahrenheit, again using 8 bits. The equation for converting is:

F = C*9/5 + 32

Let’s assume that we are not concerned about accuracy, so we’ll replace the equation by a simpler one:

F = C*2 + 32

33


Figure 4.30 Temperature averager using a right-shift-by-2 to divide by 4.

Ra Rb Rc RdT

ld

clk

>>2

+ +

+

RavgTavg

0

34


Figure 4.31 8-bit barrel shifter.

<<4x sh in 0

<<2y sh in 0

<<1z sh in 0

Q

8

8

35


Figure 4.32 Equality comparator: internal design (left), block symbol (right).

a3 b3 a2 b2 a1 b1 a0 b0

eq

a3 a2 a1 a0 b3b2 b1 b0

eq4-bit equality comparator

36


Figure 4.33 4-bit magnitude comparator: internal design using identical components in each stage (top), and block symbol (bottom).

a3

in_gtin_eqin_lt

out_gtout_eqout_lt

b3

a b

a2

in_gtin_eqin_lt

out_gtout_eqout_lt

b2

a b

a1

in_gtinA=Bin_lt

out_gtout_eqout_lt

b1

a b

a0

in_gtin_eqin_lt

out_gtout_eqout_lt

b0

a bAgtBAeqBAltB

a3 a2 a1 a0 b3 b2 b1b0AeqB

4-bi t mag ni tude co mp arato r

AgtB

AltB

IgtIeqIlt

IgtIeqIlt

010

Stage3 Stage2 Stage1 Stage0

37


Figure 4.34 The “rippling” within a magnitude comparator.

a3

in_gtin_eqin_lt

out_gtout_eqout_lt

b3

a b

a2

in_gtin_eqin_lt

out_gtout_eqout_lt

b2

a b

a1

in_gtinA=Bin_lt

out_gtout_eqout_lt

b1

a b

a0

in_gtin_eqin_lt

out_gtout_eqout_lt

b0

a bAgtBAeqBAltB

IgtIeqIlt


1 1 11 10 0 0

010

010

a3

in_gtin_eqin_lt

out_gtout_eqout_lt

b3

a b

a2

in_gtin_eqin_lt

out_gtout_eqout_lt

b2

a b

a1

in_gtinA=Bin_lt

out_gtout_eqout_lt

b1

a b

a0

in_gtin_eqin_lt

out_gtout_eqout_lt

b0

a bAgtBAeqBAltB

IgtIeqIlt


1 1 11 10 0 0

010

010

=

=

38


Figure 4.34 The “rippling” within a magnitude comparator (cont.)

a3

in_gtin_eqin_lt

out_gtout_eqout_lt

b3

a b

a2

in_gtin_eqin_lt

out_gtout_eqout_lt

b2

a b

a1

in_gtinA=Bin_lt

out_gtout_eqout_lt

b1

a b

a0

in_gtin_eqin_lt

out_gtout_eqout_lt

b0

a bAgtBAeqBAltB

IgtIeqIlt


1 1 11 10 0 0

010

100

a3

in_gtin_eqin_lt

out_gtout_eqout_lt

b3

a b

a2

in_gtin_eqin_lt

out_gtout_eqout_lt

b2

a b

a1

in_gtinA=Bin_lt

out_gtout_eqout_lt

b1

a b

a0

in_gtin_eqin_lt

out_gtout_eqout_lt

b0

a bAgtBAeqBAltB

IgtIeqIlt


1 1 11 10 0 0

010

100

>

39


Figure 4.35 A combinational component to compute the minimum of two numbers: internal design using a magnitude comparator (left), and

block symbol (right).

AeqB8-bit mag nitude co mparator

AgtB

AltB

IgtIeqIlt

010

8 8

A B

A B8-bit

s I1 I0

2x1 mux

C

A B

CMin

MIN

8 8

8

40


Figure 4.36 4-bit up-counter block symbol.

4-bit up countercntCtc

4

4-bit up-counter

cnt

Ctc

ld

+14

4-bit register

Figure 4.37 4-bit up-counter internal design.

00 1 11+0

1

0

1

1

0

00

carries:

unused

Figure 4.38 Adding 1 to a binary number

requires only 2-bits per column.

41


Figure 4.39 4-bit incrementer internal design (left) and block symbol (right).

Incr

emen

ter (

+1)

a b

co sHA

a3 a2 a1 a0 1

a b

co sHA

a b

co sHA

a b

co sHA

s3 s2 s1 s0co

a3a2a1a0+1

cos3s2s1s0

42


Figure 4.40 Sequencer for xy inputs of above-mirror display.

2-bit up countercntc0tc

mode

clk c1

x y

8-bit up-countercnttc

1

osc C(256 Hz) (unused)p

(1 Hz)

Figure 4.41 Clock divider.

43


Figure 4.42 4-bit down-counter design.

4-bit down counter

cnt

Ctc

ld

-14

4-bit register

44


Figure 4.43 4-bit up/down-counter design.

4-bit up/down-counter

cnt

Ctc

ld

-14

4-bit register

1 0

+1

clrclr

1 0

dir 2x1

2x1

45


Figure 4.44 Light sequencer.


1clk c2 c1 c0

(1 Hz)

d2 d1d0d3d4d5d6d7

unusedabc3x8 dcd

lights

46


Figure 4.45 Internal design of a 4-bit up-counter with load.

cnt

Ctc

ld

+14

4-bit register

ld 1 0L

2x1

4

47


Figure 4.46 A counter setup that pulses tc every 9 cycles.

4-bit down-countercnttc

1clk C

(unused)

ld L1000

48


Figure 4.47 Happy New Year countdown system using a down-counter.

i0i1i2i3i4

d0d1d2d3

d58d59d60d61d62d63

5958

3

12

HappyNew Year!

6x64

i5

0

dcd

rese

tco

untd

own

ld

cnt

clk(1 Hz)

8-bitdown-

ctr

L598

c0c1c2c3c4c5c6c7

tc fireworks

49


Figure 4.48 Clock divider.


1

osc C(60 Hz) p

(1 Hz)

clr

50


Figure 4.49 Measuring vehicle speeds in a highway speed measuring system.

b

a s

vehicle

SpeedMeasurer

S0

a’

a S1clr=1 cnt=1

b S2

b’

cnt=0(compute time and output speed)

clrcnt

16C

51


Multiplying two 4-bit binary numbers 0110 and 0011 by hand.

0110 (the top number is called the multiplicand)

0011 (the bottom number is called the multiplier)

---- (each row below is called a partial product)

0110 (because the rightmost bit of the multiplier is 1, and 0110*1=0110)

0110 (because the second bit of the multiplier is 1, and 0110*1=0110)

0000 (because the third bit of the multiplier is 0, and 0110*0=0000)

+0000 (because the leftmost bit of the multiplier is 0, and 0110*0=0000)

--------

00010010 (the product is the sum of all the partial products: 18, which is

6*3)

52


Figure 4.50 Internal design of a 4-bit by 4-bit array-style multiplier.

a3 a2 a1 a0

b0

b1

b2

b3

pp1

pp2

pp3

pp4

00

+ (5-bit)0

+ (6-bit)

0

000

p7..p0

+ (7-bit)A B

P* Block symbol

53


Figure 4.51 4-bit subtractor: subtraction “by hand” example (top); borrow-ripple implementation with four full-subtractors, with a borrow-

in input (bottom left), and block symbol (bottom right).

a b

wo s

wi a b

wo s

wi a b

wo s

wi

wo s3 s2 s1 s0

a3 b3 a2 b2 a1 b1 a0 b0

a3a2a1a0 b3b2b1b0

wo s3s2s1s04-bit subtractorFSFSFS

a b

wo s

wiFS

wi

wi

10

0 111 1001

1-

10

0 111 100

1-

1

1

011 10

0 111 10

1-

1

01 1

0

10

0 111 10

1-

1

0 11

00

1st column 2nd column 3rd column 4th column

54


Figure 4.52 8-bit DIP-switch-based adding/subtracting calculator, using an input f to select between addition and subtraction.

A B ci

Sco8-bit adder

0

DIP switches

LEDs

CALCeld

clk

A B wi

Swo8-bit subtractor

0

8-bit register

2x1f 0 1

10

10

55


Example 4.19 Color space converter -- RGB to CMYK.

C = 255 - RM = 255 - GY = 255 - B

Figure 4.54 RGB to CMY converter.

R

C

255G

M

255B

Y

255

RGBt

oCM

Y 8 8 8

888

56


Example 4.19 Color space converter -- RGB to CMYK.

K = Minimum(C, M, Y)C2 = C - KM2 = M - KY2 = Y - K

Figure 4.55 RGB to CMY converter.

RGBtoCMYR G B

C M Y

8

8 8 8

MIN

MIN

8

8 8R G B

8 8 8 8C2 M2 Y2 K

RG

Bto

CM

YK

57


Figure 4.56 Subtracting by adding.

123456789

987654321

0 10

-4

7

0 200 1+6

13133

7-4=3 7+6=13 -->3

4 6

3

Adding the complement results in an answer exactly 10 too much -- dropping the tens column givesthe right answer.

10

58


Figure 4.57 Two’s complement subtractor built

with an adder.

A B

AdderS

cin1

N-bitA B A B

AdderS

cin

subN-bit 2x10 1

su bb 7 b 6

. ..

adder’s B inputs

A B

Figure 4.58 Two’s complement adder/subtractor (left); alternative circuit

for B (right).

59


Figure 4.59 8-bit DIP-switch-based adding/subtracting calculator, using an adder/subtractor and two’s complement number representation.

DIP switches

LEDs

CALCeld

clk8-bit register

f 8-bit adder/subtractorA B

subS

10

10

60


Table 4.2 Desired calculator operations.

OperationSample output if A=00001111, B=00000101

x y z y0 0 0 S = A + B S=000101000 0 1 S = A - B S=000010100 1 0 S = A + 1 S=000100000 1 1 S = A S=000011111 0 0 S = A AND B (bitwise AND) S=000001011 0 1 S = A OR B (bitwise OR) S=000011111 1 0 S = A XOR B (bitwise XOR) S=000010101 1 1 S = NOT A (bitwise complement) S=11110000

Inputs

61


Figure 4.60 8-bit DIP-switch-based multi-function calculator, using separate components for each function.

DIP switches

LEDs

CALCe

ldclk

8-bit register

A B

+

8-bit 8x1

- +1 AND OR XOR NOT

xyz

0 1 2 3 4 5 6 7s2s1s0

8 8

8 8 8 8 8 8 88A lot of wires.

What awaste.

10

1 0

62


Figure 4.61 ALU design based on a single adder, with an arithmetic/logic extender.

A B

AdderIS

cinIA IB

ALU

S

AL-extender xyz

a7 b7

ia7 ib7

xyz

a6 b6

ia6 ib6

...

a0 b0

ia0 ib0

cinext

cin

abext abext abext

AL-extender

63


Figure 4.62 8-bit DIP-switch-based multi-function calculator, using an ALU.

DIP switches

LEDs

CALCe

ldclk

8-bit register

A Bxyz

8 8

ALUA B

S

xyz

10

64

C

4x16

D

load

load

d0

d15

i3-i0

i0

i15

d

load

32-bit

e

reg0

reg15

16x1

From

the

car’

sce

ntra

l com

pute

r

To the above-m

irror display

...

32

32

s3-s032

...

too muchfanout

congestion

huge mux


Figure 4.63 Above-mirror display design, assuming 16 32-bit registers.

65


Figure 4.64 16x32 register file block symbol.

W_data

W_addr

W_en

R_dataR_addr

R_en16x32

register file

32

4

32

4

66


Figure 4.65 One possible internal design of a 4x32 register file.

2x4

load

load

load

load

d0

d1

d2

d3

i0i1

e

reg0

reg1

reg2

reg3

W_data

W_addr

W_en

32d0

d1

d2

d3

2x4

e

R_en

R_data

R_addri0i1

4x32 register file

writedecoder

busdriver

32

67

CD

loadFrom

the

car’

sce

ntra

l com

pute

rTo the above-m

irror display

W_data

W_addr

W_en

R_dataR_addr

R_en16x32

register file

4

32

4

32

WA

RA

1


Figure 4.66 Above-mirror display design, using a register file.

68


Figure 4.68 Basic components of an ultrasound machine.

Transducer BeamformerDigital Signal

ProcessorScan

ConverterMonitor

69

X

focal

Transducers1

X

Transducers

12

2 X

Transducers

12

3

23

Both waves reach the focalpoint at the same time

X

Transducers

pointfocalpoint

(a) (b) (c) (d)

soundwave


Figure 4.69 Focusing sound at a particular point using beamforming: (a) first time step -- only the botton transducer generates sound(b) second time step -- the top transducer now generates sound too(c) third time step -- the two sound waves add at the focal point(d) an illustration showing that the top transducer is two time steps away

from the focal point, while the bottom transducer is three time steps away, meaning the top transducer should generate sound one time step later than the bottom transducer

70


Figure 4.70 Listening to sound from a particular point using beamforming(a) first time step (b) second time step -- the top transducer has heard the sound first(c) third time step -- the bottom transducer hears the sound at this time, (d) delaying the top transducer by one time step results in the waves from

the focal point adding, amplifying the sound.

X

Transducers

(a) (b) (c)

X X

(d)

+delay 1

time-step

focalpoint

result withoutthe delay

strongresult

71


Figure 4.71 Transducer output delay circuits for two channels.

dld

dld

DSP

Transducers

o

o

start_out

dcd

s

s

enaddr

delay_outOut

Delay

OutDelay

Figure 4.72 OutDelay circuit.

OutDelay

o dlddown

counterldL

C

tc cnt

72


Figure 4.73 Transducer output and echo delay circuits for one channel.

dld

ostart_out

s delay_outOutDelay

EchoDelay

tdelay_echo

dldtd t_delayed to

adders

N

Figure 4.74 EchoDelay circuit.

EchoDelay

dld

t

reg

4x1

reg

reg

reg

td

73


Figure 4.75 Adding many numbers: linearly (left), and using an adder tree (right); note that both methods use seven adders.

A BC DE F GH

++

++

++

+S

+ + + +

A B C D E F G H

+ +

+S

7-adderdelay

delay3-adder

74


Figure 4.76 Channel extended with a multiplier.

dld

ostart_out

s delay_outOutDelay

EchoDelay

tdldtd to

adders

N

*

dldreg-

ister

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