Digital

1. Define logic family. Classify logic family.2. Define Current Hogging, Active pull-up, passive pill-up transistor, Noise immunity and

propagation delay, fan-in, fan-out.3. Draw a 3-input RTL or gate.4. Draw the electric circuit diagram of a 1) 3-input RTL NAND gate 2)4-input RTL OR gate 3)3-input

DCTL OR gate 4)5. Write down the importance of Rb of a DTL NAND gate.6. Prove that, an RTL buffer the number of fan-out is increase by a factor of 6.7. Draw 3-input DTL NAND gate with fan-out & prove that N=.7σhfe

8. For RTL gate show that = (640 450N ).NC

9.

Gate:A gate is a decision making element that produces an output that is high or low depending on its input.Fan In:The maximum number of inputs that can be connected to a logic gate without any impairment of its normal operation is referred to as fan in. For example, if the maximum of eight input loads is connected to a logic gate without any degradation of its normal operation, then its fan-in is 8.Fan Out: Fan Out is defined as number of similar gates that a logic gate can drive. High fan out is desirable.Noise Margin:The ability of a circuit to tolerate the effect of noise is called as noise immunity. The amount by which a circuit can tolerate the effect of noise is called noise margin.

The noise margins are illustrated in Fig. 10.31. Margins shown in the figure are called dc noise margin, they are

∆1=VOH – V1H = High state noise margin ∆O=VIL – VOL = Low state noise margin

High Level Input Voltage (VIH) is defined as the minimum input voltage recognized as logic 1.Low Level Input Voltage(VIL) is defined as maximum value of input voltage recognized as logic 0.High Level Output Voltage (VOH) is defined as the minimum value of output Voltage when output is logic 1.Low Level Output Voltage (VOL) is defined as the maximum voltage that appears at output when output is logic 0.The voltage separation between the two logic states is defined as the logic swing. Input logic swing=VIH – VIL

Output Logic swing=VOH – VOL

Current hogging:The DCTL gates are simpler than RTL but suffers from a problem called current hogging. It occurs when driver output is logic 1.The input characteristics of transistor of same batch differ from each other causing variation in VBEsat. Thus if VBEsat= 0.8 V for one transistor another may have 0.798 V, some other may have 0.796 V. When driver’s output is logic 1, the transistor having lowest value of VBEsat (on the load side) will enter first into saturation and will take all the current supplied by the driver side. Thus the other transistors may not get sufficient amount of current to enter into saturation. This is called current hogging.Reason of current hogging:1. Different integrated circuit package.2. Transistor operating at different temperature.

RTL:It is Resistor-transistor logic gate. It consists of resistor and transistor. The basis RTL gate is a NOR gate.2-Input RTL NOR gate:

Logic operation:When both the inputs are high i.e., A = B = V(1), both Q1 and Q2 goes to ON state i.e., both enters into saturation. Thus the voltage at collectors is nothing but VCEsat . So output Y = VCEsat. Hence, when A = B = V(1) Y= VCEsat = 0.2 V≅ V(0) = LOWWhen both the inputs are low i.e., A = B = V(0), both Q1 and Q2 goes to OFF state. Thus no current flow through RC and drop across RC is zero. So whole +VCC will appear at output i.e. Y = +VCC = 3.6 V = HIGH. Thus when A=B = V(0)Y = +VCC = HIGHWhen only one input goes high i.e., A = V (1) and B = V(0) or when A = V(0) and B = V(1), the transistor feeded with high input conducts causing a current to flow through ON transistor. Consequently the transistor enters into saturation. Thus the output voltage becomes VCEsat. So,When A=V(1) B = V(0)Y = V CEsat = LOWA=V(0) B = V(1)Y = VCEsat = LOWFrom the above discussion it is clear that output of circuit shown in Fig. 10.36 represents a NOR gate. It is because when all the inputs are low, only then output is high otherwise the output is low.

Rise time:The Propagation Delay is affected by number of load gates. When output of driver is LOW all the load transistors are in cutoff and their base to emitter junction appears as capacitor. Since N load transistors are there, N such capacitor appears in parallel. If capacitance affered by one load transistor is Ci, then total capacitance would be CTOTAL = Ci + Ci + ... CTOTAL = NCi when driver output is LOWwhen driver output goes to high from low this capacitor (CTOTAl) must be charged to HIGHvoltage by a time constant.

= Req.CTOTAL

where Req = 640 450N

so = (640 450N

).NCi

finally = (640 N + 450) Ci

Pull-up resistors:The collector resistor Rc is called pull up resistor because it pulls the output of gate from low to high state. It is because when transistor is in LOW state the output capacitance C is discharged and for LOW to HIGH transition the output capacitance C must be charged to the Logic 1 voltage, the resistor Rc provides the charging current path. Thus the names pull up resistor. Since Rc is passive element, this is called passive pull-up.

Active pull-up/RTL buffer:The buffer is an RTL gate using an active pull-up to achieve a very low output impedance. The output current capability of a RTL buffer is significantly greater than any ordinary gate. As the output impedance is very low, more current will flow. So that it’s number of fan-out is very large. Also its rise time is less than other ordinary RTL gate.RTL Buffer:A circuit or gate that can drive a substantially a higher number of gate or load.Characteristics of RTL logic gate:

1. Poor noise margin.2. Poor fan-out capabilities3. Low-speed4. High power dissipation5. Sensitive to temperature.

Resistor Transistor Logic (RTL):Advantages:- RTL gates are almost as simple as DL gates, and remain inexpensive.- Using low power supply for each gate.- RTL integrated circuits are sometimes used as inexpensive small signal amplifiers, or as interface devices between linear and digital circuits.Limitations:- RTL gates cannot switch at the high speeds used by today's computers- These are not designed for linear operation- low noise marginRise Time of RTL and RTL buffer:The rise time of a gate is proportional to the RC time constant of the gate and load.

Fig-1 the equivalent circuit of an RTL gate driving N1 identical RTL gates.We have representedThe base-emitter junction of each transistor by a capacitor C.The time constant τ1 is

τ1=(640+450N 1

)N1C=(650 N1+450 ) C

Fig-2 is the equivalent circuit of a RTL buffer, driving N2 RTL gates, just after the input voltage Vi dropped from its 1 to 0 state. T1 and T3 are cut off and T2 is saturated.Since T2 is saturated, looking back into the emitter, we saw just the 100Ω collector resistor. Hence the time constant is

τ1≅ (100+450N2

)N2 C=(100 N2+450 ) C

If the rise time of the RTL and RTL buffer are to be the same, that is640 N1=100 N2⟹N 2=6.4 N1

∴N2=6.4 N1

DTL:Diode–Transistor Logic (DTL) is a class of digital circuits built from bipolar junction transistors (BJT), diodes and resistors; it is the direct ancestor of transistor–transistor logic. It is called diode–transistor logic because the logic gating function (e.g., AND) is performed by a diode network and the amplifying function is performed by a transistor (contrast this with RTL and TTL).

Write down the importance of Rb of a DTL NAND gate?Ans:For DTL NAND gate Rb is very importance because If transistor T2 is in saturation and if then one or more of the gate inputs returns to logic level 0, point P falls to Vp=0.2+0.75=0.95V.The equivalent circuit shown in fig-10.If this time point P drops, momentarily cutting off diodes D1 and D2, this stored charge leaves through resistor Rb.Thus, resistance Rb

provides a discharge path for the charge stored in the transistor. So Resistor Rb is connected to the -2V supply to increase the rate of discharge.

Current sink logic:DTL is called current sink-logic because when QD is in ON state there flows a current from Load stage to driver stage, and the QD acts as current sink for these load currents. When QD is in OFF

state output is HIGH and input diodes of load gates are reverse biased. Practically there flows a very small amount of current from driver to load side. This current is equal to reverse saturation current of diodes. The driver is said to be sourcing this small current to load. Since sourcing of current is very-very small compared to sinking the overall logic is called current sink logic.

Advantage of DTL:1. DTL over RTL is its better noise margin

2. Greater fan-out3. Slower speed

HTL(HIGH-THRESHOLD LOGIC):

There are several applications where the digital circuits operate in an environmentthat produces very high noise signals. For operation in such surroundings, a type of DTLgate is available that possesses a high threshold to noise immunities ∆0 and ∆1. This type of gate is called a high threshold logic or HTL gate.

The normal diode D1, as used in DTL, has been replaced by a zenner diode (Z) in HTL. The supply voltage has been changed to 15 V and the resistor values have been modified accordingly to maintain an equal current with DTL. The zenner diode has the characteristics of maintaining a constant voltage of 6.9 V when reverse biased.

In order for output transistor Q1 to conduct, the emitter of Q2 must rise to a potential ofone VBE plus fixed zenner voltage of 6.9 V, that means a total of about 7.5 V. (With a low-level input of 0.2 V, the base of Q2 is at 0.9 V and so Q1 is at cut-off. The noise signal must be higher than 7.5 V to change the state of Q1. With all inputs at high level to 15 V, sufficient voltage and current are available at the base of Q1 to drive it to saturation. On the other hand, the noise signal must be greater than 7.5 V in the opposite side to turn the transistor off. Thus the noise margin of the HTL gate is about 7.8V for both voltage levels.)HTL gates are quite useful in the industrial environment where the noise level is usuallyhigh due the presence of motors, high-voltage switches, relays, circuit breakers, etc.

Advantages of HTL:It is less temperature sensitive. Its power supply is high and overall power dissipation is high.Disadvantage of HTL:Its propagation delay time is large i.e. hundred nanosecond.

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INTEGRATED-INJECTION LOGIC (I2L):Integrated-injection logic, or IIL, or I2L, is latest generation LSI technique, also called Merged Transistor Logic (MTL), that uses both npn and pnp bipolar junction transistors to form a large number of logic gates on a single chip. It reduces the number of metal connections. This allows more circuits to be placed in a chip to form complex digital functions. It also eliminates all the resistors in the circuit, thus increasing the speed as well as reducing power dissipation.

The I2 L basic gate is similar to the RTL gate, with a few major differences. (a) The base resistor used in an RTL gate is removed altogether in the I2L gate. (b) The collector resistor used in an RTL gate is replaced by a pnp transistor that acts as a load for the I2L gate. (c) I2L transistors use multiple collectors instead of individual transistors as employed in RTL.

The schematic diagram of a basic I2L inverter gate is shown in Figure 11.36. It has a multiple collector transistor Q1 and a pnp transistor Q2 at the base of Q1. The emitter of Q2 is connected to the supply voltage VBB and its base is grounded. Q2 acts as a current source and active pull-up, and the multiple collector npn transistor Q1 operates as an inverter when one or more collectors are connected with other gates. Most of the current leaving from Q2 is injected directly to the base of Q1, and hence the emitter of Q2 is known as the injector and the integrated structure is called the integrated injection logic.