Device Microelectronic Prof. Dr. Ir. Djoko Hartanto MSc Jurusan Elektro Fakultas Teknik Universitas Indonesia Semester Genap 2003.

n-well

p-channel transistor

p-well

n-channel transistorp+ substrate

Transistor Layers

Device Device MicroelectronicMicroelectronic

Prof. Dr. Ir. Djoko Hartanto MScProf. Dr. Ir. Djoko Hartanto MSc

Jurusan Elektro Jurusan Elektro Fakultas Teknik Universitas Fakultas Teknik Universitas

IndonesiaIndonesiaSemester Genap 2003Semester Genap 2003

SAPSAP

SKSSKS : 3: 3 Staf PengajarStaf Pengajar

PJ: Prof. Dr. Ir. Djoko Hartanto MSc. (DH)PJ: Prof. Dr. Ir. Djoko Hartanto MSc. (DH) Ang: Arief Udhiarto, ST. (AU)Ang: Arief Udhiarto, ST. (AU)

Sistem KelasSistem Kelas : Tunggal: Tunggal Sistem Evaluasi (dalam %)Sistem Evaluasi (dalam %)

(20) Tugas. (20) Tugas. (30) Midtest, (30) Midtest, (30) UAS, (30) UAS, (20) Seminar(20) Seminar

Tanggal Pokok Bahasan dan Isi Bahasan Media* Tugas Dosen

1. 04-02-02 1. Pre-test2. The development of IC3. Processing Overview

Power-Point (PP)

Topics for Seminar, Design Model Device-Fab., Journals.

DH

2. 07-02-02 Thermal Oxidation of Silicon-11. Properties of matters2. Kinetics of Oxidation

PP DH

3. 11-02-02 Thermal Oxidation of Silicon-21. Oxide Thickness Charts2. Preparation of Thermal Oxide

PP Homework (HW) –1 Calculation of depth diffusion

DH

4. 14-02-02 Thin Film Deposition1. Evaporation2. Chemical Vapor Deposition

PP DH

5. 18-02-02 Lithography –1• Photomasks• Photoresists

PP Collect HW-1 DH

6. 21-02-02 Lithography-2• Resolution• Linewidth

PP DH

7. 25-02-02 Etching-11. Wet Etching2. Dry Etching

PP HW-2 Resolution / linewidth

Problems

DH

8. 28-02-02 Etching-21. Plasma Etching2. Vapor Phase Etching

PP DH

9. 04-03-02 Epitaxy1. Vapor Phase Epitaxy2. Liquid Phase Epitaxy

PP Collect HW-2 DH

10. 07-03-02 Diffusion-11.Atomic Diffusion Mechanisms2.Diffusion Characterization

DH

11. 11-03-02 Diffusion-21.Diffusion Processes2.Diffusion Equipments

PP DH

12. 14-03-02 Diffusion-31.Diffusion Sources2.The Error Function

PP DH

13. 18-03-02 Diffusion Profile PP DH

14. 21-03-02 Ion Implantation PP AU

15. 25-04-02 •Ohmic Contact •Schottky Barriers

PP AU

16. 28-04-02 Interconnect PP DH

17. 01-04-02 MAGIC-1 PP AU

18. 04-04-02 MAGIC-2 PP AU

19. Lihat Jadwal Midtest

Midtest DH, AU

20. 15-04-02 Laboratory visit AU

21. 22-04-02 SPICES-1 AU

22. 25-04-02 SPICES-2 PP AU

23. 29-04-02 SUPREM-1 PP AU

24. 02-05-02 SUPREM-2 PP AU

25. 06-05-02 Seminar-1 PP AU

25. 09-05-02 Seminar-2 PP AU

26. 13-05-02 Seminar-3 PP AU

27. 20-05-02 Seminar-4 PP AU

28. 23-05-02 Seminar-5 PP AU

29. Lihat Jadwal Ujian Akhir

Final Test DH,AU

Pre-TestPre-Test

1.1. Sebutkan empat tahap utama dalam Sebutkan empat tahap utama dalam proses proses microchip fabricationmicrochip fabrication ! !

2.2. Apa yang dimaksud dengan Apa yang dimaksud dengan photolithographyphotolithography??

3.3. Apa fungsi Apa fungsi packagingpackaging dalam proses dalam proses pabrikasi?pabrikasi?

Terms and Concepts to be Terms and Concepts to be Covered in this LessonCovered in this Lesson

• siliconsilicon• substratesubstrate• monocrystallinemonocrystalline• polycrystallinepolycrystalline• epitaxial silicon epitaxial silicon

growthgrowth• polysiliconpolysilicon• silicon dioxide silicon dioxide • oxideoxide

• silicon nitridesilicon nitride• metalmetal• dopantdopant• dopingdoping• concentrationconcentration• diffusiondiffusion• field effect field effect

transistortransistor• source, drain, gatesource, drain, gate

Terms and Concepts to be Terms and Concepts to be Covered in this LessonCovered in this Lesson

• MOSMOS• NMOS technologyNMOS technology• n-channeln-channel• PMOS technologyPMOS technology• p-channelp-channel• CMOS technologyCMOS technology• p-wellp-well• n-welln-well• photoresistphotoresist• photomaskphotomask

• exposureexposure• diffusiondiffusion• thin filmsthin films• photolithographyphotolithography• etchetch• ion implantion implant• polish, CMPpolish, CMP• planarizationplanarization• strips and cleansstrips and cleans• test and sorttest and sort

Variations in Dopant Variations in Dopant ConcentrationsConcentrations

Concentration P-type N-type

lightly doped p- n-

very lightly doped p-- n--

heavily doped p+ n+

very heavily doped p++ n++

Processing OverviewProcessing Overview

Tahap-tahap pabrikasi chip ICTahap-tahap pabrikasi chip IC

1.1. Material PreparationMaterial PreparationConvert silicon dioxside to semiconductor-grade Convert silicon dioxside to semiconductor-grade

siliconsilicon

2.2. Crystal Growth and Wafer Preparation Crystal Growth and Wafer Preparation Convert polysilicon to silicon waferConvert polysilicon to silicon wafer

Crystal growingCrystal growing Slice cutting and polishingSlice cutting and polishing Photomask manufacturingPhotomask manufacturing

Procesing OverviewProcesing Overview

3.3. Wafer FabricationWafer Fabricationa.a. Cleaning of surfacesCleaning of surfaces

b.b. Growth of epitaxial layerGrowth of epitaxial layer

c.c. Thermal oxidation of siliconThermal oxidation of silicon

d.d. Patterning of the various layers Patterning of the various layers (lithography)(lithography)

e.e. Diffusion of impurities into siliconDiffusion of impurities into silicon

f.f. Ion implantation of impuritiesIon implantation of impurities

1212

Wafer FabricationWafer Fabrication

g.g. Chemical vapor deposition of polycristalline siliconChemical vapor deposition of polycristalline silicon

h.h. Etching of silicon and GaAsEtching of silicon and GaAs

i.i. Deposition of insulating layers (silicon oxide or Deposition of insulating layers (silicon oxide or nitride)nitride)

j.j. Etching of insulating layers (silicon oxide or Etching of insulating layers (silicon oxide or nitride)nitride)

k.k. Depositon of conductive layers (metal, polysilicon, Depositon of conductive layers (metal, polysilicon, other)other)

l.l. Alloying (sintering) to form metal-silicon electrical Alloying (sintering) to form metal-silicon electrical contactcontact

Wafer FabricationWafer Fabrication

m.m. Backgrinding (thinning of wafer by Backgrinding (thinning of wafer by grinding)grinding)

n.n. Multiprobing (DC electrical testing of each Multiprobing (DC electrical testing of each IC on wafer)IC on wafer)

4. Packaging4. Packaging

a.a. Cutting or breaking of wafers into individual Cutting or breaking of wafers into individual chipschips

b.b. Packaging of individual chipsPackaging of individual chips

c.c. Full AC dan DC electrical testing of Full AC dan DC electrical testing of packaged ICspackaged ICs

Fabrication process of a simple metal oxide semiconductor (MOS) transistor

silicon substrate

source draingategateoxideoxide oxideoxide

top nitride

metal connection to source

metal connection to gate

metal connection to drain

polysilicon gatedoped silicon

field oxide

gate oxide

The manufacture of a single MOS transistor begins with a silicon substrate.

silicon substrate

A layer of silicon dioxide (field oxide) provides isolation between devices manufactured on the same substrate.

silicon substrate

oxideoxide

field oxide

Photoresist provides the means for transferring the image of a mask onto the top surface of the wafer.

silicon substrate

oxideoxidephotoresistphotoresist

Shadow on photoresist

photoresistphotoresist

Exposed area of photoresist

Chrome platedglass mask

Ultraviolet Light

silicon substrate

oxideoxide

Ultraviolet light exposes photoresist through windows in a photomask.




Chrome platedglass mask

Ultraviolet Light

silicon substrate

oxideoxide

Ultraviolet light exposes photoresist through windows in a photomask.

Exposed photoresist becomes soluble and can be easily removed by the develop chemical.

Unexposed area of photoresist

silicon substrate


oxideoxidephotoresistphotoresist

Unexposed photoresist remains on surface of oxide to serve as a temporary protective mask for areas of the oxide that are not to be etched.


silicon substrate

oxideoxide

photoresistphotoresistphotoresist

Areas of oxide protected by photoresist remain on the silicon substrate while exposed oxide is removed by the etching process.

silicon substrate

oxideoxide oxideoxide

silicon substrate


The photoresist is stripped off -- revealing the pattern of the field oxide.

silicon substrate


silicon substrate

field oxide

A thin layer of oxide is grown on the silicon and will later serve as the gate oxide insulator for the transistor being constructed.

silicon substrate


gate oxidegate oxide

thin oxide layer

The gate insulator area is defined by patterning the gate oxide with a masking and etching process.

silicon substrate


gate oxide

Polysilicon is deposited and will serve as the building material for the gate of the transistor.

silicon substrate


gate oxide

polysiliconpolysilicongate oxide

The shape of the gate is defined by a masking and etching step.

silicon substrate

oxideoxide oxideoxidegategategate

ultra-thin gate oxide

polysilicongate

Dopant ions are selectively implanted through windows in the photoresist mask.

silicon substrate



Scanning direction of ion beam

implanted ions in active region of transistors

Implanted ions in photoresist to be removed during resist strip.

source drain

ion beam

The source and drain regions of the transistor are made conductive by implanting dopant atoms into selected areas of the substrate.

silicon substrate


source drain

doped silicon

A layer of silicon nitride is deposited on top of the completed transistor to protect it from the environment.

silicon substrate

source draingategate

top nitridetop nitride

Holes are etched into selected parts of the top nitride where

metal contacts will be formed.

silicon substrate

source draingategate

contact holes

Metal is deposited and selectively etched to provide electrical contacts to the three active parts of the transistor.

silicon substrate


metal contacts

Completed structure of a simple MOS transistor

silicon substrate


top nitride

metal connection to source

metal connection to gate

metal connection to drain

polysilicon gatedoped silicon

field oxide

gate oxide

Test/Sort

Thin Films

Photo

Implant

Diffusion Etch

Polish

Manufacturing Areas in Wafer Fab

Wafer Fabrication (front-end)

Bare silicon wafer

Completed product

Common Terms in Wafer Fab

• Diffusion– high temperature processes– atmospheric - low vacuum pressures– oxidation, anneal, alloy, deposition, diffusion

• Photolithography– patterning process (masking)– photoresist coating– exposure to UV light– develop


• Etch– selective removal of specific materials– permanent patterning of wafer– low vacuum - high vacuum pressure– RF power, plasma etching

• Ion Implant– selective doping of specific areas of wafer– through windows in photoresist or oxide– high voltage, high vacuum, ion acceleration


• Thin Films– moderate temperatures– low vacuum - high vacuum pressures– dielectric films, metals, anneal

• Polish– chemical mechanical polish (CMP)– planarization of wafer surface


• Strips & Cleans– dry, plasma resist strip– wet, chemical cleans using acid solutions and

solvents

• Test/Sort– automated testing of each die on wafer– discriminate good from bad– determines a fab’s yield– ship to assembly & packaging

Typical Wafer Flow in CMOS Fab

Thin Films

Photo

Implant

Diffusion Etch

Test/Sort

Polish

CMOS Inverter Technology

Schematic Diagram

Top view of Transistor

Cross-section of Transistor

VDDVSS

Vout

Vin

s d s d

g g

VDDVSS

Vout

Vin

g gs d s d

n-channel transistor

p-channel transistor

p-well

n+p+ n+p+

n-substrate

source drainsourcedrain

field oxide

gate oxide

metalpolysilicon gate contact

Device Microelectronic Prof. Dr. Ir. Djoko Hartanto MSc Jurusan Elektro Fakultas Teknik Universitas Indonesia Semester Genap 2003.

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