Design of Modulo 2n to 1 Adder

DESIGN AND IMPLEMENTATION OF MODULO 2n + 1 ADDER

BY USING PREFIX ADDER

• Half adder.

• Full adder.

• RCA.

• CLA.

Adders Introduction:

FULL ADDER

Ripple Carry Adder

Carry Look Ahead Adder

Carry propagation and generation logic for CLA.

Carry Look Ahead Adder

Set of equations required to implement carry look ahead

adder.

a = an – 1 an-2 …. A0

b = bn – 1 bn-2 …. b0

S = Sn – 1 Sn-2 …. S0

The preprocessing stage computes◦ Carry Generate Gi = Ai . Bi

◦ Carry Propagate Pi = Ai + Bi

◦ Half Sum bits Hi = Ai XOR Bi

PARALLEL PREFIX ADDER

CARRY PROPAGATE

THE DOT ( ) OPERATOR

ADDITION RESULT

Pre-processing stage stage

Computation Unit

unitPrefix networkComputation unitSum bitPrefix network

8-bit 8-bit parallel-prefix structures for integer adders kogge-stone

parallel-prefix structures for integer adders kogge-stone

8-bit parallel-prefix structures for integer adders Ladner-Fischer

DESIGN OF MODULO 2n + 1 ADDER

In the design of modulo 2n + 1 adder, 3 representations are considered

1. the normal weighted one2. the diminished-13. the signed-LSB representations

MODULO 2n ± 1 ADDITION

(A + B), A + B < 2n,

(A + B + 1) mod 2n, A + B ≥ 2n.

Modulo 2n – 1 Adder

The computation condition for this operators is defined as

(A + B) mod (2n – 1) =

SPARSE-4 PARALLEL-PREFIX STRUCTURE FOR A 32-BIT INTEGER ADDER

LOGIC LEVEL IMPLEMENTATION OF THE CS BLOCK

PARALLEL PREFIX MODULO 28 - 1 ADDERS using an additional carry-increment stage

PARALLEL PREFIX MODULO 28 + 1 ADDERS using an additional carry-increment stage

GRAY PREFIX OPERATOR; NOTATION & IMPLEMENTATION

PROPOSED SPARSE-4 MODULO 216 + 1 DIMINISHED-1 ADDER

An arithmetic example of the new approach for the computation of the modulo 2n + 1 sum via the result of the corresponding modulo 2n – 1 addition

RNS application Network security DSP filter application

APPLICATIONS

Efficient modulo 2n+1 adders appreciated in a variety of computers application including all RNS implementations

CONCLUSION

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