Ripple Carry Adder and Bcd Adder Results

8/10/2019 Ripple Carry Adder and Bcd Adder Results

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RIPPLE CARRY ADDER :4 BIT

DELAY:

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 13.521ns

AREA:

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 8 1,536 1%

Number of occupied Slices 6 768 1%

Number of Slices containing only related

logic

6 6 100%

Number of Slices containing unrelated logic 0 6 0%

Total Number of 4 input LUTs 8 1,536 1%

Number of bondedIOBs 14 124 11%

Average Fanout of Non-Clock Nets 1.71

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RCA 8BIT

AREA :

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 16 1,536 1%

Number of occupied Slices 12 768 1%

Number of Slices containing only related logic 12 12 100%

Number of Slices containing unrelated logic 0 12 0%

Total Number of 4 input LUTs 16 1,536 1%

Number of bondedIOBs 26 124 20%

Average Fanout of Non-Clock Nets 1.73

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DELAY :

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 19.776ns

POWER :

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RCA 16 :

Timing Summary:--------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 31.744ns

AREA :

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POWER :

RCA 32

AREA :

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 64 1,536 4%

Number of occupied Slices 48 768 6%

Number of Slices containing only related logic 48 48 100%

Number of Slices containing unrelated logic 0 48 0%

Total Number of 4 input LUTs 64 1,536 4%

Number of bondedIOBs 98 124 79%

Average Fanout of Non-Clock Nets 1.74

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TIMMING

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 55.680ns

POWER :

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RCA 64 :

AREA

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 128 66,560 1%

Number of occupied Slices 96 33,280 1%

Number of Slices containing only related

logic96 96 100%

Number of Slices containing unrelated logic 0 96 0%

Total Number of 4 input LUTs 128 66,560 1%

Number of bondedIOBs 194 633 30%

Average Fanout of Non-Clock Nets 1.75

POWER

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TIMING

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 103.552ns

RCA 128 :

AREA

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 256 66,560 1%

Number of occupied Slices 192 33,280 1%

Number of Slices containing only related logic 192 192 100%

Number of Slices containing unrelated logic 0 192 0%

Total Number of 4 input LUTs 256 66,560 1%

Number of bondedIOBs 386 633 60%

Average Fanout of Non-Clock Nets 1.75

Timing Summary:

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 199.296ns

8/10/2019 Ripple Carry Adder and Bcd Adder Results

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POWER

8/10/2019 Ripple Carry Adder and Bcd Adder Results

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BCD 4 BIT

Area

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 17 66,560 1%

Number of occupied Slices 9 33,280 1%

Number of Slices containing only related

logic9 9 100%

Number of Slices containing unrelated logic 0 9 0%

Total Number of 4 input LUTs 17 66,560 1%

Number of bondedIOBs 13 633 2%

Average Fanout of Non-Clock Nets 2.91

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Power

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 15.729ns

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Bcd 8

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 25.678ns

Area

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 34 66,560 1%

Number of occupied Slices 19 33,280 1%

Number of Slices containing only relatedlogic

19 19 100%

Number of Slices containing unrelated logic 0 19 0%

Total Number of 4 input LUTs 34 66,560 1%

Number of bondedIOBs 26 633 4%

Average Fanout of Non-Clock Nets 2.74

BCD 16 :

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

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Maximum output required time after clock: No path found

Maximum combinational path delay: 44.001ns

Area

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 68 66,560 1%

Number of occupied Slices 37 33,280 1%

Number of Slices containing only related

logic37 37 100%

Number of Slices containing unrelated logic 0 37 0%

Total Number of 4 input LUTs 68 66,560 1%

Number of bondedIOBs 50 633 7%

Average Fanout of Non-Clock Nets 2.83

Bcd32

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 68 66,560 1%

Number of occupied Slices 37 33,280 1%

Number of Slices containing only relatedlogic

37 37 100%

Number of Slices containing unrelated logic 0 37 0%

Total Number of 4 input LUTs 68 66,560 1%

Number of bondedIOBs 50 633 7%

Average Fanout of Non-Clock Nets 2.83

Timing Summary:

---------------

Speed Grade: -4

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Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 44.001ns

Rca 64

Area

Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 268 66,560 1%Number of occupied Slices 146 33,280 1%

Number of Slices containing only related

logic146 146 100%

Number of Slices containing unrelated logic 0 146 0%

Total Number of 4 input LUTs 268 66,560 1%

Number of bondedIOBs 192 633 30%

Average Fanout of Non-Clock Nets 2.74

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 154.147ns

Rca 128

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Device Utilization Summary [-]

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs 503 66,560 1%

Number of occupied Slices 272 33,280 1%

Number of Slices containing only related

logic272 272 100%

Number of Slices containing unrelated logic 0 272 0%

Total Number of 4 input LUTs 503 66,560 1%

Number of bondedIOBs 369 633 58%

Average Fanout of Non-Clock Nets 2.72

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 149.917ns