Design of a Cache Controller using Simple FIFO Algorithm Tirthajyoti Sarkar Shubhrangshu Mallick Chaithanya Dharmavaram Swaroop Patel Adil Ahmed Presented By: Overview Architectural Overview of the Cache Memory and Logic flow diagram The Design Pathway: How do we actually translate the ‘logic’ into hardware? Specification and Components The ‘real stuff’: Schematics and Layouts of various components on Cadence Overall System at a glance and Conclusion
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Design of a Cache Controllerusing Simple FIFO Algorithm
Tirthajyoti Sarkar
Shubhrangshu Mallick
Chaithanya Dharmavaram
Swaroop Patel
Adil Ahmed
Presented By:
Overview
Architectural Overview of the Cache Memory and Logic flow diagram
The Design Pathway: How do we actually translate the ‘logic’ into hardware?
Specification and Components
The ‘real stuff’: Schematics and Layouts of various components on Cadence
Overall System at a glance and Conclusion
Memory Hierarchy
• Decreasing cost per bit.
• Increasing capacity.
• Increasing access time.
• Decreasing frequency of access of the memory by the processor
Inboard Memory
Cache
Registers
Main
Memory
Outboard Memory
Magnetic Disk
CD-ROM/ R-W
DVD-RAM/ R/ RW
Off-line Storage Magnetic
Tape
WORM
Inboard Memory
Cache
Registers
Main
Memory
Outboard Memory
Magnetic Disk
CD-ROM/ R-W
DVD-RAM/ R/ RW
Off-line Storage Magnetic
Tape
WORM
Principles of Cache Memory
CPU CacheMain
Memory
Word Transfer Block Transfer
Processor attempts to read a word from memory.
First, cache is checked to see if the word is there.
If so – the word is delivered to the CPU.
If not – a block of words from main memory containing the needed word, is retrieved from main memory and placed into the cache. The word is then read from cache.
Simple Overview of the Cache Operation
ADDRESSINDEX DATA
INPUT ADDRESS CACHE LOGIC CONTROLLER
MEMORY READ SIGNAL
OUTPUT ADRESS BUFFER
INP
UT
AD
DR
ES
S
MAIN MEMORY CHIP
OUTPUT DATA BUFFER
CONTROLS
(MISS)
(HIT)
ADDRESSINDEX DATA
INPUT ADDRESS CACHE LOGIC CONTROLLER
MEMORY READ SIGNAL
OUTPUT ADRESS BUFFER
INP
UT
AD
DR
ES
S
MAIN MEMORY CHIP
OUTPUT DATA BUFFER
CONTROLS
(MISS)
(HIT)
• Core idea is Mapping i.e. mapping the relatively slow but large main memory onto a fast but limited secondary memory.
• Works on the Principle of Locality
• Main memory ‘off-chip’ but Cache is generally ‘on-chip’.
• Two main parts –Cache storage and Cache Controller
Logic Flow-Chart for Our Circuit
INPUT ADDRESS
COMPARISON WITH THE ADDRESSES OF THE STORED DATA
IN THE CACHE
I/P ADDRESS = STORED ADDRESS (i)?
NOFOR i=0; i < 16, i ++
SEEK THE DATA FROM CACHESTORAGE (i) AND PLACE IT ON
DATA BUS
YES (HIT)
i = 16(MISS)
1. GENERATE MEMORY READ SIGNAL
2. READ THE DATA FROM THE MEMORY AND UPDATE THE CACHE STORAGE WITHTHIS DATA FOLLOWING THE REPLACEMENT ALGORITHM.
INPUT ADDRESS
COMPARISON WITH THE ADDRESSES OF THE STORED DATA
IN THE CACHE
I/P ADDRESS = STORED ADDRESS (i)?
NOFOR i=0; i < 16, i ++
SEEK THE DATA FROM CACHESTORAGE (i) AND PLACE IT ON
DATA BUS
YES (HIT)
i = 16(MISS)
1. GENERATE MEMORY READ SIGNAL
2. READ THE DATA FROM THE MEMORY AND UPDATE THE CACHE STORAGE WITHTHIS DATA FOLLOWING THE REPLACEMENT ALGORITHM.
Comparator & Demux Function
HIGH IF INPUTS MATCH, OTHERWISE LOW.
COMPARATOR
CPU
CACHE INTERNAL STORAGE
OUTPUT
DEMUX BUSSWITCH
UP-COUNTER (i = 0 TO 15)
REQUESTED ADDRESS
ADDRESSES OF INTERNALLY STORED DATA
HIGH IF INPUTS MATCH, OTHERWISE LOW.
COMPARATOR
CPU
CACHE INTERNAL STORAGE
OUTPUT
DEMUX BUSSWITCH
UP-COUNTER (i = 0 TO 15)
REQUESTED ADDRESS
ADDRESSES OF INTERNALLY STORED DATA
Hit-Miss Decision Diagram
PLACING THE DATA ON THE BUS
COMPARATOROUTPUT
IF HIGH (HIT)
MEMORY READ
CACHE INTERNAL STORAGE
SYSTEM DATA BUS
OUTPUT ADDRESSBUFFER
BUFFER ENABLE
MAIN MEMORY ENABLE SIGNAL
IF LOW AFTER i = 16
(MISS)
UP-COUNTER (i = 0 TO 15)
READ INDEX
PLACING THE DATA ON THE BUS
COMPARATOROUTPUT
IF HIGH (HIT)
MEMORY READ
CACHE INTERNAL STORAGE
SYSTEM DATA BUS
OUTPUT ADDRESSBUFFER
BUFFER ENABLE
MAIN MEMORY ENABLE SIGNAL
IF LOW AFTER i = 16
(MISS)
UP-COUNTER (i = 0 TO 15)
READ INDEX
COMPARATOROUTPUT
IF HIGH (HIT)
MEMORY READ
CACHE INTERNAL STORAGE
SYSTEM DATA BUS
OUTPUT ADDRESSBUFFER
BUFFER ENABLE
MAIN MEMORY ENABLE SIGNAL
IF LOW AFTER i = 16
(MISS)
UP-COUNTER (i = 0 TO 15)
READ INDEX
Overall System Logic-Diagram
Demux Logic
Input Buses
Output Bus
Comparator4-bit up-counter
RESET
AND
‘Miss’ condition Memory
Read Signal
2-bit counter/Incrementor
Trigger
8-bit Full Adder O/P Buffer
Delay
Address Buffer
Trigger
Cache Read Index
Cache Read Signal
Cache Write Signal
Demux Logic
Input Buses
Output Bus
Comparator4-bit up-counter
RESET
AND
‘Miss’ condition Memory
Read Signal
2-bit counter/Incrementor
Trigger
8-bit Full Adder O/P Buffer
Delay
Address Buffer
Trigger
Cache Read Index
Cache Read Signal
Cache Write Signal
CPU Requested Address
List of Systems/ Components to be Built
8-bit 2-word Comparator.
4-bit up-counter with asynchronous RESET.
8 bit × 16 word Demultiplexer Bus
8-bit Full-Adder
The starting point is our Lab 1: 2-input NAND and Inverter!
So a few examples of the complex gates that were built…2-input X-OR, NOR and X-NOR
3- and 4-input NAND
9-input NAND
4-input and 5-input AND
J-K Flip-Flop with asynchronous SET and RESET
8-bit wide bus switch
Chip Specifications and Symbol
8-bit wide address input (Request from CPU)
16-word wide 8-bit sized on-board cache storage
Cache-Read output signal - in the case of ‘Hit’
Cache-Write/ Memory-Read signal – in the case of ‘Miss’
Power and Ground pins
System Clock input
The design of the chip has been done following the specification, listed below…
Logic Diagrams of Some Components
Comparator Logic Diagram 8-input NAND Gate Logic Diagram
X-NOR Gate Logic Diagram
More Components…
Demultiplexer Bus Switch for 8 bit by 8 words
More Components…
Q
NOT-Q
Q
NOT-Q
J-K Flip-Flop (With Asynchronous SET and RESET) Logic Diagram
2-input AND Schematic & Layout
2-input NOR Schematic & Layout
3-input NAND Schematic & Layout
5-input AND Schematic & Layout
8-input NAND Schematic & Layout
Single-bit Full-Adder Schematic
Single-bit Full-Adder Layout
Bus Switch and Serial Adder Schematic
8-bit Serial Adder Bus Switch for Demux
X-NOR Schematic & Layout
J-K Flip-Flop Schematic
J-K Flip-Flop Layout
4-bit Up-Counter Schematic
8-bit 2-word Comparator Schematic
8-bit 2-word Comparator Layout
Full System Schematic
Related Documents
