Design For Testability Design For Testability - Organization Organization Overview of DFT Techniques Overview of DFT Techniques Ad Ad-hoc techniques hoc techniques Examples Examples I/O Pins I/O Pins Scan Techniques Scan Techniques Full & Partial Scan Full & Partial Scan C. Stroud 9/09 Design for Testability 1 Full & Partial Scan Full & Partial Scan Multiple Scan Chains Multiple Scan Chains Boundary Scan Boundary Scan Built Built-In Self In Self-Test Test Evaluation Criteria for DFT Techniques Evaluation Criteria for DFT Techniques
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Design For Testability Design For Testability -- OrganizationOrganization
�� Overview of DFT TechniquesOverview of DFT Techniques
�� AdAd--hoc techniqueshoc techniques
��ExamplesExamples
��I/O PinsI/O Pins
�� Scan TechniquesScan Techniques
��Full & Partial ScanFull & Partial Scan
C. Stroud 9/09 Design for Testability 1
��Full & Partial ScanFull & Partial Scan
��Multiple Scan ChainsMultiple Scan Chains
�� Boundary ScanBoundary Scan
�� BuiltBuilt--In SelfIn Self--TestTest
�� Evaluation Criteria for DFT TechniquesEvaluation Criteria for DFT Techniques
Overview of DFT TechniquesOverview of DFT Techniques
�� AdAd--hoc techniqueshoc techniques��Target “difficultTarget “difficult--toto--test” test” subcircutssubcircuts to improve to improve
�� Add gates to provide control to internal circuitryAdd gates to provide control to internal circuitry
��Controllability onlyControllability only
�� Add these “test points” only where needed in circuitAdd these “test points” only where needed in circuit
��Low area overhead penaltyLow area overhead penalty
C. Stroud 9/09 Design for Testability 3
��Low area overhead penaltyLow area overhead penalty
��Little (if any) performance impactLittle (if any) performance impact��Critical paths can often be avoidedCritical paths can often be avoided
��Target difficult to test Target difficult to test subcircuitssubcircuits��Potential for significant increase in fault coveragePotential for significant increase in fault coverage
�� Creative testability solutions on a caseCreative testability solutions on a case--byby--case basiscase basis
��But we have to figure out what & where those areBut we have to figure out what & where those are
AdAd--Hoc DFT Techniques: Some BenefitsHoc DFT Techniques: Some Benefits
�� Provide test points for controllability & Provide test points for controllability & observabilityobservability
�� Provide easier initializationProvide easier initialization
��For logic simulation and design verificationFor logic simulation and design verification
�� Partition the logic into easier to test piecesPartition the logic into easier to test pieces
��Provide access to embedded blocksProvide access to embedded blocks
��Core tests can be reCore tests can be re--usedused
C. Stroud 9/09 Design for Testability 4
��Core tests can be reCore tests can be re--usedused
Partitioning into easy to test Partitioning into easy to test subcircuitssubcircuits using MUXsusing MUXs�� Each Each subcircuitsubcircuit can be tested independentlycan be tested independently
��this may require many MUXsthis may require many MUXs�� Example of partitioning pipelined structure Example of partitioning pipelined structure (works for (works for
almost any almost any cktckt))��T1=0, T2=1 T1=0, T2=1 ⇒⇒ normal system mode of operationnormal system mode of operation��T1=0, T2=0 T1=0, T2=0 ⇒⇒ testing testing cktckt AA��T1=1, T2=0 T1=1, T2=0 ⇒⇒ testing testing cktcktBB AA BB CCA B C
��Relatively low area overhead and performance impactRelatively low area overhead and performance impact��1 MUX (or gate) per test point1 MUX (or gate) per test point
��Critical paths can often be avoided Critical paths can often be avoided
��Moderate to good improvements in testabilityModerate to good improvements in testability
��Does not constrain the designDoes not constrain the design
��Can be used with other DFT techniques like BISTCan be used with other DFT techniques like BIST
C. Stroud 9/09 Design for Testability 10
��Can be used with other DFT techniques like BISTCan be used with other DFT techniques like BIST
��Limited CAD support (if any) availableLimited CAD support (if any) available
��I/O pin overhead can be high in some casesI/O pin overhead can be high in some cases
��Fault simulation required to evaluate effectivenessFault simulation required to evaluate effectiveness
��Considerable test development effort requiredConsiderable test development effort required
Scan Design Techniques: Basic IdeaScan Design Techniques: Basic Idea
�� Transform FFs in sequential logic into shift registerTransform FFs in sequential logic into shift register
��All FFs controllable & observable via serial accessAll FFs controllable & observable via serial access�� Many different types of scan FF (too many!)Many different types of scan FF (too many!)
��Test problem simplified to testing combinational logicTest problem simplified to testing combinational logic�� The best overall DFT approach ever developedThe best overall DFT approach ever developed
�� Fully automated DFT processFully automated DFT process��WellWell--supported by CAD vendorssupported by CAD vendors��Sequential circuits become combinational in test modeSequential circuits become combinational in test mode
�� ATPG CAD tools for generating test vectorsATPG CAD tools for generating test vectors��Typically no fault simulation requiredTypically no fault simulation required
�� ATPG can identify redundant logicATPG can identify redundant logic��Helps minimize designHelps minimize design
��Reduced timeReduced time--toto--marketmarket
C. Stroud 9/09 Design for Testability 14
��Reduced timeReduced time--toto--marketmarket�� High fault coverageHigh fault coverage
��Near 100% for gate level stuckNear 100% for gate level stuck--at and bridging faultsat and bridging faults�� Can be applied hierarchicallyCan be applied hierarchically
��chips chips ⇒⇒ boards boards ⇒⇒ systemsystem�� Allows simplified & accurate fault/defect diagnosis & FMAAllows simplified & accurate fault/defect diagnosis & FMA�� Highly structured & provides good basis for BISTHighly structured & provides good basis for BIST
��Pins: 3 ( Pins: 3 ( Scan Data In, Scan Data Out, Scan ModeScan Data In, Scan Data Out, Scan Mode))�� Scan Data InScan Data In can be shared with primary inputcan be shared with primary input
�� Scan Data OutScan Data Out can be shared with primary outputcan be shared with primary output
��Area Overhead: 1 MUX per flipArea Overhead: 1 MUX per flip--flopflop��Typically 2Typically 2--10% total area overhead penalty10% total area overhead penalty
��Performance degradation: added delay through MUXPerformance degradation: added delay through MUX
C. Stroud 9/09 Design for Testability 15
��Performance degradation: added delay through MUXPerformance degradation: added delay through MUX
��Routing overhead: scan chain connections, Routing overhead: scan chain connections, Scan ModeScan Mode�� Long test application time:Long test application time:
��# clock cycles # clock cycles == #vectors #vectors ×× (#FFs + 1) + #FFs(#FFs + 1) + #FFs��Lots of vectors & output responses to storeLots of vectors & output responses to store
�� Logic must be synchronousLogic must be synchronous
�� Difficult to test at system clock speed Difficult to test at system clock speed
Variations on Scan Design TechniquesVariations on Scan Design Techniques
�� Multiple scan chainsMultiple scan chains
��Fewer clock cycles to scan vectors in/outFewer clock cycles to scan vectors in/out
��Reduces test time if scan chains are balancedReduces test time if scan chains are balanced�� MM times faster for times faster for MM equal length scan chainsequal length scan chains
��Good for multiple clock (or clockGood for multiple clock (or clock--edge) circuitsedge) circuits
��Additional pins for Scan Data In/Out for each chainAdditional pins for Scan Data In/Out for each chain
C. Stroud 9/09 Design for Testability 16
��Additional pins for Scan Data In/Out for each chainAdditional pins for Scan Data In/Out for each chain�� Scan Data In can come from PIsScan Data In can come from PIs
�� Scan Data Out can use POs if output FF is last in scan chainScan Data Out can use POs if output FF is last in scan chain
�� Partial Scan Design replaces only selected FFs in devicePartial Scan Design replaces only selected FFs in device��Full scan replaces all FFs in device with scan FFsFull scan replaces all FFs in device with scan FFs
��Lower area & performance penalty than full scanLower area & performance penalty than full scan��But usually lower fault coverage as wellBut usually lower fault coverage as well
Lower area & performance penalty comes with price:Lower area & performance penalty comes with price:
�� What FFs should be replace and how manyWhat FFs should be replace and how many
��TradeTrade--off between fault coverage and area overheadoff between fault coverage and area overhead
��FF replacement selection methodsFF replacement selection methods�� Structural:Structural: select FFs to cut loopsselect FFs to cut loops�� ATPGATPG--based:based: select FFs useful during ATPGselect FFs useful during ATPG
C. Stroud 9/09 Design for Testability 17
�� TestabilityTestability--based:based: select FFs to maximize testabilityselect FFs to maximize testability
�� CAD tool support more limited than for full scanCAD tool support more limited than for full scan
�� Fault simulation typically required for partial scanFault simulation typically required for partial scan
��Not required for full scan since done by ATPGNot required for full scan since done by ATPG
�� Significantly more complex diagnosisSignificantly more complex diagnosis
�� Still difficult test at system clock speedStill difficult test at system clock speed
Full Scan Full Scan -- Partial Scan Comparison ExamplePartial Scan Comparison Example
Comparison study data from Comparison study data from Jet Propulsion LaboratoryJet Propulsion Laboratory
�� Viterbi Butterfly Decoder used for comparisonViterbi Butterfly Decoder used for comparison
��Fewer FFs replaced with partial scanFewer FFs replaced with partial scan
��Lower area overhead with partial scanLower area overhead with partial scan
��More vectors but fewer clock cycles with partial scanMore vectors but fewer clock cycles with partial scan
C. Stroud 9/09 Design for Testability 18
Number of Scan FFsNumber of Scan FFsLogic OverheadLogic Overhead
Number of VectorsNumber of VectorsClock cycles/vectorClock cycles/vectorTotal clock cyclesTotal clock cycles
Number of Scan FFsNumber of Scan FFsLogic OverheadLogic Overhead
Number of VectorsNumber of VectorsClock cycles/vectorClock cycles/vectorTotal clock cyclesTotal clock cycles
Full ScanFull Scan448448
24.6%24.6%3434449449
15,71415,714
Full ScanFull Scan448448
24.6%24.6%3434449449
15,71415,714
Partial ScanPartial Scan256256
14.1%14.1%4141262262
10,99810,998
Partial ScanPartial Scan256256
14.1%14.1%4141262262
10,99810,998
Number of Scan FFsNumber of Scan FFsLogic OverheadLogic Overhead
Number of VectorsNumber of VectorsClock cycles/vectorClock cycles/vectorTotal clock cyclesTotal clock cycles
Full ScanFull Scan448448
24.6%24.6%3434449449
15,71415,714
Partial ScanPartial Scan256256
14.1%14.1%4141262262
10,99810,998
Boundary ScanBoundary Scan�� Developed to test interconnect between chips on PCBDeveloped to test interconnect between chips on PCB
��Originally referred to as JTAG (Joint Test Action Group)Originally referred to as JTAG (Joint Test Action Group)��Uses scan design based approach to test external interconnectUses scan design based approach to test external interconnect��NoNo--contact probe overcomes problems of “incontact probe overcomes problems of “in--circuit” testing:circuit” testing:
��Surface mount components with less than 100 mil pin spacingSurface mount components with less than 100 mil pin spacing��DoubleDouble--sided component mounting sided component mounting ��MicroMicro-- and floating and floating viasvias
�� Provides standardized test interfaceProvides standardized test interface
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�� Provides standardized test interfaceProvides standardized test interface��IEEE standard 1149.1 IEEE standard 1149.1 ��Four wire interface Four wire interface
�� TMS TMS -- Test Mode SelectTest Mode Select�� TCK TCK -- Test ClockTest Clock�� TDI TDI -- Test Data InTest Data In�� TDO TDO -- Test Data OutTest Data Out
Defined by IEEE 1149.1 standard:Defined by IEEE 1149.1 standard:�� Mandatory InstructionsMandatory Instructions
��ExtestExtest –– to test external interconnect between ICsto test external interconnect between ICs��Bypass Bypass –– to bypass BS chain in ICto bypass BS chain in IC��Sample/Preload Sample/Preload –– BS chain samples external I/OBS chain samples external I/O��IDCodeIDCode––3232--bit device IDbit device ID
��IntestIntest –– to test internal logic within the ICto test internal logic within the IC��RunBISTRunBIST –– to execute internal Builtto execute internal Built--In SelfIn Self--TestTest
�� If applicable (this is rare)If applicable (this is rare)
��UserCodeUserCode –– 3232--bit programming data codebit programming data code��For programmable logic circuitsFor programmable logic circuits
��User Defined InstructionsUser Defined Instructions
��Public instructions (available for customer use)Public instructions (available for customer use)
��Private instructions (for the manufacturer use only)Private instructions (for the manufacturer use only)
��Extending the standard to a universal interfaceExtending the standard to a universal interface��For any system operation feature or functionFor any system operation feature or function
��A communication protocol to access new IC test functionsA communication protocol to access new IC test functions
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��A communication protocol to access new IC test functionsA communication protocol to access new IC test functions
��Allows realAllows real--time sampling of devices on boardtime sampling of devices on board
��Useful at wafer test Useful at wafer test (fewer probes needed)(fewer probes needed)�� BS path reconfigured to bypass ICs not under test for faster testBS path reconfigured to bypass ICs not under test for faster test
��Logic: about 300 gates/chip for TAP + about 15 gates/pinLogic: about 300 gates/chip for TAP + about 15 gates/pin��Overall overhead typically small (1Overall overhead typically small (1--3%)3%)
��But significant for only testing external interconnectBut significant for only testing external interconnect
�� 5 if optional TRST (Test Reset) pin is included5 if optional TRST (Test Reset) pin is included
��I/O delay penalty I/O delay penalty �� 1 MUX delay on all input & output pins1 MUX delay on all input & output pins
��This can be reduced by designThis can be reduced by design
�� Internal scan design cannot have multiple chainsInternal scan design cannot have multiple chains
�� Cannot test at system clock speedCannot test at system clock speed
��But internal BIST can run at system clock speedBut internal BIST can run at system clock speed
BuiltBuilt--In SelfIn Self--Test (BIST)Test (BIST)�� Provides the capability of a circuit to test itselfProvides the capability of a circuit to test itself�� Can be applied hierarchically: module, chip, board, or systemCan be applied hierarchically: module, chip, board, or system�� Provides Provides vertical testabilityvertical testability = same test circuitry used all all = same test circuitry used all all
levels of testing: from chip to systemlevels of testing: from chip to system�� OnOn--line BIST:line BIST: testing occurs during normal system operationtesting occurs during normal system operation�� OffOff--line BIST:line BIST: testing occurs when circuit is outtesting occurs when circuit is out--ofof--serviceservice
�� Area overhead Area overhead �� Performance penaltiesPerformance penalties�� IO pin countIO pin count�� CAD tool supportCAD tool support�� Fault simulationFault simulation�� ATE costATE cost
Power dissipationPower dissipation
Area Overhead Calculation MethodsArea Overhead Calculation Methods
chip areachip areaarea of chip w/DFTarea of chip w/DFT
area of chip w/o DFTarea of chip w/o DFT
number of gatesnumber of gatestotal gates w/DFTtotal gates w/DFT
total gates w/o DFTtotal gates w/o DFTfrequently used frequently used
methodmethodtotal gates for DFTtotal gates for DFTtotal gates w/o DFTtotal gates w/o DFT
most frequently most frequently used methodused method
total gates for DFTtotal gates for DFTtotal gates w/DFTtotal gates w/DFT
number of gate number of gate inputsinputs
total gate inputs for DFTtotal gate inputs for DFTtotal gate inputs w/DFTtotal gate inputs w/DFT
C. Stroud 9/09 Design for Testability 28
�� Power dissipationPower dissipation�� Risk to projectRisk to project
��Increase in design time vs. test time reductionIncrease in design time vs. test time reduction�� Economic impact on productEconomic impact on product
��Impact on product quality and product costImpact on product quality and product cost�� How well does the DFT circuitry get tested?How well does the DFT circuitry get tested?
��Does the BIST circuitry also test itself?Does the BIST circuitry also test itself?
inputsinputs total gate inputs w/DFTtotal gate inputs w/DFTNumber of gate Number of gate
I/OI/Ototal gate I/O for DFTtotal gate I/O for DFTtotal gate I/O w/DFTtotal gate I/O w/DFT