DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited

1

DESIGN AND PERFORMANCE

ANALYSIS OF BINARY ADDERS

A project report submitted towards partial fulfillment of the requirements for the degree of Bachelor in Technology

in

Electronics and Telecommunication Engineering

By

RAHUL HANSDA (11010245)

SHITAL PRASAD BADAIK (11010240), &

MADHU MANASI PATI (11011468),

of 7th semester

Under the guidance of

Dr. Kabiraj Sethi

VEER SURENDRA SAI UNIVERSITY OF

TECHNOLOGY, BURLA, ODISHA

NOVEMBER-2014

2

VEER SURENDRA SAI UNIVERSITY OF TECHNOLOGY, BURLA

CERTIFICATE

This is to certify that the project entitled “DESIGN AND

PERFORMANCE ANALYSIS OF BINARY ADDERS” is carried out

by Rahul Hansda(11010245) ,Shital Prasad Badaik(11010240) , Madhu

Manasi Pati(11011468), and of the Department of Electronics and

Telecommunication Engineering, Veer Surendra Sai University of

Technology, Burla by a the virtue of the diligence and adherence to my

guidance and advice during the academic year 2014-2015.

Dr. D. Mishra Dr.Kabiraj Sethi

Head Of Department, Assistant Professor,

El. & Telecomm. Engg El. & Telecomm. Engg

VSSUT, Burla VSSUT, Burla

3

VEER SURENDRA SAI UNIVERSITY OF TECHNOLOGY, BURLA

CERTIFICATE OF APPROVAL*

This project entitled “DESIGN AND PERFORMANCE ANALYSIS OF

BINARY ADDERS” submitted by Rahul Hansda(11010245),Shital

Prasad Badaik(11010240), Madhu Manasi Pati(11011468), to Veer

Surendra Sai University of Technology, Burla has been examined by us.

It is found fit and approved for the degree of Bachelor of Technology.

INTERNAL EXAMINER EXTERNAL EXAMINER

*Only in case the project is approved

4

ACKNOWLEDGEMENT

We feel honoured of this opportunity to express deep sense of gratitude

to our guide and acknowledge our indebtedness to Dr. Kabiraj Sethi,

Asst. Professor in Department of Electronics and Tele-communication

Engineering for assisting us to select the given project, giving valuable

guidance, encouragement and effort guiding us throughout our project.

We also thank our friends for their support and help they had rendered us

through the preparation of the project.

Rahul Hansda (11010245)

ETC, 7th Semester

Shital Prasad Badaik (11010240)

ETC, 7th Semester

Madhu Manasi Pati (11011468)

ETC, 7th Semester

5

ABSTRACT

Adders are one of the most widely implemented blocks of

microprocessor chips and digital components in the digital integrated

circuit design. They are the necessary part of Digital Signal Processing (DSP)

applications. With the advances in technology, researchers have tried and

are trying to design adders which offer either high speed, low power

consumption, less area or the combination of them.

Every adder generates a carry value that has to be propagated through

the circuit within a series of adders. This contributes largely to the critical

path delay of the circuit. By reducing the number of stages the carry has to

be propagated, the delay in the circuit can be reduced. The required sum is

selected using a multiplexer. This project deals with the design of various

adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry

Increment Adder (CIA), Carry Look Ahead Adder (CLAA), Carry Save

Adder (CSA), Carry Select Adder (CSlA), are discussed and the

performance parameters of adders such as area and delay are determined

and compared. Various adders are designed using Verilog HDL. Then, they

are simulated and synthesized using Xilinx ISE 8.2i for Spartan 3 family

device with speed grade -5.

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CONTENTS

CHAPTER 1

1. Introduction

CHAPTER 2 2.0 Binary adders

2.0.1 Half adder 2.0.2 Full Adder

2.1 Types of adders 2.1.1 Ripple Carry Adder 2.1.2 Carry Look Ahead Adder

2.1.3 Carry Select Adder 2.1.4 Carry Save Adder

2.1.5 Carry Increment adder 2.1.6 Carry Skip Adder

CHAPTER 3 Design of Adders

3.1 Design of Ripple Carry Adder 3.1.1 Design of 4-bit Ripple Carry Adder

3.1.2 Design of 8-bit Ripple Carry Adder 3.1.3 Design of 16-bit Ripple Carry Adder

3.2 Design of Carry-Look Ahead Carry Adder 3.2.1 Design of 4-bit Carry-Look Ahead Carry Adder

3.2.2 Design of 8-bit-Carry-Look Ahead Carry Adder 3.2.3 Design of 16-bit-Carry-Look Ahead Carry Adder

3.3 Design of Carry Select Adder

3.3.1 Design of 4-bit Carry Select Adder 3.3.2 Design of 8-bit Carry Select Adder

3.3.3 Design of 16-bit Carry Select Adder

3.4 Design of Carry Skip Adder

3.4.1 Design of 4-bit Carry Skip Adder 3.4.2 Design of 8-bit Carry Skip Adder 3.4.3 Design of 16-bit Carry Skip Adder

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3.5 Design of Carry Increment Adder 3.5.1 Design of 4-bit Carry Increment Adder

3.5.2 Design of 8-bit Carry Increment Adder 3.5.3 Design of 16-bit Carry Increment Adder

3.6 Design of Carry Save Adder 3.6.1 Design of 4-bit Carry Save Adder

3.6.2 Design of 8-bit Carry Save Adder 3.6.3 Design of 16-bit Carry Save Adder

CHAPTER 4

Discussion and Results

CHAPTER 5 Conclusion

References Bibliography

Appendix

8

LIST OF FIGURES

1. Figure 2.1 Half Adder logic diagram

2. Table 1.Truth Table for Half Adder

3. Figure2. 3 Full Adder circuit

4. Table 2.Truth Table for Full Adder circuit

5. Figure2. 3 Full Adder circuit

6. Figure 2.4 Truth Table for Full Adder cir

7. Fig. 2.5 Architecture of Ripple Carry Adder (RCA)

8. Figure 2.6 Carry Look Ahead Adder

9. Figure 2.7 Flowchart of Carry look Ahead Adder

10. Figure 2.8 Carry Select Adder

11. Fig. 2.9 Carry Save Adder (CSA)

12. Fig. 2.10 Carry Increment Adder

13. Fig 2.11 Carry Skip Adder

14. Table-3: Performance analysis of adders

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Chapter1

1. INTRODUCTION

The objective of this project is to design different architectures of adders and to study

their respective performance, cost and design time. Adders are being used extensively in

many processor architectures and computational units. It is a vital part in any processor

or chip. By reducing the area occupied by these adders, the critical path delay can also be

reduced. This can be done by implementing different designs of these adders. The

ultimate aim of reducing the area and design is to optimize the cost of manufacture and

improve the efficiency of the processor.

Every adder generates a carry value that has to be propagated through the circuit within

a series of adders. This contributes largely to the critical path delay of the circuit. By

reducing the number of stages the carry has to be propagated, the delay in the circuit can

be reduced. This can be done by implementing different architectures of the adder

design and by incorporating varied logic to propagate the carry through the least

number of stages possible. One by looking ahead of several blocks, i.e., by identifying

where the actual output is and by delivering the carry signal right to that stage or by

calculating the sum before the propagation is started. The required sum is selected using

a multiplexer.

In the above cases, the carry signal is not propagated through more than three stages

which reduce the delay in the circuit. The various designs of adders are explained as

follows. In this project, we implement the following adders:

Carry Ripple Adder

Carry Skip Adder

Carry Select Adder

Carry Look Ahead adder

Carry Save Adder

Carry Increment Adder

The above designs are verified by performing the following steps

RTL design using synthesis

Logic simulation using Xilinx simulator

Place and Route for power analysis

Synthesis report for area and delay

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Chapter 2

BINARY ADDERS

In electronics, an adder or summer is a digital circuit that performs addition of numbers.

In many computers and other kinds of processors, adders are used not only in the

arithmetic logic unit(s), but also in other parts of the processor, where they are used to

calculate addresses, table indices, and similar operations.

Although adders can be constructed for many numerical representations, such as binary-

coded decimal or excess-3, the most common adders operate on binary numbers, hence

named Binary Adders.

Starting with the basic blocks of adder circuits-Half Adder and Full Adder we shall see

how complex adder circuits are designed using these basic blocks.

Half –Adder: The half adder adds two single binary digits A and B. It has two outputs,

sum (S) and carry (C). The carry signal represents an overflow into the next digit of a

multi-digit addition. The value of the sum is 2C + S.

The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and

an AND gate for C. The half adder adds two input bits and generates a carry and sum,

which are the two outputs of a half adder.

Figure 2.1 Half Adder logic diagram

Figure2.2 Truth Table for Half Adder

Full Adder: A full adder adds binary numbers and accounts for values carried in as well

as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A

and B are the operands, and Cin is a bit carried in from the previous stage. The circuit

produces a two-bit output, output carry and sum typically represented by the

signals Cout and S.

Input Output

A

B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Digital_circuit

http://en.wikipedia.org/wiki/Addition

http://en.wikipedia.org/wiki/Computer

http://en.wikipedia.org/wiki/Arithmetic_logic_unit

http://en.wikipedia.org/wiki/Binary-coded_decimal

http://en.wikipedia.org/wiki/Binary-coded_decimal

http://en.wikipedia.org/wiki/Excess-3

http://en.wikipedia.org/wiki/Binary_numeral_system

http://en.wikipedia.org/wiki/XOR_gate

http://en.wikipedia.org/wiki/AND_gate

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A full adder can be implemented in many different ways such as with a custom transistor-

level circuit or composed of other gates. One example implementation is with

and

Figure2. 3 Full Adder circuit Figure 2.4 Truth Table for Full Adder circuit

Ripple Carry Adder:

Ripple Carry Adder (RCA) is a basic adder which works on basic addition principle [1].

The architecture of RCA is shown in Fig 2.5.

Fig. 2.5 Architecture of Ripple Carry Adder (RCA)

RCA contains series structure of Full Adders (FA); each FA is used to add two bits along

with carry bit.

The carry generated from each full adder is given to next full adder and so on. Hence, the

carry is propagated in a serial computation. Hence, delay is more as the number of bits is

increased in RCA.

Carry Look-Ahead Adder:

Carry Look Ahead (CLA) design is based on the principle of looking at lower adder bits

of argument

and addend if higher orders carry generated. This adder reduces the carry delay by

reducing the number of gates through which a carry signal must propagate. As shown in

Fig 2.5, in the generation and propagation stage, the generation values, propagation

values are computed. Internal carry generation is calculated in second stage. And in final

stage, the sum is calculated. The flow chart of CLA is given in Fig 2.5 and the architecture

of CLA is given in Fig 2.6.

Input A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

Output Cout 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

http://en.wikipedia.org/wiki/Transistor

12

Figure 2.5 Carry Look Ahead Adder Figure 2.6 Flowchart of Carry look Ahead Adder

Carry Select Adder:

Carry Select Adder (CSlA) architecture consists of independent generation of sum and

carry i.e. Cin=1 and Cin=0 are executed parallelly. Depending upon Cin, the external

multiplexers select the carry to be propagated to next stage. Further, based on the carry

input, the sum will be selected. Hence, the delay is reduced.

However, the structure is increased due to the complexity of multiplexers. The

architecture of CSlA is illustrated in Fig. 2.7

Figure 2.7 Carry Select Adder

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Carry Save Adder:

In Carry Save Adder (CSA), three bits are added parallelly at a time. In this scheme, the

carry is not propagated through the stages. Instead, carry is stored in present stage, and

updated as addend value in the next stage. Hence, the delay due to the carry is reduced

in this scheme.

The architecture of CSA is shown in Fig 2.8.

Fig. 2.8 Carry Save Adder (CSA)

Carry Increment Adder:

The design of Carry Increment Adder (CIA) consists of RCA’s and incremental circuitry.

The incremental circuit can be designed using HA’s in ripple carry chain with a

sequential order. The addition operation is done by dividing total number of bits in to

group of 4bits and addition operation is done using several 4bit RCA’s. The architecture

of CIA is shown in Fig 2.9

Fig. 2.9 Carry Increment Adder

Carry Skip Adder:

As the name indicates, Carry Skip Adder (CSkA) uses skip logic in the propagation of

carry. It is

designed to speed up the addition operation by adding a propagation of carry bit around

a portion of entire adder. The carry-in bit designated as Ci. The output of RCA (the last

stage) is Ci+4. The Carry Skip circuitry consists of two logic gates. AND gate accepts the

carry-in bit and compares it with the group of propagated signals.

Pi, Pi+3= (Pi+3)*(Pi+2)*(Pi+1)*Pi & Carry= Ci+4 + (Pi, i+3)* Ci

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The architecture of CSkA is shown in Fig 2.10

Fig 2.10: Carry Skip Adder

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Chapter 3

DESIGN OF BINARY ADDER

3.1 Design of Ripple Carry Adder

3.1.1 Design of 4 bit Ripple Carry Adder

The RTL design of Ripple Carry adder uses input vector a, b, and carry input Cin and

output vector i.e. output sum vector is denoted by S and final carry output by Cout. The

schematic diagram of 4-bit Ripple Carry Adder is depicted below.

a. RTL Schematic Design

b.Xilinx ISE simulator result

Considering the following data:

Input Vector 1: 9, Input Vector 2: 11 and Carry Input: 2

We have theoretical value of S: 20

The same can be observed in the following simulation result depicted below for a 4-bit RCA.

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The RTL design of Ripple Carry adder uses input vector a, b, and carry input Cin and output vector i.e.

output sum vector is denoted by S and final carry output by Cout. The schematic diagram of 8 -bit Ripple

carry adder is depicted below.


b. Xilinx ISE Simulator result:





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The RTL design of Ripple Carry adder uses input vector a, b, and carry input Cin and output vector i.e.

output sum vector is denoted by S and final carry output by Cout. The schematic diagram of 16 -bit Ripple

Carry Adder is depicted below.







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3.2 Design of Carry Look Ahead Adder

3.2.1 Design of 4 bit Carry Look Ahead Adder

The RTL design of Carry look ahead adder uses input vector a, b, and carry input Cin and output vector

i.e. output sum vector is denoted by S and final carry output by Cout. The schematic diagram of 4 -bit

Carry Look Ahead adder is depicted below.


9




We have theoretical value of S: 4’b0110

The same can be observed in the following simulation result depicted below for a 4 -bit CLA.

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b. Xilinx ISE Simulator result



We have theoretical value of S:203

The same can be observed in the following simulation result depicted below for a 8-bit CLA.

20










The same can be observed in the following simulation result depicted below for a 16-bit CLA.

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3.3 Design of Carry Select Adder

3.3.1 Design of 4 bit Carry Select Adder

The RTL design of Carry Select adder uses input vector a, b, and carry input Cin and output vector i.e.

output sum vector is denoted by S and final carry output by Cout. The schematic diagram of 4 -bit Carry

Select adder is depicted below.


b.Xilinx ISE Simulator result:



We have theoretical value of S:14

The same can be observed in the following simulation result depicted below for a 4 -bit CSA.

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Look Ahead adder is depicted below.


b. Xilinx ISE simulator result




The same can be observed in the following simulation result depicted below for a 8-bit CSA.

23











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3.4 Design of Carry Save Adder


The RTL design of Carry Select adder uses input vector a, b, and carry input Ci and output vector i.e.







We have theoretical value of S: 4’b1001


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output sum vector is denoted by S and final carry output by Cout. The schematic diagram of 8-bit Carry

Select Adder is depicted below.







26






b. Xilinx ISE simulator result:




The same can be observed in the following simulation result depicted below for a 16 -bit CSA.

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3.5 Design of Carry Increment Adder

3.5.1 Design of 4 bit Carry Increment Adder

The RTL design of Carry Increment adder uses input vector a, b, and carry input Cin and output vector




b. Xilinx ISE simulator results:




The same can be observed in the following simulation result depicted below for a 4 -bit CIA.

3.5.2 Design of 8 bit Carry Increment Adder

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Carry Increment adder is depicted below.




Input Vector 1:29, Input Vector 2: 3 and Carry Input: 0


The same can be observed in the following simulation result depicted below for a 8-bit CIA.

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3.5.3 Design of 16- bit Carry Increment Adder


i.e. output sum vector is denoted by S and final carry output by Cout. The schematic dia gram of 16-bit

Carry Increment adder is depicted below.





We have theoretical value of S: 17’b 0042

The same can be observed in the following simulation result depicted below for a 16-bit CIA.

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3.6 Design of Carry Skip Adder

3.6.1 Design of 4- bit Carry Skip Adder

The RTL design of Carry Skip adder uses input vector a, b, and carry input Cin and output vector i.e.


Skip adder is depicted below.




Input Vector 1: 5, Input Vector 2:7 and Carry Input: 0



31











32











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Results and Discussion

There are six different complex adder circuit design which have been developed using

Verilog-HDL and synthesized in the ISE simulator tool using Xilinx ISE 8.2.Table I

exhibits post simulation results of the conventional adder circuits in terms of

Propagation delay (in ns), Area (in terms of No. of Slices and LUTs) and Power (in

mW).The Area Indicated the total cell area of the design; the total power is sum of

dynamic power, internal power, net power and leakage power. The delay is the critical

path delay of the adder circuits [2].

The results shows that for a 4-bit adder circuit, the Carry Increment Adder circuit

has higher speed and minimum area when compared to other conventional adder

circuits depicted by the figure (2.9).

The results shows that for a 8-bit adder circuit, the Carry Increment Adder circuit

has higher speed depicted by figure(2.9) and the Carry Look Ahead Adder has

minimum area when compared to other conventional adder circuits depicted by

the figure (2.5).

The results shows that for a 16-bit adder circuit, the Carry Skip Adder circuit has

higher speed and minimum area when compared to other conventional adder

circuits depicted by the figure (2.10).

The marginal improvement in speed increases with the rise in word size of the adder.

This shows very well that the design can be incorporated into complex VLSI Design and

DSP applications in order to increase the operating speed of the circuits without

compromising in terms of area and path delay due to large carry chains.

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T A B U L A T I O N

The Tabulation compares adder circuits for the area for different word sizes. It shows

that the area of ( ) adder circuit occupies minimum area when compared to other

conventional adder counterparts. The amount of area gain achieved in ( ) adder circuit

increases with word-size of the adders.

Table-3: Performance analysis of adders

4-bit 8-bit 16-bit

Types of Adders Area Pow

er(in mW)

Dela

y(in ns)

Area Powe

r(in mW)

Del

ay ( in

ns)

Area Powe

r(in mW)

Del

ay (in

ns)

Ripple Carry Adder Slice-04 LUT-08

I/O-14

56.05

13.902

Slice-08

LUT-15

I/O-26

56.05 18.646

Slice-18

LUT-

32

I/O-50

56.05 33.378

Carry Look Ahead

Adder

Slice-04

LUT-08

I/O-14

56.0

5

11.89

7

Slice-

08

LUT-15

I/O-26

56.05 15.7

49

Slice-

19

LUT-

33 I/O-50

56.05 26.4

86

Carry Select Adder Slice-06

LUT-11 I/O-14

56.0

5

11.54

7

Slice-

13 LUT-24

I/O-26

56.05 14.9

03

Slice-

30 LUT-

56

I/O-50

56.05 19.9

34

Carry Save Adder Slice-03

LUT-06

I/O-14

56.0

5

9.142 Slice-

13

LUT-23

I/O-26

56.05 15.0

96

Slice-

31

LUT-

54

I/O-50

56.05 18.4

85

Carry Increment

Adder

Slice-03

LUT-06

I/O-14

56.0

5

9.043 Slice-

11

LUT-20 I/O-27

56.05 14.1

43

Slice-

24

LUT-42

I/O-51

56.05 23.2

49

Carry Skip Adder Slice-04 LUT-08

I/O-14

56.05

13.521

Slice-09

LUT-15

I/O-26

56.05 15.345

Slice-14

LUT-

25

I/O-50

56.05 18.552

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Conclusion:

The selected adder circuit with minimum area, power and delay is Carry Increment

Adder for 4-bit, in case of an 8-bit, there is a competence between Carry Look Ahead and

Carry Increment Adder and in case of a 16-bit, Carry Skip adder has minimum area and

delay which proves to be easy solution in improving the speed of the adder circuit over

other conventional adder circuits in discussion suffering from disadvantage of either

occupying more number of slices or look-up tables per unit of cell or have highest

minimum propagation delay owing to their critical carry path for same power (in

mW).The selected adder circuit is also found to have comparatively less power

consumption in comparison to other adder circuits. Hence it can be concluded on our

part that above respective adder circuit on the basis of different word size can be used to

speed up the final addition in parallel multiplier circuits and other architectures which

uses adder circuits no doubt, exhibiting maximum efficiency. The structure has been

synthesized using Xilinx ISE 8.2i and simulated using ISE simulator tool.

36

References:

1. A Very Fast and Low Power Carry Select Adder Circuit -Samiappa Sakthikumaran1,

S. Salivahanan, V. S. Kanchana Bhaaskaran2, V. Kavinilavu, B. Brindha and C. Vinoth,

Department of Electronics and Communication Engineering,SSN College of

Engineering, Kalavakkam, (Off)Chennai [email protected],

[email protected]

2. International Journal of Science and Research (IJSR), Simulation of Different bit

Carry-Skip Adder in Verilog ,Sangeeta Rani1, Sachin Kumar2 1M. Tech Student,

Department of Electronics & Communication,2Faculty, Department of Electronics &

Communication, Meri College of Engineering & Technology, Sampla,Haryana, India

3. Efficient Implementation of Carry Save Adder, Sabyasachi Bhowmick , Mr. P. Mohan

Kumar Student – Department of Electronics & Communication Engineering ; LPU ;

Punjab, India Assistant Professor – Dept. of Electronics & Communication

Engineering ; LPU ; Punjab, India [email protected] [email protected]

4.International Journal of Computer Science and Mobile Computing, IJCSMC, Vol. 2,

Issue. 9, September 2013,RESEARCH ARTICLE, Design and Performance Analysis of

Various Adders using Verilog Maroju SaiKumar1, Dr. P. Samundiswary2 ¹Student,

Department of Electronics Engineering, Pondicherry University, Pondicherry,

India;²Assistant Professor, Department of Electronics Engineering, Pondicherry

University, Pondicherry, India

1 [email protected]; 2 [email protected]

5 http://en.wikipedia.org/wiki/Adder_%28electronics%29

6. 1999 Computer Arithmetic –Algorithms and Hardware Designs, Behrooz Parhami, Dept. of Electrical

and Computer Engineering, University of California, Santa Barbara

7. Digital Design 3rd Edition –M. Morris Mano

mailto:[email protected],%[email protected]

mailto:[email protected],%[email protected]

mailto:[email protected]

mailto:[email protected]

http://en.wikipedia.org/wiki/Adder_%28electronics%29

37

Appendix:A HDL Codes Verilog Code for 4-bit Ripple Carry Adder

module rip2(s,cout,a,b,cin);

//sub module for 4 bit Ripple carry adder

input [3:0]a;

input [3:0]b;

input cin;

output cout;

output [3:0]s;

wire c2,c3,c4,cout;

fa m1(s[0],c2,a[0],b[0],cin);

fa m2(s[1],c3,a[1],b[1],c2);

fa m3(s[2],c4,a[2],b[2],c3);

fa m4(s[3],cout,a[3],b[3],c4);

endmodule

module fa(s,cout,a,b,cin);

//sub module for Full adder

input a,b,cin;

output s,cout;

wire w1,w2,w3;

ha m1(w1,w2,a,b);

ha m2(s,w3,w1,cin);

or m3(cout,w2,w3);

endmodule

module ha(s,cout,a,b);

//sub module for Half adder

input a,b;

output s,cout;

xor m1(s,a,b);

and m2(cout,a,b);

endmodule

Verilog Code for 8-bit Ripple Carry Adder

module rip(s,cout,a,b,cin);

38

//main module of 8 bit Ripple carry adder

input [7:0]a;

input [7:0]b;

input cin;

output cout;

output [7:0]s;

wire c4,c8,cout;

rip2 m1(s[3:0],c4,a[3:0],b[3:0],cin);

rip2 m2(s[7:4],c8,a[7:4],b[7:4],cout);

endmodule



input [3:0]a;

input [3:0]b;

input cin;

output cout;

output [3:0]s;

wire c2,c3,c4,cout;

fa m1(s[0],c2,a[0],b[0],cin);

fa m2(s[1],c3,a[1],b[1],c2);

fa m3(s[2],c4,a[2],b[2],c3);

fa m4(s[3],cout,a[3],b[3],c4);

endmodule



input a,b,cin;

output s,cout;

wire w1,w2,w3;

ha m1(w1,w2,a,b);

ha m2(s,w3,w1,cin);

or m3(cout,w2,w3);

endmodule



input a,b;

output s,cout;

xor m1(s,a,b);

and m2(cout,a,b);

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endmodule

Verilog Code for 16-bit Ripple Carry Adder

module rip(s,cout,a,b,cin);

//main module of 16 bit Ripple carry adder

input [15:0]a;

input [15:0]b;

input cin;

output cout;

output [15:0]s;

wire c4,c8,c12,cout;

rip2 m1(s[3:0],c4,a[3:0],b[3:0],cin);

rip2 m2(s[7:4],c8,a[7:4],b[7:4],c4);

rip2 m3(s[11:8],c12,a[11:8],b[11:8],c8);

rip2 m4(s[15:12],cout,a[15:12],b[15:12],c12);

endmodule



input [3:0]a;

input [3:0]b;

input cin;

output cout;

output [3:0]s;

wire c2,c3,c4,cout;

fa m1(s[0],c2,a[0],b[0],cin);

fa m2(s[1],c3,a[1],b[1],c2);

fa m3(s[2],c4,a[2],b[2],c3);

fa m4(s[3],cout,a[3],b[3],c4);

endmodule



input a,b,cin;

output s,cout;

wire w1,w2,w3;

ha m1(w1,w2,a,b);

ha m2(s,w3,w1,cin);

or m3(cout,w2,w3);

endmodule

40



input a,b;

output s,cout;

xor m1(s,a,b);

and m2(cout,a,b);

endmodule

Appendix:B

Verilog code for 4 bit Carry Lookahead Adder

//4-bit ripple carry adder

module RCA(A,B,Ci,So,Co);

//outputs

output [3:0] So ;

output Co ;

//inputs

input [3:0] A ;

input [3:0] B ;

input Ci ;

//internal wiring

wire c1,c2,c3,c4;

wire g0,g1,g2,g3;

wire p0,p1,p2,p3;

//g = A * B

assign g0=A[0]&B[0];




//p = A + B

assign p0=A[0]|B[0];




//c = g + (p * Ci)...

assign c1=g0|(p0&Ci);

assign c2=g1|(p1&g0)|(p1&p0&Ci);

assign c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&Ci);

assign c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&Ci);

assign Co=c4;

41

//S = g XOR p XOR C

assign So[0]=g0^p0^Ci;

assign So[1]=g1^p1^c1;



endmodule

Verilog Code for 8-bit Ripple Carrylookahead Adder

module CLA8(sum,carryout,A_in,B_in,carryin);

output [7:0] sum;

output carryout;

input [7:0] A_in;

input [7:0] B_in;

input carryin;

wire [7:0] sum;

wire carryout;

wire [2:0] carry;

cla4 c1(sum[3:0],carry[0],A_in[3:0],B_in[3:0],carryin);

cla4 c2(sum[7:4],carry[1],A_in[7:4],B_in[7:4],carry[0]);

//cla4 c3(sum[11:8],carry[2],A_in[11:8],B_in[11:8],carry[1]);

//cla4 c4(sum[15:12],carryout,A_in[15:12],B_in[15:12],carry[2]);

endmodule

//***************** 4-bit carry look-ahead adder **********************

module cla4(s,cout,i1,i2,c0);

output [3:0] s; //summation

output cout; //carryout

input [3:0] i1; //input1


input c0;

wire [3:0] s;

wire cout;

wire [3:0] g;

wire [3:0] p;

wire [3:1] c;

assign g[3:0]=i1[3:0] & i2[3:0]; //carry generation

assign p[3:0]=i1[3:0] ^ i2[3:0]; //carry propagation

assign c[1]=g[0] | (p[0] & c0); //calculate each stage carryout

assign c[2]=g[1] | (g[0] & p[1]) | (p[0] & p[1] & c0);

assign c[3]=g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) | (p[0] & p[1] & p[2] &

42

c0);

assign cout=g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3])

| (g[0] & p[1] & p[2] & p[3]) | (p[0] & p[1] & p[2] & p[3] & c0);

assign s[0]=p[0]^c0; //calculate summation

assign s[3:1]=p[3:1]^c[3:1];

endmodule

Verilog Code for 16-bit Ripple Carrylookahead Adder

module cla16(sum,carryout,A_in,B_in,carryin);

output [15:0] sum;

output carryout;

input [15:0] A_in;

input [15:0] B_in;

input carryin;

wire [15:0] sum;

wire carryout;

wire [2:0] carry;

cla4 c1(sum[3:0],carry[0],A_in[3:0],B_in[3:0],carryin);



cla4 c4(sum[15:12],carryout,A_in[15:12],B_in[15:12],carry[2]);

endmodule

//***************** 4-bit carry look-ahead adder **********************

module cla4(s,cout,i1,i2,c0);

output [3:0] s; //summation

output cout; //carryout



input c0; //?????

wire [3:0] s;

wire cout;

wire [3:0] g;

wire [3:0] p;

wire [3:1] c;

assign g[3:0]=i1[3:0] & i2[3:0]; //carry generation

assign p[3:0]=i1[3:0] ^ i2[3:0]; //carry propagation

assign c[1]=g[0] | (p[0] & c0); //calculate each stage carryout

assign c[2]=g[1] | (g[0] & p[1]) | (p[0] & p[1] & c0);

assign c[3]=g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) | (p[0] & p[1] & p[2] &

43

c0);

assign cout=g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3])

| (g[0] & p[1] & p[2] & p[3]) | (p[0] & p[1] & p[2] & p[3] & c0);

assign s[0]=p[0]^c0; //calculate summation

assign s[3:1]=p[3:1]^c[3:1];

endmodule

Appendix:C

Verilog Code for 4-bit Carry Select Adder

module csa(a,b,cin,sum,co);

input [3:0]a;

input [3:0]b;

input cin;

output [3:0]sum;

output co;

wire [3:0]sum;

wire co;

wire s1,c1,s2,c2,s3,c3,s4,s11,s44,c4,c11,s22,c22,s33,c33,c44;

//assuming carry in 0

fa x1(a[0],b[0],0,s1,c1);

fa x2(a[1],b[1],c1,s2,c2);

fa x3(a[2],b[2],c2,s3,c3);

fa x4(a[3],b[3],c3,s4,c4);


fa x5(a[0],b[0],1,s11,c11);

fa x6(a[1],b[1],c11,s22,c22);

fa x7(a[2],b[2],c22,s33,c33);

fa x8(a[3],b[3],c33,s44,c44);

//select either carry 1 or 0 using carry out of FA

//mux for sum select

mux x9(s1,s11,cin,sum[0]);




//mux for carry select

mux x13(c4,c44,cin,co);

endmodule

//fa module

44

module fa(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

wire d,e,f;

xor(sum,a,b,c);

and(d,a,b);

and(e,b,c);

and(f,a,c);

or(carry,d,e,f);

endmodule

//mux module

module mux(a,b,s,q);

input a;

input b;

input s;

output q;

wire q;

assign q=s?b:a;

endmodule


module CSA_8bit(a,b,cin,sum,co);

input [7:0]a;

input [7:0]b;

input cin;

output [7:0]sum;

output co;

wire [7:0]sum;

wire co;

wire s1,c1,s2,c2,s3,c3,s4,s11,s44,c4,c11,s22,c22,s33,c33,c44;


fa x1(a[1:0],b[1:0],0,s1,c1);

fa x2(a[3:2],b3:2],c1,s2,c2);

fa x3(a[5:4],b[5:4],c2,s3,c3);

fa x4(a[7:6],b[7:6],c3,s4,c4);


45

fa x5(a[1:0],b[1:0],1,s11,c11);

fa x6(a[3:2],b[3:2],c11,s22,c22);

fa x7(a[5:4],b[5:4],c22,s33,c33);

fa x8(a[7:6], b[7:6],c33,s44,c44);



mux x9(s1,s11,cin,sum[1:0]);






endmodule

//fa module


input a;

input b;

input c;

output sum;

output carry;

wire d,e,f;

xor(sum,a,b,c);

and(d,a,b);

and(e,b,c);

and(f,a,c);

or(carry,d,e,f);

endmodule

//mux module


input a;

input b;

input s;

output q;

wire q;

assign q=s?b:a;

endmodule


module csa16bit(a,b,cin,sum,co);

46

input [15:0]a;

input [15:0]b;

input cin;

output [15:0]sum;

output co;

wire [15:0]sum;

wire co;

wire

s1,c1,s2,c2,s3,c3,s4,s5,c5,s6,c6,s7,c7,s8,c8,s9,c9,s10,c10,s11,c11,s12,c12,s13,c13,s14,c14,s15,c

15,s16,c16,

s111,s44,c32,c111,s22,c22,s33,c33,c44,s55,s88,c55,s66,c66,s77,c77,c88,s99,c99,s1010,c1010,s1

111,c1111,s1212,c1212,s1313,c1313,s1414,c1414,s1515,c1515,s1616,c1616;


fa x1(a[0],b[0],0,s1,c1);

fa x2(a[1],b[1],c1,s2,c2);

fa x3(a[2],b[2],c2,s3,c3);

fa x4(a[3],b[3],c3,s4,c4);

fa x5(a[4],b[4],c4,s5,c5);

fa x6(a[5],b[5],c5,s6,c6);

fa x7(a[6],b[6],c6,s7,c7);

fa x8(a[7],b[7],c7,s8,c8);

fa x9(a[8],b[8],c8,s9,c9);

fa x10(a[9],b[9],c9,s10,c10);

fa x11(a[10],b[10],c10,s11,c11);

fa x12(a[11],b[11],c11,s12,c12);

fa x13(a[12],b[12],c12,s13,c13);

fa x14(a[13],b[13],c13,s14,c14);

fa x15(a[14],b[14],c14,s15,c15);

fa x16(a[15],b[15],c15,s16,c16);

//assuming carry 1

fa x17(a[0],b[0],1,s111,c111);

fa x18(a[1],b[1],c111,s22,c22);

fa x19(a[2],b[2],c22,s33,c33);

fa x20(a[3],b[3],c33,s44,c44);

fa x21(a[4],b[4],c44,s55,c55);

fa x22(a[5],b[5],c55,s66,c66);

fa x23(a[6],b[6],c66,s77,c77);

fa x24(a[7],b[7],c77,s88,c88);

fa x25(a[8],b[8],c88,s99,c99);

fa x26(a[9],b[9],c99,s1010,c1010);

47

fa x27(a[10],b[10],c1010,s1111,c1111);

fa x28(a[11],b[11],c1111,s1212,c1212);

fa x29(a[12],b[12],c1212,s1313,c1313);

fa x30(a[13],b[13],c1313,s1414,c1414);

fa x31(a[14],b[14],c1414,s1515,c1515);

fa x32(a[15],b[15],c1515,s1616,c1616);













mux x43(s11,s1111,cin,sum[10]);

mux x44(s12,s1212,cin,sum[11]);

mux x45(s13,s1313,cin,sum[12]);

mux x46(s14,s1414,cin,sum[13]);

mux x47(s15,s1515,cin,sum[14]);

mux x48(s16,s1616,cin,sum[15]);



endmodule

//fa module


input a;

input b;

input c;

output sum;

output carry;

wire d,e,f;

xor(sum,a,b,c);

and(d,a,b);

and(e,b,c);

48

and(f,a,c);

or(carry,d,e,f);

endmodule

//mux module


input a;

input b;

input s;

output q;

wire q;

assign q=s?b:a;

endmodule

Appendix:D

Verilog Code for 4-bit Carry Save Adder

module csa4(a,b,ci,s,co);

input [3:0]a;

input [3:0]b;

input ci;

output co;

output [3:0]s;

wire [5:0]c;

wire [3:0]stemp;

//overall circuit

FA x1(a[0],b[0],ci,s[0],c[0]);

FA x2(a[1],b[1],c[0],s[1],c[1]);

FA x3(a[2],b[2],1,stemp[0],c[2]);

FA x4(a[3],b[3],c[2],stemp[1],c[3]);

FA x5(a[2],b[2],1,stemp[2],c[4]);

FA x6(a[3],b[3],c[4],stemp[3],c5);

//conditional assignments

assign s[2]= c[1]?stemp[0]:stemp[1];

assign s[3]= c[1]?stemp[2]:stemp[3];

assign co=c[1]?c[3]:c[5];

endmodule

//FA module

module FA(a,b,cin,s,co);

49

input a,b,cin;

output s,co;

wire d,e,f;

xor (s,a,b,c);

and (d,a,b);

and (e,b,c);

and (f,a,c);

or (co,d,e,f);

endmodule



module RCA(A,B,Ci,So,Co);

//outputs

output [3:0] So ;

output Co ;

//inputs

input [3:0] A ;

input [3:0] B ;

input Ci ;

//internal wiring

wire c1,c2,c3,c4;

wire g0,g1,g2,g3;

wire p0,p1,p2,p3;

//g = A * B





//p = A + B





//c = g + (p * Ci)...





50

assign Co=c4;

//S = g XOR p XOR C





endmodule

//8-bit carry save adder

module csa8(A,B,Ci,So,Co);

//outputs

output [7:0] So;

output Co;

//inputs

input [7:0] A,B;

input Ci;

//internal wiring

wire [3:0] stemp1,stemp0;

wire c4;

wire c80,c81;

//utilize RCA for CSA

RCA RCAin(A[3:0],B[3:0],Ci,So[3:0],c4);

RCA RCA1 (A[7:4],B[7:4],1'b1,stemp1,c81);



assign So[7:4] = c4?stemp1:stemp0;

assign Co= c4?c81:c80;

endmodule


module CSA16(A,B,Ci,So,Co);

input [15:0] A,B;

input Ci;

output [15:0] So;

output Co;


wire c8;

wire c160,c161;

CSA8 CSA8in(A[7:0],B[7:0],Ci,So[7:0],c8 );

CSA8 CSA81 (A[15:8],B[15:8],1'b1,stemp1,c161);

51

CSA8 CSA80 (A[15:8],B[15:8],1'b0,stemp0,c160);



endmodule


module RCA (A,B,Ci,So,Co);

//outputs

output [3:0] So ;

output Co ;

//inputs

input [3:0] A ;

input [3:0] B ;

input Ci ;

//internal wiring

wire c1,c2,c3,c4;

wire g0,g1,g2,g3;

wire p0,p1,p2,p3;

//g = A * B





//p = A + B





//c = g + (p * Ci)...





assign Co=c4;

//S = g XOR p XOR C





endmodule

52

//8-bit carry save adder

module CSA8(A,B,Ci,So,Co);

//outputs

output [7:0] So;

output Co;

//inputs

input [7:0] A,B;

input Ci;

//internal wiring


wire c4;

wire c80,c81;

//utilize RCA for CSA

RCA RCAin(A[3:0],B[3:0],Ci,So[3:0],c4);






endmodule

Appendix:E

Verilog Code for 4-bit Carry Increment Adder

module cia4bit(a,b,cin,s,co);

input [3:0]a;

input [3:0]b;

input cin;

output [3:0]s;

output co;

wire [2:0]sum;

wire c0,c1,c2,c3,c4,c5;

//overall ckircuit description

FA x1(a[0],b[0],0,s[0],c0);

FA x2(a[1],b[1],c0,s[1],c1);

FA x3(a[2],b[2],0,s[2],c2);

FA x4(a[3],b[3],c2,s[3],c3);

53

//incrementer circuit

HA x5(s[2],c1,sum[0],c4);

HA x6(s[3],c4,sum[1],c5);

HA x7(c3,c5,sum[2],co);

endmodule

//full adder module

module FA(a,b,cin,s,co);

input a,b,cin;

output s,co;

wire d,e,f;

xor (s,a,b,c);

and (d,a,b);

and (e,b,c);

and (f,a,c);

or (co,d,e,f);

endmodule

//half adder module

module HA(a,b,c,s);

input a,b;

output s,c;

xor(s,a,b);

and (c,a,b);

endmodule


module cia8(a,b,cin,s,co);

input [7:0]a;

input [7:0]b;

input cin;

output [7:0]s;

output co;

wire sum4,sum5,sum6,sum7,c[0],c[1],c[2];

//overall circuit desciption

RCA x1(a[3:0],b[3:0],cin,s[3:0],1);

RCA x2(a[7:4],b[7:4],0,sum[7:4],0);

//incrementor circuit

HA x3(sum[4],1,s[4],c[0]);

HA x4(sum[5],c[0],s[5],c[1]);

54

HA x5(sum[6],c[1],s[6],c[2]);

HA x6(sum[7],c[2],s[7],co);

end module

//RCA 4bit module

module RCA (A,B,Ci,So,Co);

//outputs

output [3:0] So ;

output Co ;

//inputs

input [3:0] A ;

input [3:0] B ;

input Ci ;

//internal wiring

wire c1,c2,c3,c4;

wire g0,g1,g2,g3;

wire p0,p1,p2,p3;

//g = A * B





//p = A + B





//c = g + (p * Ci)...





assign Co=c4;

//S = g XOR p XOR C





endmodule

//HA module

module HA(a,b,s,c);

55

input a,b;

output s,c;

xor(s,a,b);

and(c,a,b);

end module


module cia16bit(a,b,cin,s,co);

input [15:0]a;

input [15:0]b;

input cin;

output [16:0]s;

output co;

wire [7:0]c;

wire [16:8]sum;

wire carry,carry1;

//overall circuit desciption

ripplemod x1(a[7:0],b[7:0],cin,s[7:0],carry);

ripplemod x2(a[15:8],b[15:8],0,sum[16:8],carry1);

//incrementor circuit

HA x3(sum[8],carry,s[8],c[0]);

HA x4(sum[9],c[0],s[9],c[1]);

HA x5(sum[10],c[1],s[10],c[2]);

HA x6(sum[11],c[2],s[11],c[3]);

HA x7(sum[12],c[3],s[12],c[4]);

HA x8(sum[13],c[4],s[13],c[5]);

HA x9(sum[14],c[5],s[14],c[6]);

HA x10(sum[15],c[6],s[15],c[7]);

HA x11(sum[16],carry1,s[16],co);

endmodule

//RCA 8bit module

module ripplemod(a, b, cin, sum, cout);

input [07:0] a;

input [07:0] b;

input cin;

output [7:0]sum;

output cout;

wire[6:0] c;

fulladd a1(a[0],b[0],cin,sum[0],c[0]);

56

fulladd a2(a[1],b[1],c[0],sum[1],c[1]);






fulladd a8(a[7],b[7],c[6],sum[7],cout);

endmodule

//full addder module

module fulladd(a, b, cin, sum, cout);

input a;

input b;

input cin;

output sum;

output cout;

assign sum=(a^b^cin);

assign cout=((a&b)|(b&cin)|(a&cin));

endmodule

//HA module

module HA(a,b,s,c);

input a,b;

output s,c;

xor x12(s,a,b);

and x13(c,a,b);

endmodule

Appendix:F

Verilog Code for 4-bit Carry Skip Adder

module carryskipadder(A, B, X, CIN, COUT);

input [3:0]A, B;

input CIN;

output [3:0]X;

output COUT;

reg [3:0]X;

reg [2:0]base;

reg [2:0]ifzero;

reg [2:0]ifone;

57

reg COUT;

always @(A or B or CIN)

begin

base = A[1:0] + B[1:0] + {1'b0, CIN};

ifzero = A[3:2] + B[3:2];

ifone = A[3:2] + B[3:2] + 2'b01;

if(base[2])

begin

X = {ifone[1:0], base[1:0]};

COUT = ifone[2];

end

else

begin

X = {ifzero[1:0], base[1:0]};

COUT = ifzero[2];

end

end

endmodule


Verilog code for 8 bit csa :

module fulladd_p(a,b,carryin,sum,carryout,p);

input a, b, carryin; /* add these bits*/

output sum, carryout, p; /* results including propagate */

assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */

assign p = a | b;

endmodule

module carryskip(a,b,carryin,sum,carryout);

input [7:0] a, b; /* add these bits */

input carryin; /* carry in*/

output [7:0] sum; /* result */

output carryout;

wire [8:1] carry; /* transfers the carry between bits */

wire [7:0] p; /* propagate for each bit */

wire cs4; /* final carry for first group */

fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);

fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]);


http://image.slidesharecdn.com/report-13420353055909-phpapp01-120711143630-phpapp01/95/my-report-on-adders-22-728.jpg?cb=1342035447

58


assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin);

fulladd_p a4(a[4],b[4],cs4, sum[4],carry[5],p[4]);




assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4);

endmodule


module fulladd_p(a,b,carryin,sum,carryout,p);

input a, b, carryin; /* add these bits*/

output sum, carryout, p; /* results including propagate */

assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */

assign p = a | b;

endmodule

module carryskip(a,b,carryin,sum,carryout);

input [15:0] a, b; /* add these bits */

input carryin; /* carry in*/

output [15:0] sum; /* result */

output carryout;

wire [16:1] carry; /* transfers the carry between bits */

wire [15:0] p; /* propagate for each bit */

wire cs4,cs5,cs6,cs7; /* final carry for first group */

fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);




assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin);





assign cs5= carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4);


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assign cs6= carry[12] | (p[8] & p[9] & p[10] & p[11] & cs5);





assign carryout= carry[16] | (p[12] & p[13] & p[14] & p[15] & cs6);

endmodule

DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited

Documents

design of various adders

project deals

given project

carry value

adder rca

adder claa

adder csa

adder csla