R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003 DEPFET pixel sensor – concept and status DEPFET pixel sensor – concept and status » DEP(leted)F(ield)E(ffect)T(ransistor) operation principles » DEPFET prototype run » Simulation and design examples » Production status » Read out electronics and steering chips » Summary R.H. Richter a , L. Andricek a , P. Fischer b , G. Lutz a , I. Peric c , J. Treis a , M. Trimpl c , N. Wermes c a MPI Halbleiterlabor Munich b Univ. of Mannheim c Univ. of Bonn
DEPFET pixel sensor – concept and status. R.H. Richter a , L. Andricek a , P. Fischer b , G. Lutz a , I. Peric c , J. Treis a , M. Trimpl c , N. Wermes c a MPI Halbleiterlabor Munich b Univ. of Mannheim c Univ. of Bonn. DEP (leted) F (ield) E (ffect) T (ransistor) operation principles - PowerPoint PPT Presentation
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R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
DEPFET pixel sensor – concept and statusDEPFET pixel sensor – concept and status
A pixel size of ca. 20 x 20 µm² is achievable using 3µm minimum feature size.
Active Pixel Sensor (rectangular)
• 2 pixels
30 x 30 µm²
• DEPFET
L = 5 µm
W = 18 µm
reduce the required read out speed by 2doubles the number of read out channels
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Potential during collection - 3D Poisson equation (Poseidon)Potential during collection - 3D Poisson equation (Poseidon) (50µm thick Si, N (50µm thick Si, NBB=10=101313cmcm-3-3,V,VBackBack=-20V)=-20V)
Depth 10µmDepth 7µmDepth 4µmDepth 1µm
So
urce
sD
rain
External (internal) Gates
n+
cle
ar
con
tact
s
Cell size 36 x 27 µm²
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Current production statusCurrent production status
Pixel array section – design with clockable clear gatePixel array section – design with clockable clear gate
Done:
N-side with two polysilicon layers and contact openings
Backside processing
Aluminium Sputtering
To do:- 1st metal lithography (2 weeks)- First measurements- 2nd metal process
Drain Gate
Clear
Cleargate
Source
1 pixel cell
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
keep potential at input node constant (regulated cascode)
(signal+pedestal current) stored in current memory cell (inverting property)
pedestal current after reset subtracted automatically
signal value is stored in FIFO (analog part)
hit identification with current comparator and store hit pattern in FIFO (digital part)
FIFO is emptied row wise:
DEPFET provides current + fast readout neededcurrent based readout (see Vertex2002 proceedings)
• ‘hit finder’ identifies hits in a row and multiplexes (MUX) the appropriated currents to ADC (respective analogous outputs)
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Chip development for TESLAChip development for TESLA
TSMC 0.25µm, 5metal radiation tolerant design with annular nmos transistors contains: various current memory cells, hit finder, comparator size: 4 x 1.5 mm2
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Summary / scheduleSummary / scheduleo Key features: low noise, full bulk sensitivity, no charge transfer loss, low power
consumption, random access within an arrayo A new DEPFET technology (2 poly/ 2 aluminum) was developed for large arrays and
high speed operation.o A DEPFET prototype production has been started with DEPFET arrays
30 x 30 µm² pixel size. o First measurements in 2 weekso Read out electronics first test chip successfully tested (50MHz operation possible) o 128 channel read out chip (2.0) currently in design, submission this month, chip
delivery in summero Steering chip for Gate and Clear access successfully fabricated
(first tests very encouraging) o Complete prototype system ready by end of the year
Further plans
In 2004: Design and production of large arrays
Some wafer on SOI (thinned technology) ?
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Back up transparenciesBack up transparencies
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Problems with demolished polysilicon lines and bad polyI/polyII insulation
Solved now
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Self aligning TechnologySelf aligning Technology
Positions of all essential implantations are determined not by masks but by polysilicon layers
shallow channel implantation
- mandatory for rectangular cells (lateral channel definition)
- reduces parameter variations on the wafer
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Hiding the nHiding the n++-clear contacts-clear contacts
Depth 1µm
The positive Clear pulse removes the electrons from the Internal Gate and also pushs the holesout of the deep p cover region. After returning of theclear the deep p remains negatively charges forminga shield for the signal electrons.
TeSCA (2D, time dependent)Removal of 1600 electrons from the internal gate (VClear=15V)
Simulation of the Clear mechanism
Poseidon (3D Poisson equ.)Includes 3D effects => VClear=20V
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Pixel prototype production (6“ wafer)Pixel prototype production (6“ wafer)for XEUS and LC (TESLA)for XEUS and LC (TESLA)
Many test arrays- Circular and linear DEPFETS up to 128 x 128 pixels minimum pixel size about 30 x 30 µm² - variety of special test structures
Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors