Defect-tolerant FPGA Defect-tolerant FPGA Switch Block and Switch Block and Connection Block with Connection Block with Fine-grain Redundancy for Fine-grain Redundancy for Yield Enhancement Yield Enhancement Anthony J. Yu Anthony J. Yu Guy G.F. Guy G.F. Lemieux Lemieux August 25, 2005 August 25, 2005
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Defect-tolerant FPGA Switch Block and Connection Block with Fine- grain Redundancy for Yield Enhancement Anthony J. YuGuy G.F. Lemieux August 25, 2005.
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Defect-tolerant FPGA Switch Block Defect-tolerant FPGA Switch Block and Connection Block with Fine-and Connection Block with Fine-
grain Redundancy for Yield grain Redundancy for Yield EnhancementEnhancement
Anthony J. YuAnthony J. Yu Guy G.F. LemieuxGuy G.F. Lemieux
August 25, 2005August 25, 2005
FPL'05 - PresentationFPL'05 - Presentation 22
OutlineOutline
Introduction and MotivationIntroduction and Motivation
Previous ApproachesPrevious Approaches
Fine-grain RedundancyFine-grain Redundancy
ResultsResults
ConclusionsConclusions
FPL'05 - PresentationFPL'05 - Presentation 33
Introduction and MotivationIntroduction and Motivation
Scaling introduces new Scaling introduces new types of defectstypes of defectsNumber of defects Number of defects expected to increase as expected to increase as chip density increaseschip density increases– As a result, chip yield is on As a result, chip yield is on
the declinethe decline
FPGAs are mostly FPGAs are mostly interconnectinterconnect
To improve yield (and To improve yield (and revenue), we must revenue), we must tolerate multiple tolerate multiple interconnect defectsinterconnect defects
FPL'05 - PresentationFPL'05 - Presentation 44
Previous ApproachesPrevious Approaches
Defect-tolerance is one method to Defect-tolerance is one method to minimize impact of manufacturing defectsminimize impact of manufacturing defectsTwo approaches taken by industry: avoid Two approaches taken by industry: avoid the defective resources (Xilinx EasyPath) the defective resources (Xilinx EasyPath) or make the defective resources or make the defective resources inaccessible (Altera)inaccessible (Altera)Past attempts either did not scale well, Past attempts either did not scale well, required too much reprogramming time or required too much reprogramming time or affected signal timingaffected signal timing
FPL'05 - PresentationFPL'05 - Presentation 55
ObjectiveObjective
ProblemProblem– FPGA yield is on decline because of FPGA yield is on decline because of
Defect Avoidance - Example 1Defect Avoidance - Example 1
FPL'05 - PresentationFPL'05 - Presentation 1313
Defect Avoidance - Example 2Defect Avoidance - Example 2
FPL'05 - PresentationFPL'05 - Presentation 1414
ResultsResults
AreaArea
DelayDelay
Area Delay ProductArea Delay Product
YieldYield
SummarySummary
FPL'05 - PresentationFPL'05 - Presentation 1515
Area ResultsArea Results
FPL'05 - PresentationFPL'05 - Presentation 1616
Delay ResultsDelay Results
FPL'05 - PresentationFPL'05 - Presentation 1717
Area-Delay ProductArea-Delay Product
FPL'05 - PresentationFPL'05 - Presentation 1818
Yield - 1Yield - 1
* Assumes all bridging defects
FPL'05 - PresentationFPL'05 - Presentation 1919
Yield - 2Yield - 2
FPL'05 - PresentationFPL'05 - Presentation 2020
SummarySummary
FPL'05 - PresentationFPL'05 - Presentation 2121
ConclusionConclusion
FGR meets desired objectives:FGR meets desired objectives:– Tolerates Tolerates multiplemultiple randomly distributed defects randomly distributed defects– Defect correction Defect correction does not perturb timingdoes not perturb timing– Tolerates an Tolerates an increasing numberincreasing number of defects as array of defects as array
size increasessize increases– Correction can be applied Correction can be applied quicklyquickly
FGR has different implementation optionsFGR has different implementation options– Trade-offs between yield, area and delay can be Trade-offs between yield, area and delay can be