Defect Tolerance Defect Tolerance for for Yield Enhancement Yield Enhancement of of FPGA Interconnect FPGA Interconnect Using Fine-grain and Using Fine-grain and Coarse-grain Redundancy Coarse-grain Redundancy Anthony J. Yu Anthony J. Yu Guy G.F. Guy G.F. Lemieux Lemieux September 15, 2005 September 15, 2005
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Defect Tolerance for Yield Enhancement of FPGA Interconnect Using Fine-grain and Coarse-grain Redundancy Anthony J. YuGuy G.F. Lemieux September 15, 2005.
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Defect ToleranceDefect Tolerancefor for Yield EnhancementYield Enhancementof of FPGA InterconnectFPGA InterconnectUsing Fine-grain and Using Fine-grain and
Coarse-grain RedundancyCoarse-grain RedundancyAnthony J. YuAnthony J. Yu Guy G.F. LemieuxGuy G.F. Lemieux
September 15, 2005September 15, 2005
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OutlineOutline
Introduction and motivationIntroduction and motivation Previous worksPrevious works New architecturesNew architectures
Introduction and Introduction and MotivationMotivation
Scaling introduces Scaling introduces new new typestypes of defectsof defects
Smaller feature sizes Smaller feature sizes susceptible to susceptible to smaller smaller defectsdefects
Expected resultsExpected results Defects per chip increasesDefects per chip increases Chip yield declinesChip yield declines
FPGAs are mostly FPGAs are mostly interconnectinterconnect
FPGAs must tolerate FPGAs must tolerate multiple interconnect multiple interconnect defectsdefects to improve yield to improve yield (and $$$)(and $$$)
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General Defect Tolerant General Defect Tolerant TechniquesTechniques
Defect-tolerant techniques minimize Defect-tolerant techniques minimize impact (cost) of manufacturing defectsimpact (cost) of manufacturing defects
FPGA defect-tolerance can be loosely FPGA defect-tolerance can be loosely categorized into three classes:categorized into three classes: Software Redundancy – use CAD tools to map Software Redundancy – use CAD tools to map
around the defectsaround the defects Hardware Redundancy – incorporate spare Hardware Redundancy – incorporate spare
resources to assist in defect correction (eg. resources to assist in defect correction (eg. Spare row/column)Spare row/column)
Run-time Redundancy – protection against Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)transient faults such as SEUs (eg. TMR)
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Previous work – 1 – XilinxPrevious work – 1 – Xilinx Xilinx’s Defect-Tolerant ApproachXilinx’s Defect-Tolerant Approach
Customer (knowingly) purchases “less that perfect” Customer (knowingly) purchases “less that perfect” partsparts
Customer gives Xilinx configuration bitstreamCustomer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstreamXilinx tests FPGA devices against bitstream
Sells FPGA parts that “appear” perfectSells FPGA parts that “appear” perfect Defects avoid the bitstreamDefects avoid the bitstream
Limitation:Limitation: Chips work only with given bitstream – no changes!Chips work only with given bitstream – no changes!
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Previous work – 2 – Previous work – 2 – AlteraAltera
Yield for Varying Wire Yield for Varying Wire LengthLength
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Limitations of Study & Limitations of Study & ArchitecturesArchitectures
FGRFGR Does not tolerate defects in the logicDoes not tolerate defects in the logic Cannot tolerate clustered defectsCannot tolerate clustered defects Requires a detailed fault mapRequires a detailed fault map
CGRCGR Assumes that all defects can be Assumes that all defects can be
corrected with a single row/columncorrected with a single row/column Bypass circuitry is approximatedBypass circuitry is approximated
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Summary of FGRSummary of FGR
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ConclusionsConclusions CGR CGR is effective for 1 or 2 defects effective for 1 or 2 defects FGR meets desired objectives:FGR meets desired objectives:
Defect correction Defect correction does not perturb timingdoes not perturb timing Tolerates an Tolerates an increasing numberincreasing number of defects of defects
as array size increasesas array size increases Correction can be applied Correction can be applied quicklyquickly
FGR potentially capable of FGR potentially capable of correcting correcting crosstalkcrosstalk faults, but has not been faults, but has not been exploredexplored