Data link control line control unit LCU

Data Link Control Line Control Unit LCU

Parallel data transfer

✓Signaling elements sent down the line all 8 bits at a time.

✓One clock loads 8 bits. ✓8 times faster than serial transmission. ✓Data available to PC in desired form. ✓Best suitable for internal BUS. ✓Requires much larger cabling infrastructure.(One wire per

bit)

✓Can not be used for longer distances as delay in each wire may be different.

Serial data transfer

✓Signaling elements sent down the line one at a time. ✓One clock loads one symbol.

✓Each signaling element may be ✓ Less than a bit – Manchester code ✓ One bit long -- NRZ-L, FSK, etc.. ✓ More than a bit – QPSK.

✓Requires much lesser cabling. ✓Can be used for longer distances. ✓Slower than parallel transmission. ✓Synchronization is a critical issue.

Serial data transfer

✓Receiver should recognize beginning and end of bit stream and each bit duration.

✓If Transmitter and Receiver are not synchronized, bits sampled would be erroneous.

✓Error may not occur immediately but will occur later due to cumulative effect.

Serial data transfer-- Example

✓Tr rate is 10,000 bits/ s. ✓Bit time T = 0.1ms ✓Bits sampled at mid-bit time = 0.05ms away from both ends.

!!!!

✓Receiver clock faster or slower by 1%. ✓Each pulse will be sampled at a cumulative of 0.001ms. ✓After how many bits, it would be samples at the edge of the bit? ✓50 bits. ✓51st bit sampled will be the adjacent bit – error. ✓Larger the CLK difference, earlier the error.

0.1ms

0.05ms

Asynchronous Transmission

✓Data sent one character at a time. ✓Data can be 5 to 8 bits in length.

!!!!

✓Receiver resynchronizes with each character. ✓Larger difference in CLK of TR and REC can also be

accommodated as only 8 bits max transmitted together. How much ?

✓Receiver alerted with a start bit.

Asynchronous Transmission

!!!!!!!

✓Idle ‘1’ is negative voltage and ‘0’ is positive voltage. ✓Receiver is activated with one bit start bit i.e. positive pulse. ✓Followed by 5 to 8 data bits and one bit parity. ✓Frame ends with 1 to 2 stop bits – idle 1’s. ✓New character will have a new start bit.

START

BITOne character

P STOP

BITs

0

1

Asynchronous Transmission

✓ADVANTAGES: ✓Simple and cheap. ✓Resynchronizes at every start bit. ✓Very good for low speed transmission. ✓Example: PC connected to real time terminal where operator feeds

manually. ✓DISADVANTAGES: ✓2 to 3 bits overhead per character(25%). ✓Additional gap between words.

Synchronous Transmission

✓Blocks of characters or bits transmitted without start or stop bits. ✓REC synchronizes with either separate clocking line or clocking info

embedded in data. ✓Pre-amble and post-amble bits sent at beginning and end

respectively for synchronization. ✓TYPES:

✓ Character oriented transmission ✓ Bit oriented transmission

Character Oriented Synchronous Transmission

!!!!!

✓Data and control information both in character form. ✓Individual bits have no meaning, except in character form. ✓SYNC are predetermined unique bit pattern in character form for

synchronization of Rec. ✓Post amble can be avoided by stating length of data. ✓Overheads are very less as large chunk of data can be sent with

one set of headers.

Other control information

S Y N

S Y N

S Y N

S Y N

DATAPreamble Post ambleAddress

Bit Oriented Synchronous Transmission

!!!!!

✓Data and control information both in bit form. ✓Every bit has a definition. ✓Overheads are very less as large chunk of data can be sent with

one set of headers.

Control Field

FL AG

…FL AG

DATA8 bit flag 8 bit flagAddress CRC

Line Control Unit LCU

✓PC is Data Terminal Equipment DTE. ✓DTE feeds Data Communication Equipment DCE. (MODEM). ✓DTE gives parallel data, which needs to be carried to DCE as serial

data. ✓LCU converts parallel data to serial data. ✓TYPES:

✓ UART Universal Asynchronous Receiver/Transmitter. ✓ USRT Universal Synchronous Receiver/Transmitter.

UART Universal Asynchronous Receiver/Transmitter

✓Used to transmit asynchronous data format without clocking information.

✓FUNCTIONS: ✓Performs parallel to serial and serial to parallel conversion at

Transmitter and Receiver respectively. ✓Perform error detection by inserting and checking parity bits at

Transmitter and Receiver respectively. ✓Inserts and detects start and stop bits at Transmitter and Receiver

respectively. ✓Uses a control word to accommodate options for parity, data and

stop bits. ✓Control word must be programmed into UART control register prior

to transmission.

UART Control Word

✓START Bit: Always a single bit ‘0’, +ve voltage. No other option. ✓Number of Parity Bit NPB:

✓ NPB ‘1’ = No parity bit used.(RPE disable) ✓ NPB ‘0’ = One Parity bits used

✓ EVEN or ODD Parity POE: ✓ POE ‘1’ = Even Parity ✓ POE ‘0’ = ODD Parity

✓ Number of STOP Bits NSB ✓ NSB ‘1’ = 2 stop bits ✓ NSB ‘0’ = 1 stop bits

UART Control Word

✓Number of DATA Bit NDB1, NDB2:

!!!!!!!

✓If NDB2-NDB1 is 11 and NSB is 1 then: ✓ NSB = 1.5

NDB2 NDB1 Bits/word

0 0 1 1

0 1 0 1

5 6 7 8

UART Transmitter

Transmit Buffer Register

TD7 TD8TD5 TD6TD7 TD4 TD9 TD0

TDS

Control Register

NPB NSB NDB1 NDB2

CS

Parity Generator

Data bits, Parity bits, Stop bits Steering Logic Circuit

O/P Ckt

Buffer Empty Logic Circuit

TEOC

Timing Generator

TCP

Status Word RegisterSWE

TBMT

TSOStart Bit

UART Transmitter

✓UART sends TBMT, a transmit Buffer Empty signal to DTE to indicate it is ready to receive data.

✓Sensing an active TBMT, DTE sends parallel data character to transmit data lines (TD0 - TD7).

✓It strobes them into Transmit Buffer Register using Transmit Data Strobe signal and TBMT becomes low.

✓Contents of Transmit Buffer Register are transferred to Transmit shift Register when TEOC, Transmit End of Character, goes active to indicate Transmit Shift Register is empty.

✓Parity generator generates parity as per data bits. ✓Data passes through steering logic circuit and picks Start, Stop and

Parity bits as decided by Control Word in Control Register. ✓Complete word is now serially outputted on the Transmit Serial

Output TSO pin with bit rate equal to Transmit Clock frequency TCP. ✓At end of last bit, it activates TEOC.

UART Transmitter

✓When data shifts from Transfer Buffer Register to Transmit Shift Register, Buffer Empty Logic Circuit updates Status word register to activate TBMT.

✓Active TBMT signals DTE to load new word on Buffer Register. ✓ It will wait for active TEOC when last serial bit goes out and moves

to shift register. ✓Process continues.

UART Transmitter Timing Diagram

Word 2 Word 3 Word 4Word 1TSO

TEOC

TDS

TBMT

UART Receiver

Receive Shift Register

Receive Buffer Register

Status Word Register

Receive Timing Circuit

Control Register

Parity Checker

Start Bit Verify

RSI

RCP

RD7 RD0

RPERDAR

RFE RDA RORSWE

RDE

RSI – Receive serial input RCP – Receive clock pulse RPE – Receive parity error RFE – Receive flag error ROE – Receive overrun RDA – Receive data available SWE – Status word enable RDAR – Receive data available reset

UART Receiver

✓ Control word defining number of stop bits, data bits and parity information is same as used for transmitter.

✓ UART receiver ignores idle time 1s. ✓ When valid start bit is detected by start bit verification circuit, data

character is serially clocked in to Receive Shift Register. ✓ If parity is used, the parity bit is checked in Parity Check Circuit. ✓ After full data character is loaded in shift register, character is

parallel loaded into Receive Buffer Register. ✓ Receive Data Available (RDA) flag is set in Status Word Register. ✓ DTE monitors Status Word Register through Status Word Enable

SWE’. ✓ When RDA goes high, it reads character from Receive Buffer

Register using Receive Data Enable RDE’. ✓ DTE then activated RDAR’, Receive Data Available Reset, which

resets RDA pin. ✓ Process continues…

UART Receiver

✓ Status Word Register also used for diagnostic information. ✓ Receive Parity Error, RPE flag is set when received character has

parity error. ✓ Receive Framing Error RFE flag is set when the character is

received with improper number of stop bits. ✓ Receive Overrun, ROR flag is set when character in buffer is

overwritten by another character as DTE fails to check RDA and download bits.

✓ Receive Clock for UART (RCP) is 16 times higher than receive data rate.

✓ This allows start bit verification circuit to identify valid high-to-low transition from among negative going noise spikes.

Start Bit Verification

✓ Once a low is detected, verification circuit counts-off 7 clock pulses and samples the line.

✓ If found still low, it is a valid start bit as noise spike will not hold that long.

✓ If found high, it was a noise spike. ✓ Once a valid start bit received, verification circuit samples

incoming bits once every 16 clock cycle.

UART Receiver Timing Diagram

WORD 1 WORD 2 WORD 3RSI

STATUS STATUS

RDA

RPE, RFE, ROR

SWE

RDE

RDAR

USRT Universal Synchronous Receiver/Transmitter

✓Used to transmit synchronous data format with clocking information.

✓FUNCTIONS: ✓Performs parallel to serial and serial to parallel conversion at

Transmitter and Receiver respectively. ✓Perform error detection by inserting and checking parity bits at

Transmitter and Receiver respectively. ✓Inserts and detects sync characters at Transmitter and Receiver

respectively. ✓Uses a control word to accommodate options for parity and data

bits. ✓Control word must be programmed into USRT control register prior

to transmission. ✓Control word same as UART except for stop bits.

USRT Transmitter

Data Bus

DB0DB1DB7 DB6 DB5 DB4 DB3 DB2

Transmit Data Register Transmit Sync RegisterTSS

Timing and Control

Transmit

!!Control Register

TCP

TDS

TBMT

SCT

NDB1

CS

NDB2

POE

NPB

Multiplexer

Transmit Shift Register TSO

USRT Transmitter

✓Transmit clock signal (TCP) is set at desired bit rate. ✓Desired SYNC character is loaded from parallel input pins (DB0-DB7)

into Transmit Sync Register by Transmit Sync Strobe TSS. ✓Data are loaded into Transmit Data Register from parallel input pins

(DB0-DB7) using Transmit Data Strobe TDS. ✓NEXT character is extracted from Transmit Data Register if TDS pulse

occurs during presently transmitted character. ✓Otherwise NEXT character is extracted from Transmit SYN Register

and SYN Character Transmitted flag (SCT) is set. ✓Transmit Buffer Empty TBMT signal is used to request next character

from DTE. ✓Serial output data appears on Transmit Serial Output TSO pin. ✓Control Register stores Control word containing number of data and

parity bits per word and type of parity. ✓CS selects the USART only when active low. CS high does not mean

standby, but means not selected that time.

USRT Receiver

! !Timing

and Control Receive

RR

RCP

SCR

RPE

ROR

RDA

RDAR

RSI

Receive Shift Register

Receive Sync Register

Comparator

Receive Buffer RegisterRDE

USRT Receiver

✓The Receive Clock signal (RCP) is set at desired bit rate. ✓Desired SYN character is preloaded into Receive Sync Register

through (DB0-DB7) using Receive SYN Strobe RSS. ✓On high-to-low transition of Receive Rest input (RR) in Timing and

Control Receive, receiver is placed into bitwise search mode - ✓to examine serially received data bit-by-bit for SYN character.

✓Data is loaded into Receive Shift Register bitwise through RSI, Receive Serial Input.

✓Comparator compares contents of Receive Shift Register with contents of Receive SYN Register.

✓On receiving SYN, SYN Character Receive (SCR) output is set. ✓SYN character is transferred to Receive Buffer Register and

receiver is placed in character mode. ✓Received next data is received bitwise but examined in character

mode and RDA is set.

USRT Receiver

✓Received data is checked for receiver overrun or receive parity error and respective flags ROR or RPE are set if found with problems.

✓All control signals SCR, RDA, ROR, RPE are available in Status Word Register.

✓Correct data is outputted to DTE through pins (DB0-DB7) using Receive Data Enable strobe RDE.

✓Receive Data Available Reset RDAR is set to reset RDA pin.