Design and Evaluation of a Data-Dependent Low-Power 8x8 DCT/IDCT Cheng-Yu Pai A Thesis in The Department of Eiectrical and Computer Engineering Presented in Partial Fulfillrnents of the Requirement for the Degree of Master of Applied Science (Electrical) at Concordia University Montreal, Quebec, Canada December 2000 O Cheng-Yu Pai, 2000
122
Embed
Data-Dependent Low-Power 8x8 DCT/IDCT · 2005-02-09 · Design and Evaluation of a Data-Dependent Low-Power 8x8 DCT/IDCT Cheng-Yu ai' Traditional fast Discrete Cosine Transforrn @CT)/hverse
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Design and Evaluation of a
Data-Dependent Low-Power 8x8 DCT/IDCT
Cheng-Yu Pai
A Thesis
in
The Department
of
Eiectrical and Computer Engineering
Presented in Partial Fulfillrnents of the Requirement
for the Degree of Master of Applied Science (Electrical) at
Concordia University
Montreal, Quebec, Canada
December 2000
O Cheng-Yu Pai, 2000
National Library I*l ,,,a Bibliothèque nationale du Canada
Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 395 Wellington Street 395. rue Wellington Ottawa ON KlA ON4 Ottawa ON K I A O N 4 Canada Canada
The author has granted a non- exclusive licence allowing the National Librq of Canada to reproduce, loaq distribute or sell copies of this thesis in microfom, paper or electronic formats.
The author retains ownership of the copyright in this thesis. Neither the thesis nor substantial extracts fÎom it may be printed or otherwise reproduced without the author's pemiission.
Yowfile Votre réfd~(yso~
Our fi& Notre dtdr~nte
L'auteur a accordé une licence non exclusive permettant à la Bibliotheque nationale du Canada de reproduire, prêter, distribuer ou vendre des copies de cette thèse sous la forme de microfiche/fïJm, de reproduction sur papier ou sur format électronique.
L'auteur conserve la propriété du droit d'auteur qui protège cette thése. Ni la thèse ni des extraits substantiels de celle-ci ne doivent être h p h e s ou autrement reproduits sans son autorisation.
Design and Evaluation of a
Data-Dependent Low-Power 8 x 8 DCT/IDCT
Cheng-Yu ai'
Traditional fast Discrete Cosine Transforrn @CT)/hverse DCT (DCT)
algorithms have focused on reducing arithmetic complexity and have fixed m - t h e
cornplexities regardless of the input. Recently, data-dependent signal processing has been
applied to the DCT/IDCT. These algorithms have variable nui - the complexities.
A new two-dimensional 8x8 low-power DCTIIDCT design is implemented using
VHDL by applying the data-dependent signal-processing concept ont0 the traditional
fixed-complexity fast DCTADCT algorithm. To reduce power, the design is based on
Loeffler's fast a lgori th, which uses a low number of multipIications. On top of bat,
zero bypassing, data segmentation, input tnuication, and hardwired canonical sign-digit
(CSD) multipliers are used to reduce the run-time computation, hence reduce the
switching activities and ths power.
When synthesized using Canadian MicroeIectronic Corporation 3-V 0.35 pn
CMOSP technology, this FDCTlIDCT design consumes 122.7i124.9 mW with dock
fiequency of 40MHz and processing rate of 32OM sample/sec. With technology scaling
to 0.35 pm technology, the proposed design features lobver switching capacitance per
' This work is supported by National Sciences and Engineering Research Council of Canada (È4iSERC) post-graduate
scholarship. and NSERC rescarch grants
sample. i.e. more power-e fficient, than other previously reported hi&-performance
I would l k e to express rny deepest and most sincere gratitude toward my
supenisors - Dr. Asim 5. Al-Khalili and Dr. William E. Lynch. They have given me
clear and helpful guidelines throughout my years as a master student. Above dl, I wish to
rhank them for the geat amount of time devoted to me and my work.
1 wish to th& die scholarship offered by the National Sciences and EngÏneering
Research Council of Canada (NSERC) Post-Graduate Scholarship (PGS-A), and NSERC
research gants. Their financial support allows me concentrating my tirne and effort on
my research.
1 would also like to thank my fellow fnends Wassim Tout, Wei Wang, and VLSI
lab specialist Ted Obuchowicz for helping me throughout the technical problems with the
simulation environnlenrs. and givïng me their valuable opinions about the cornparison
strate,^.
Finally, 1 would like to dedicate this work to my family for their love and support.
I rhank you all for your patience and your sacrifices. This work is as much yows as it is
mine.
Table of Contents
List of Figures ................ ................. ................................................... ix List of TabIes ................................................................................................. x
List of Acronyrns .......................................................................................... xi
[28] Xanthopoulos, "Low pou7er data-dependent transform video and still image
coding", Ph. D. Thesis, M. 1. T., February 1999.
[29] E. Feing and S. Winograd? "Fast algorithms for the discrete cosine transform7',
IEEE trans. on signal processing, 40(9), pp. 2 174-2 193, September 1992.
K. Hwang? Cornpziter Arirhmetic - Principles. Architecfzrre, and Design, John
Wiley Br Songs, 1979, pp. 149-151.
Z. Wang, "Fast Algorithrns for Discrete W-Transfomi and for the Discrete Fourier
Transform", E E E trans. on acoustics, speech and signal processing, vol. ASSP-32,
no. 4, pp. 803-8 16, Aupst 1984.
M. Vetterli, W. Nussbaumer, "Simple FFT and DCT Algorithms with Reduced
Number of Operations", Sipal Processing (North Holland), vol. 6. no. 4, pp. 264-
275. August 1954
N. Suehiro, M. Hatori. "Fast algorithms for the DFT and other Sinusoida1
Transforms", IEEE Trans. on acoustics, speech, and signal processing, vol. ASSP-
34. no. 3, pp. 642-664, June 1986
P. Duhamel and H. H'Mida, "New 2" DCT algorithms suitable for VLSI
implemcntation", Proceedings IEEE international conference on acoustics, speech
and sienai C processing, ICASSP-85, Dallas, pp. 1805-1 808, April 1987
K. Swang, pp. 152-1 55
S. Shah. A. J. Al-Khalili, and D. Al-Khalili, Tomparison of 32-bit multipliers of
various performance rncasures", Proceedings of the 12" international Conference
on Microelectronics, ICb1'2000, pp. 75-80, October 3 1- November 2,2000
A. Bhattacharya and S. Haider, "A VLSI implementation of the inverse cosine
transforrn, International J. of Pattern R e c ~ ~ p i t i o n and AI, 9(2), pp. 303-3 14, 1995
K. R. Rao and P. Yip, Discrete Cosine Tt-ansform - Algorithrns, Advantages,
Applications, Academic Press, 1990, pp. 10- 1 5
[39] V. Lefèvre? "Multiplication by an integer constanty7, LIP research report RR1999-
06, Laboratoire d'Informatique du Parallélisme, Lyon, France, 1999
[LCO] F. de Dinechine and V. Lefevre, "Constant MultipKers for FPGAs", LIP research
report W 0 0 0 - 1 8, Laboratoire d'Informatique du Parallélisme, Lyon, France, 2000
[4 11 R. Bernstein, Multiplication by integer constants, Software - Practice and
Expenence, 16(7), Juiy 1956, pp. 641-652
[42] M. Potkonjak, M- Snvastava, and A. Chandrakasan, "Multiple Constant
Multiplications: Efficient and Versatile Frameworks for Exploring Common
Subexpression Elimination": IEEE Trans. on CAD of IC and Systems, vol. 15, no.
2, pp. 151-165, February 1996
[433 Xilinx Cooperation, "Constant (k) Coefficient Multiplier Generator for Virtex",
Application Note, Version 1.1, Mach 12, 1999
1441 Xilim Cooperation, "Constant Coefficient Multipliers for XC3000E", Application
Note XAPP 054, Version 1-1, December 1 1, 1996
[4>3 R Hartley. "Optimization of Canonical Sign Digit Multipliers for Filter Design",
IEEE International Sympoisum on Circuits and Systems, 1991, vol. 4, 1992-1995,
1991
Appendix A
Truncation Test Result
Table 17 shows the truncation erïor of 3 test video sequences: coke, salesman,
and tennis. The truncation error is defined as:
Tuca t ion Error = Average PSNR(reference) - Average PSNR(tnuication)
Each sequence is encoded with pure 1-hunes, 8 Mb/s and 180 frames. The FDCT
is computed with fixed-point calculation with 1 1-bit precision after binary points.
Truncation Error = Average PSNR(reference1- Average PSNR(truncation1
Average of 3 Sequences (dB;
-- -
TNnc(2tn) Numker of
Truncated Bit Tennis Coke Saiesmar
(dB) (dB) (dB)
Table 17: Truncation errors of test sequences: coke, salesman, and tennis
a r ch i t e c tu r e S t ruczu rz l o f COS-3-16 Fs component HalfAdder
port (A, 9: i2 Std-Loqic; S m , Cout: out Std-Logic) ; end componenz ;
cornuone3r FullAdcer O , , c i : i 3cd-Logit; Sum, Cocr: ou t Szd-Logic);
ena component;
s i g n o l S û r CO, SI, C i , s 2 , C 2 , 5 3 , C 1 : Srci-Logic-Vector (25 downto O ) ;
s igna l n-m : Std - LoqFc-Vector (25 downto O ) ; s i g n a l ZEXO: Std-Logic; -- cons tan^ s i g n a l ' O ' s i gnc i ONE : Stc-Logic; -- Cozstan t s i g n a l '1'
ZE8O <= ' 0 ' ; ONE <= '1';
-- I n ~ e r t e à i n p u t siqnals: N <= nor P;
-- a i r O Srage 9: -- B i t O Stage 1:
-- B i t O Stage 2: -- B i = O Çcoge 3:
-- B i t 1 Stage O:
ïiA - 0-1: XalfAdder 3 0 x rnac (N ( I l ,N ( -- B i t L Scaqe 1: -- B i t I Sïaçe 2: -- Biz I Srage 3 :
-- Sic 2 Stzge O: -- E i t 2 Stage 1:
HA-1-2: HalfAdder porc map (N ( 2 , CO -- Bi= 2 Scage 2: -- a i t 2 Stage 3 :
-- E i t 3 Stage O: 34-0-3: FuilAdder p o r t map(N( 3),N(
-- B i t 3 Stage 1: -- a i z 3 Stage 2:
Ka--2-3: Holr'P-dder porz rnaplSO( 3 ) , C I ( 23,S2( 3),C2( 3 ) ) ; -- B i t 3 Stage 3:
-- B i r 4 Stzge O : -- Bit 4 Stage 1:
FP--I-?: FullAdder p o r t map(N( 4),A;I( l),CO( 3),Si( 4),CI( 4 ) ) ; -- B i t 4 S t a g e 2 : -- B i t 4 stage 3:
m-3-4: H a l f A d d e r porc ~ p ( S l ( 4) ,C2( 3),S3( 4),C3( 4));
-- Sic 6 S c a q e O : E3--0-6: FullS.dder port rnap(bJ( 61, NI 3 ) , 1 ( C),SO( CO( 6));
-- B i c 6 Stage 1: -- Biz 6 S t a g e 2 : -- B i t 6 S t e g e 3:
-- Sic 7 Sz+çe O : FA-C-7: Fü1IAdcier p o r t - p ( N ( 7 ) , Y f 4)r?1 I),SO( ?),CO( 7 ) ) ;
-- S i r 7 S c a g e 1: -- Bit 7 S t a g e 2: -- Bit 7 S c a g e 3:
-- B i t I I S t a q e O : Fr? - 0-11: F t r l l A d c i e r p o r c .nap(N(LI),N( a ) , P ( 5),S0(11),C0(11)1;
-- E i c II Scage 1: FA - 1-11: F u l l A d d e r porz mâp(P( ~ ) , S O ( I ~ ) , C O ( I O ) , S I ( ~ ~ ) , C ~ ( ~ ~ ) ) ;
-- Bit 11 Sracre 2:
-- Bic 1 3 Stage O: FA O 13: FullAdder p 0 r . L r n a p ( N ( l O ) , P ( 7 ) , P ( 5),~0(13),~0(13));
-- Bit 20 Stage 1:
FA-1-20: FullAdder porc nzp( ONE ,SO(20) ,CO(19) ,S1{20) ,CI (20) ) ; -- B i t 20 Stâge 2:
-- Bit 23 Scage O : FA - 0-23: FullAaaer porc nap(N(ll), P( 91 , ONE ,SO (23) ,CO (23) ) ;
-- Bir 23 Szage 1: m-1-23: E~lZAdder ?art map(SO(23),CO(22},S1(23),C1(23));
-- B i t 23 Stage 2: -- Six 23 Sxage 3:
-- B i = 21 Scaqe O: -- 3ic 24 S t q e 1:
Fi-1-24: EalfAdcier port nap[P(IO) ,C0(23; ,SI ( 2 4 ; , CIi241 ! ; -- 3it 24 Szage 2: -- a i t 2 4 Stage 3 :
end;
-- Statistical Info-macion: A d Stage : 4 -- K Inverter : 12 -- # E a l f adaerr 13 -- t Fu11 adcer: 4 8
Appendix C
Source Code of Constant Multiplier Generator
The following is the C++ source code listing for constant multiplier generator.
The codes are listed in arphabetic order of the source file name. The header file (.h) is
aiways in fiont of the implementation file (.cpp). The main program is located inside n l e
IntMrkcpp. Notice tbat al1 codes are also included in the attached CD.
using naneSpace s t d ;
ucs igned nXezcyAïStzge(SignalVector& imï, int curSïage);
void gecAdderOperana (znsigced n O p , msigned r n a x C o n s t I n p u t , S i g n a l V e c t o r & i m t ,
void createE? {vec=cr<Sig?.aItJector> & k t , unsigned xnsignea m a x C o n s t O p , oscreemb 0 ) ; voia c r e ~ t e ? ~ (vêctcr<SiqnaItiector> S i m r , umigned xnsianed nzxCanscC~, oscrsam& G ) ;
curBiz , unsigned curstaqe,
c u r B i t , u n s i g n e d c u r s t a g e ,
voici genprate-VHDI, - CSA - Eody(vec~or<ÇignalVec~sr> &imt, unsignea CSA-Scage, u r r s i g c e c & n H â l f A d d e r , unsigned a c F u l l A c d e r , ostrem& csa) ;
using nomespace std; I sca t i c S i g n a l
SIGNAL_SU?.I (VARIABLE,"S",SUM ,false,NONE,-1,-11, S I G N ~ C P ~ Y (V.UI.ABLE, "Cm , CPRRY, fafse, NONE, -1, -1 1 ,
boof -HA - for-2op = c rue ; 5001 i sF i r s tAdder ; Fnt ~Xeady; for (i=O; i<sv.size ( ) ; i + - 1 I csa << "\n"; FsFirstAdder = Erne;
f o r ( j = O ; j<CÇk-Sccge; j +-)
I cça << "-- Bit "<<i<<" Stage "<<j<<" : \n"; if (,U,-for_20pI { switch (nSeadyAtStage (SV [ il , j 1 1 I czse 0: nreak; case 1: break; case 2: (
if (sv[i],sizeO==2)
creace-FIA (SV, i, j, (isFirstAeder?2: 1) , csa) ; if (j==CSA-Stage-l) KA-for-2op=false; isFirstAdder=false; nHalfAdder++;
1 break;
1 default : ! creaceFL(sv, i, j , f isFirstAddez?3 : 1) , csz) ; if ( j ==CS-S tage-1) F-a- - ffor_2op=false; isFirstAdaer=false; nFuL1Accierit;
i t
I else / / L-A-for-20p = false I nReaay = nRe~cy~tStaçe (svii], j 1 ; . - r r (sv[il -size O ==3) i L
If (nReâdy==2 1 1 riReady==3 1 I createw-(SV, i, j , (isPirsSidder?2: I), csa) ; isFirstAdder = false; nXalZAader+i;
I i else if (nRêady>=3 1 I creaïeFA (SV, F , j , (isFirsiAader?3 : l) , csa) ; isFFrstAdder = folse; nFullAddec+t;
i 1
1 i
1
void s i ~ ~ l i f ~ ~ o n s ~ ~ n r s ( v e c t o r ~ S i g ~ a f V e c ~ o ~ ~ &c) I SipaiVecrcr: : i ï e rzcor result; int ?One, carry=O; fo r (unrigzed 1=0; i<c-sire ( 1 ; i++l { nOne=O ; //counc ( c [ i ] .beginO ,c[il .end0 ,SfGXIL1,ONEInOne) ; nOne = count (c[i] .begFn0,c[i~.en~O,S1GNPJ;~0NE);
/ / Removing constant zeros: No operation result = rernoveic[ij .begin{},c[i] .er?d(),SIGNPJ,-ZERCI; c[i] .erase(result,cCil .end0 1 ;
/ / S i m p l i f y constant o n e s : adding rhem together result = reF.ove(c[ii .beginO , c [ i I .ena(),SIGNNiILLONFl; c i F 1 .ercse(resulc,c[i] . e d O ) ;
nO?e-=carry; carry=nOr?e/2; nOne%=2; if (nOne!=O; c [ i l .push_back (SIGNAL-ONE) ;
1 1
void create CSA Vector(
77
vec=or<SignalVector>& op, vector<SFqrrziVector>& c sa, bool issigned) I int i, j; unsigned max9it=O; for (i=O; i<cp.sizeO ; i++l
for (i=op.çize ( 1 >>Ir j=O; i!=O; i > > = l , j -t) ; / / Get tne MSB posizion of i: Log2 (op. s i z e ( 1 l
naxBiz+= j ; / / n m-Dit operand will have outpur of n+m bic
csâ. reçize ( x ï a x E i ~ ) ;
Signal signal (VARIABLE, l I O ~ l r r O, crueI NONE, -1, -1) ; for (signol. ID=O; signal. ID<op. size ( 1 ; signal. ID*+)
O << " "c<signalc<" : in Std Logic Vector ("<< (op [signal. ID] . size O -1) <<"
d o w n t o O 1 ; \n" ;
s i g n a l . n a m e = "Sum"; f o r (sicnal.ID=l; sFgnal. ID<=2; sional. ID++)
O << Ii " < < s i g n z l < C " : out S t d - L o g i c - V e c t o r ( "cc (nBitOut-1) cc" d o w n t o O) ;\nW;
o c < " ) ;\a" c< "end; \n\c" ;
/ / Generâcf VEDL Architecture H e a d e r o c < "zrcnitecture Structural of " << en~ityNzme <C" Fs\nW
<< " componenz EalEAdderb" << " po r t (A, E: i n S t c i - L o g i c ; S m , C o c t : out S t d - L o g i c ) ; \n" c< " enci cc-onent; \n\nn cc " conFccent FullAcder\n" <c II pc rz (A, B, CFrr: in S r d - L o g i c ; Sun,, tout: o u t Std-Loqic) ; \n" << " end c c m p c n e , r ; t ; \ c \ n W ;
C S . - S t a c e = ( o p . s i z e O > = 3 ? o p . s i z o 0 - 2 : 1) ; SIGNAL-SUT. showïD=SIGNALLC1.RRY. s h o w I D = ~ r u e ; O << " slqn&lw << encil; f o r (F=O- , i < = C S A - S t a g e ; i+-1 {
SIGNAL-SVM.ID = SIGNAL_CF,9RY.ID = i; O << " w<cSFGNPL-SU-IC<", " < < S I G N P L - C m Y ; Lf ( i !=CSI;=Stage)
O << ",\nW; else O << ": Std-Logic - Vec~or("c<(nSirOut-L)<<" domto O1 ; \n\nl ' ;
, r
i E ( FsSigned)
O << " signal "; f o r (SIGLJAL-SIC-N. I D = G ; S I G N U - S I G N . I D < o p . s i z e O ; S I G N A L - S I G N . I D t i ) c << SIGXPL - SIGX C c (SIGNPL-SIGN.LD<opPsizei}-1 ? ", " : " " 1 ;
o << ": Scd-Lcgic-Vector ( " < < ( o p . s i t e ( 1 -1) <<" downto O ! ; \ r iv ;
1
i f ( i s s i g n e d ) i
s i g n a i - n a m e = "Op"; f o r ( i = O ; i<op. s i z e O ; i++) C
SIGNAI-STGN-ID = s i g n a l . 1 D = i;
void g e n e r a t e _ V H D 4 C S - A - - T a F I (
char- en t i cyNme, vector<SignalVector>& op, 5001 issigned, SignalVeccor &oucl, SignalVector &outSr oscr2arn& 01
ist CSA-Stage; unsigced nEalfAader, riFullAdder; vector<SignolVecccr> csa;
creaïe-CSA-Vector (op , csar lsSigneci} ; gzcerate-VECL-CSA-Sezaer (ent-i~:~Nms, op, issigned, csa. s i z e (1, C S C S t a g e , O ) ; generzte-VEDL-CSA-3ody (csa, CSA-Stage, r-AalEAddez, nFullAdder, O ) ; generate-VEDL-CSD,TaFI (csa, oucl , out2, O) ;
HWMult. h - - 1 . . - . - .. . -
Sifncef -HWL'ULT-H #def ine - H'rNULT-H
voia HWMult ( unsignec nVarBit, bool sFgneaVar, unsigned lcng constop, vector<SiqnalVeccor> &out, ostreEm O, ostreamç ccmpone?t, charf entityNme-0, unsigned cruncLSE=O, no01 goceraïeProduct=~rue, bcol byPass=fa l se ) ;
t o << " 3 e s u l t : ouc Scd-LcgFc-Veczor ("<< (nOuc9itl-1) <<" downto O) \n"; c << " R e s u L c : oct Std-Logic~Vec-,or("<<(nOut3Lt1-1)~~~f downto O)\n";
1 else f O << " Xesrrltl: oilc Std-Loqic-Vector ("<< (nOutSit1-It cc'' downto O) ;\n"
<< " Result2: cur S t c - Loçic~Veccor("<<(nOutSF~2-l)<<" downto O)\nn; c << " R e s ~ i t l : e u t Szci-Logic-Vector ( "<< (nOut8iil-1) <Cs' downto O) ; \nu
/ / Generace VHDL Archiïecrure Header O CC "architecture Structural of " << entityName CC" i s \ n m
<< " port (A, B: in StkLogic; Sum, COUC: out Scd-Logic) ;\nV cc ecd component;\n\nW
<< II component FulXader\n" cc Il porr iA, 9, Cin: in StdLogic; S m , Cour: out Std-Logic) ;\n" < enc cornpone~t; \n\n" ;
L 0 << " Sm << i <<", C" << i; iE (:!=CS-A-Scaqe-l)
O cc ",\nu; else O cc ": Std-Logic-Vecror ("Cc (nCSFBit-l) <<" downto O) ; \n\nn;
1
if ( invertedIn-uz} I O c< " signal N : Std - Logic-Vector ("cc (riVar9i1~-1) cc'* downto O) ; \n\nn; if (signeci'Jzr)
o << " siqnal "<<CIGM-AL-SIGN-3<<", "<<SIGN3L-SIGN-N<<": Std-Logic;\nn; 1
O c< " sicnzl P : S t d - Logic-Vector !"<< (nVarBFt -1) <<" downto O) ; \nW << " signal numl : Std-Logic-Vector ("<< (;?OuiSitI-1) <<Ir domto O) ;\nu << '* sicnal num2 : Scd-Logic-Vector("<c(nOucBit2-l)<<" aownto O);\n\nW;
o << " signal ZERO: Std-Logic; -- Constant signal 'O'\nt' <c " signal ONE : Std-Loçic; -- Zonscanc signal 'll\n";
if (bypzss) O << " signal NonZeraIn: Std-LoqFc;\nW
cc " s i g n a l ZERO-Out : S c d - Logic-Vector ("<< (nOutBit1-1) <cl1 downto O} ;\n\nW;
if (byPass) (
O << " SP: MZ"cCnVzrSFt<<" port ma? (VarI2, NonZeroIn) ; \n" <c " P <= VarIn when (NonZeroIn=' 1' ) else P; \n\nM;
e L s e O € c " P <= Var1n;\n\nu;
if (inverreciInpur) f 0 c< II-- Inverced input siqnals:\nW; //for :i=O; i<nVarBit; itt)
if (signedvar) / / Signeci variable oceranc! O << " " << SImTkL-sIG??-P << " <= P("<<(nVarBir-1) <<") ; \nvf
CC " " << SIGNAL-SIGN-Pl << " <= N ("<< (nVarBit-1) <<") ; \n\nn'; k
void generace-VSCL-Hm-TâiI ( vector<SignzlVector> &imt, vector<SiqnclVectcr> &cct, oscrêarri& O, Uool qenerzreproduct, b o o l byFass)
i ,./-------------------------------------------------------------------------- / / Mep inccxnzl signal~ to ouepur 3 s trçirfzq nu?nl, nm2 ; numl << " n u m l <= " ; nu12 << " m . <= ";
j +t ; if ( (jâ8)==O) ( numl c< "\ri "; nwn2 cc "\n
1 1 nrrrnl<<"; \n"; nu1;i2<<"; ?nW; numl . flush { 1 ; n-~m2. f l u s h ( 1 ;
cher -SI = rruml.szr(); s1[nunl.pcount()]='\O1; char * s 2 = num2.str O ; s2[num2.pcoun~(} ]='\O1; O << "\n" c< sl << ç2 <c "\fi";
O << " ZERO-Ou= <= \"" ; for (i=O; i<ou=.size ( ) ; i--) o<<"O";
if (generatePrcduct i O cc " nun <= Unsigsec(ncml) + Unsigned(nun2) ;\II"; if (byPass)
O c< " R e s c l t <= num whec (NonZeroLn='lr ) else ZSBO0ut;\n\n1'; eLse o c c " R e s u l t <= \n\n" ;
k else I
iE (5yPass) O << " R~sulclC= n u l when (NonZeroIn=' l ' 1 eise Z E R O O u t ; \nt'
<< " Result2C= n m 2 when (NonZerofn=' l' 1 else ZEE?OOuc; \n\nW; else o << " ?.esulzl<= narnl;\nw
<< " ?.esült2<= n 1 a 2 ; \n\n8';
vec~or<SiçnolV2ctor> signZero (sign) , signOne (sign) ; SIgnalVeccor: : i t e r a r o r resulr;
reclace (s içnOne fi 1 . b q i n ( ) sLgn0ne [il .*-ONE) ;
1
unsigneà n O u t S i ~ = nVarsic + const3it.sizeO; / / N u m b e r of output bit imt . r l s i z e (nCu=Bir) ; / / Inte-mediate signals sign. res i ze (nOut9it) ; / / Sign and constanc 1's
/ / I n s e r t a l1 Lncermediate signols S i q n z l siçnal;
invercedIzpuc = false; fo r ( I = G ; icconsrBit .size ( 1 ; ii+) t
if (canszBit[ij==l) t
fcz [ j=O; j< (signecVar?~Vor3it-I:nVarBit) ; j++) i signal .bitPos=j ; çiqnal,inv~rted=2OSITIVS; kr[i+j j .push-back(signa1) ;
1
s i g n [il , p u s h b a c k (SIGNPL-ONE) ;
/ / Kerge s i g n / c o n s ~ a n t s t o g e t e r and perform opcimization for constant 1's unsignec mxEepth=O ; f o r ( i = G ; i < i m t . s i z e O ; i++)
if (siçnii] .sFze() !=O) t
if ( s i g r i [ i ] [O]==SIGMAL-CNS &t i C i m c . s i z e 0 - l & & imï[i].sizeO==l & &
irr , i[i-l] . s F z e ( ) c=2)
/ / bit T I => sm-=(nec o i t ) , c a r q r = S i t iinï [ i + l ] .push-bock (imt [ i l [O] ) ; imt[ij [ 0 ] . i n v e r t e d = i m t [ i ] [O] .lnverted==POSITIVE ? NEGATIVE: POSITIVE; i nve r t ed rnpuc = t r u e ;
1 e l s e i n t [ i ] .push-bock(sigr:[FI [ W ;
i
. - I r ( F r n t [ i f .size ( ) > m a x C e g r n f inaxDepth=imt [il .size ( 1 ;
unsigned nVzrBit , ho01 signedTJar, unsigneci long constop, vector<SignzlVector> & o u t , astream& O , ostream& component, charr entityName, ansigcec cruncLSB, b o o l genera teProduc t , boo l SyPassl
( unsigzeb L , j;
/ / Cons t ruc t M u c i p l i c a t i c n v e c t o r to be usea i n CSA creace-EiW-Vector ( ~ V a r B i ' c , s igneavar , consrOp, i m t , i n v e r t e d I n p u t ,
CS&--Stage) ;
i m t . erase (imc. begin ( ) , imt . begin ( 1 +rruncLSB 1 ; COU^ << " \ n A f t e r t r u n c a c i n g "<<truncLSa<<" b i t s : \n";
/ / Generaring ca r ry - save aaaer VH3L code u s i g n e d nEalfAdcer, nFulLAdder; generate-JH3L-CSA-3cdy ( i m t , CSA-Stage, nffaifAdder, n F ~ l f A d d e r , 01 ; a.flusn() ;
/ / Generezing VEDL tail ( ~ n c a r c h i t e c t u r e & statistical i n f o r n a c i o n generace - VHDL-I_Tail ( i m t , ou t , O, gene taceProauc t , byPass) ;
l u s i n ç na-tespace scd;
c o n s t double p i = 3.1415526535897932384o;
i n t nain i i nc zrgc, char ' arcv [ 1 )
unsiqnea long va l ; ccu t << "Conscanc Operand c i n >> val;
inc nVarBit, trcncLSB, bypsss; inc s ignedvâr , generzceProduct ; couz << "f b i t of V a r i a b l e Operând . 11 .
r I
c i n >> nVar3Fc; coüt << "Çigred v a r i a b l e operond ( O / L ) : "; c i n >> s ignedvar ; cour << " # bic crurrcoted at LSB . 11 .
. ?
c i n >> EruncLSS; couc << "Generate p r o d u c i (O/l) : '*; c i n >> genera teProàuc t ; cout << "Bypass Zero ( O / L ) : Il;
c i n >> bypass;
tout CC "Entity ( f i l e ) nane cin >> en t i t yNme; if (entFtÿNarne [ O ] = = 1 \ O 1 1
c o u r <c ll\n\n"; cour << "Cons tan t Value : "C<valCC"'~n\n";
f i n c l u d e <fstre&.ru
using namespace std;
voici Nonzero (char- z n t i t y N m î , unsigned n B i t , ostrea-m6, cl f char f iloxaxte :2561 ; s p r i n t f (EileNcrne, "ES .vhdl', encityNzne1 ; L- ~ a t r e a m f (f i l e N m ~ e , F o s : : ourj ;
<< " porc\nl' << (\n" << Ir D : i n Std-Logic-Vector ("<< (nBit-1) <<" downto O) ; \n" << " NZ: ouz S t < L o g i c \ ~ " << " ) ;\n" << "end; \n\n" ;
/ / C o n v e r t unsiqnea l cng tc a sequezce of bic. / / Trie MC6 of t k e r e t u r n i z g b l t is a l w a y s O
void ulonqToBFc(unsFgned long 1, vector<char>& b i c ) ;
vo i d 3izoryToSFgnDigFE (veceor<char>& b i t ) ; void op r in ï zeSD (vec tor<char> &bic) ; / / Seduce -1's void uLongToSignDigit (unsigceà long I, vector<char>& sd) ;
vold uiongToBoo~8 (unsigned long 1, vector<cnar>& booCh1; vo i d E o o c k T o S i c p D i q i ~ (v~c to r<cha r>&boo th , vecror<char>& sd);
1 osc r smh p r i n t a i c ( c s c r e m i O , veccor<chsr>& b i t ) ; vo i d s k o w B i t ( v e c t o r ~ c h ~ r > t bir;;
#endif
/ / Convert wsiqned lonç CO a sequence o f S i c . / / T h e ES3 of the returning bit is always O void u l o n g T o S F r (unsiqxed l o n g 1, veccor<thar>& Sic) t
b i t . c l ea r ( ; for (; l ! = 0 ; 1>>=I)
bii.push-'Dack(l&l ? 1: O}; 1
void show Bi^ (veczor<char>& b i t ) t
p r i ? c 5 i c ( c o u t , nit ; 1
f o r ( i n t F = D ~ E . size ( ) -l; i>=O; i--1 f o << s e t w ( 3 ) <c ( i n t ) b l r [ l l ; if ( b i ~ [ i l ! = O ) weight+t;
1 O << " Weighc=" cc welght; retur? O ;
1
int stczc, enc; / / Sïârt azd end p o s i c i o n of consecotive ones
i stârt=i; f o r (end=i+l; end<rBit; end++) if ( ~ i t [ena] ==O) breok;
i f (ena-s târt>l) / / More cheni one l y s i
b i ~ [starcl=-1; b i t [end] =l; for ( s t a r t t t ; startcend; start-f 1 bit [scart]=O;
! F = end-1;
if (bit [bit-size ( ) -l]==O} b i t - c r a s e (8ir.end:; -1) ;
1
void ulongToSignDigit (üns igned l o n q 1, vec ro r<char>& b i t ) i
ulongToBit (1, b i r ) ; b ina ryToSignù ig i r (bit 1 ;
/ / cp tL .?zeSD ( b i t ) ; i
L
s t o c i c ccnçc c h a r ~ o B o o c h [ ] = ( O , 1, 1, 2 , -2, -1, -1, O );
v o i d BoothT~SignDFgiC ( ~ e c t o r < c h a r > & C o o t h , vec to r<cner>& sd) f
f o r (int i=O; i < b o o c n . s F z e ( ) ; i++) s w i ~ c h ('coccir [ i 1 1 I
case -2: sd-push-back( 0); s d - p u s h b a c k ( - 1 ) ; Dreak; case -1: sd, push-back (-1) ; sd.-ush-back ( 0) ; break ; case 0: sd . pusn-bock ( 0) ; sa. pnsn-back ( 0 ) ; break ; c a s e I: sd.pnsh-bccic( 1) ; çd. p u s h b a c k ( 0) ; break ; c a s e 2: sa. p u s n j a c k ( O } ; sd. pnsn-back ( 1) ; break ;
. . ) . . - - . - . .;, :z D i f nde f -VHDL-SIGN-AL-B + d e f i n e VZDL-SIGNAL-ii
ginciucie < v e c t o r > Winciude < ç ~ r i n g > SincLuae < ios r re s ,w Oinclude <iomanip> k i n c l u d e <s t r s t r ea rn>
u s i n g nanespace std;
cypeaef enum { CONSTANT, VXQIPBLE, SIGN 1 s F q n a l T p e ; c ~ e d e f enum ( NONE, POSITI'VE, NEGATIVE 1 inverrrype; typede f enum { ZERO , ONE, OPEN 1 consrIDType; cypedef enum ( INPUT, SUM, CARRY 1 varIDType;
Signa l ( 1 : tlQe (V.=IP3LE) , name l " " ) , I D ( O ) , i nver ted(~ONE) , bFtPos (-1) , s t a g e (-1) , show13 ( f â l s e ! 1 ;
i q n a l ( s i g n a l T l n e t , cha r "2, ur-çignêd id, bool showid, inverCType inv, int pos, i n t s t g )
signalType type; char* ncn~e ; unsigneci I D ; / / ID f o r che s i ç n a l Do01 showID; inverzType Invexed; i n t --- b i t - 3 0 ~ ; / / Bit p o s i t i o n (Non-negative i n t e g e r . -1 w i l l not show
che b i t position) irrc stage ; / / stage where t h i s s i g n a l is gensra ted (-1: input or
corstent s igna l & w i l l not show the s t a g e )
s t a c i c Fnt cre~ceNewSigria l0 { ur,sigzed save=idCount++; return s c a c i c int idCounr;
I ;
oscreznh 03erator << ( o s t r e ~ = & s t r e m , const Signal& s i g n a l ) ; bool operator== !cocst SLgnal&sl , cons t Signal &s2 ) ; bool osera tor ! = (consr S i g n z l & s l , consc Signal &s2) ; bool operâcor < (consc S i g n a l & s l , c m s r Signal &s2) ;
consr Signal S LGN-%-ZERO (CONST,n-NT, " ZERO " , ZERO, Eâlçe, NONE, -1 , - 1 1 , SIGXALONE (CONSTANT, " GNE " ,ONE , fâLse, NONE, -1, -1 1 , ÇIG>IAL OFEN (CGNSTGXT," \'X\' " , O P ~ N , ~ ~ ~ S ~ , N O N ~ , - 1 , - I ) ; -
uçing nomespace scd;
i n t SicnaL::idCcunc=O;
//------------------------------------------------------------------------ o s t r e m & operator CC ( ~ ~ ~ r e m & st rem. , const Signal& s i g n a l ) f
scream << signal.norne; i f (signal. cype==CONST-XYT ) re turr - scream;
if (signal.showID) strearn<<sLgnal. I D ;
Ff (signal.inverred!=NONEI stream << ( s i g n a l . i n v e r r e a = = P O S I T I F Y ? " P" : "N" ) ;
/ / Variable signal if (signal.stage>=O:
stream C < signal. sraqe;
//------------------------------------------------------------------------ bool operatcr==(consC Signal&sl, const Signal & s 2 ) ( . - rr (s i . t - p e ! = s L . type) retrrrn false;
i f (si. ttype==CONST-W! recurn (sl . ID==s2. ID) ; rêcnzn (SI. ID==s2. ID & & sl. inverted=s2 . inverteci & & sI.SitP~s==s2 .bitPos
s l . s t a g e = = s 2 . s r a g e ) ; 1
//------------------------------------------------------------------------ Dco: operâccr < ( c o n s t Signal &sL, const Sigcal &s2) i
if (sl. s ï age<s2 . scoge) return true; i f (SI. ~~Q~==CONSTPNT) rerurn true; i f (sl. stage==s2,stage)
- - - ,- ,, :SI. ID==SUM & o s2 - ID==C..V.?.Y) r e t c r n zrne; roccrn f alse;
The following is the Java source code listing for IEEE Standard 1 180- 1990
compliance test program for IDCT. It is used to determine the interna1 bandwidth of the
IDCT for both the first dimension IDCT and second dimension IDCT.
The codes are listed in alphabetic order based on the souice file name. The main
program is located inside file IEEE-118O-l99Ojava. Notice that al1 codes are also
included in the attached CD.
To esecute the program, use the following command: jm IEEE - 1180 - 1990. The
program reads the intemal banduidth confipuration from file Setzptxt, and perform test
to check if the bandwidth yields IEEE 1 180-1 990 compliance.
. - - - - CSDij ava . - . . . I V . - - -A,
/+ Convert conven t iona l b i n a r y nunber t o c a n o n i c a l sign-digit represen ta t ion Algorir-hm: H. Zwarig, Conputer Aritiimetic, Wiiey, 1979 , pp. 150 Coding : Pai, Cheng-Yu Nore
To conpi le , execute " j avac SignDiqit . java" To rur. , e x e c u i e "java SignDigit xxxx",
where xxxx is the number wish t o c o n v e r t . * /
p u b l i c class CSD {
p u b l i c s c a t i c byte [ 1 coCSD ( long 1) I
/ / Construct bit a r r a y represencacion of t h e input byte [ ] b = ( "O"+Long. toBinaryStr ing (1) ) . ge tBytes ( 1 ; f o r (inc i=0, j=b. length-1; i<=j ; i++, j - - 1
byce [ l d = new b y t e [b. l eng th] ; byte ci=O, ci-1; f o r (Fric :=O; i <b , lengtn; i + t , ci=ci-l) f
i f (i==b . lenqcn-1 j
ci-l = ( b y t e ) f (bEll+ci>l)?l:O); e l s e ci-l = ( b y t e ) ((Dlil+b[i+l]tci>l)?L:O); d[d. lenoch-i-l] = (byte) (b [il +ci -2fc i - 1) ;
t
. .. .. . -. FDCEjava - _ -
._. . . _ _ - - _ . - - -- 1 .-.. -, . . . . - ,
public c l a s s FDCT {
s c a t i c double s [ l [ = new double i51 [8 1 ; s r z c i c double tmp[] [! = new couble[8] [ a ] ; s t a t i c final ict m a p [ ] = { 0 1 4 , 2 1 6 , 7 , 3 , 5 1 1 ~ ;
s r a t i c void f
s [ s cage t l s [scage+1
f
static ~ i o i d xO, inc ? c l )
L o e f f l e r (acuble AI double BmixusA, docble AplusE, int ç ïsge , i n t
s t ac ic vo id Lrl (inï srage, i n t xO, i n t xl) I ?.
r r n a l Fnc n=l; f i n a l double k=Mach . sqrt (2 1 ; f i n a l double a=k*Math.cos(n*Math.P1/16),
fer ( j = O ; j <8 ; j++: Sysrem.out.princ(tmptil [ j I + " , "1 ;
Syste,.n.out - p r i n t l n ( 1 ; 1 Systern-out -println f) ;
+/ f c r (i=O; i < B ; i++l f
/ / Izpuc rnapping for (j=O; f c 9 ; j + t l s[0: [ j ] = t x p [ i ] [ j ] ;
/ / Stage 4 for ( j = O ; j < l ; j++, s [41 [ j ] = s [ 3 ] [ j ] ; Bucterfly!3,7,41 ; sC41 [51 = r oo t2 * s r31 [51; s [ 4 ] [ 6 ] = roo t2 " s [ 3 ] i61;
/ / O ~ r p u t rnapping for (j=G; j<8 ; Siil ~lockli] [mapl j ] 1 = (shorr) Math. rounci (s 1 4 1 [ j ] ) ;
/ = Syste_m.oi?c . p r i n t I n ("23 S: " 1 ; f o r (j=O; j<5; j-i) (
f o r (k=.;li; k<3; k t t j System.out.prir,rs(s[j! [k]+", " ) ;
Syscem.out . pzintln! ; 1
= /
I s t a t i c double s [ I [ ] = n e w doul ; le[5][a] ; s t c t i c couble unp[] C I = new doub l e [8 ] [8 ] ; s c a t i c f i n a l Fnt mop[I=f0,4,2,6,7,3,S,11;
scatic void Ektterfly ( i n t stage, i n c xO, inc xl)
1 s [sczge-il [xOj = !s istaçei [xO 1 + s [stage] [xl] /2; s [scâgeil] [XI] = ( s [stoçel [xO 1 - s [stage] [xll ) /2;
I
s z o c i c voici Iloeffler(ao&le C, double DminusC, d o b l e DpLusC, int stage, i n t xO, inc xlj
s t a t i c long s [ j [I = new 1o~qi51 [ 8 ] ; sratic l o n q t?~ [ 1 [ ] = n e w long [ a j [ 8 1 ; scatic f i z a l int mep[]={O, 4,2,6,7,3,5,1);
p rec i {
Frit i; Long factor = ( (long} 1) <Cprec; Lonq CL, subL, surrL; CL = (long1 Math. r o u ~ d ( c " f a c t o r ) ;
~aCtOr) ; s u j L = ( long) Mach. round ( s-;bw =- s-mL= (Lcr-.g) Mazh. ronnd ( smtfzctor) ;
coplidx] [O] = CSD.toCSD!cL) ; COD [ idx] [l] = CSD . coCSO ( s u b L ) ;
p u b l i c staric void iniï-IDCT-Trunc ( i n r p r e c [ 1 1 t
f i n a i d o b l e k [ ] = { L , 1,Math.çqr t (21 1 ; final int 1 ~ [ ] = { 1 , 3 r l l ; double c, d, sub, sun;
I Syscern, o u t , p r i n t l n ("LnFtialize IDCT c o e f f i c i e n t s : " 1 ;
f i n a l cou8 ie F r = 1/Math.sqr= ( 2 ) ; long factor=! (long) 1) <cprec [ 3 I ; long r2L = (long) Nach. round ( i r C f a c t o r 1 ; Fnü-Zoor2 = CSD. toCSD (r25) ;
Sysren. o u t . p r i n t l n ("l/Sqrt (2) =11+r2L1 ; 1
/ * scatic long mult ( n y ~ e sdf 1, long v a l , int t r u n c l f
l o n g resclr=O;
s t a ~ i c l o n g nult (by te sa [ ] , long val, int trünc) {
long result=O; long pp; i f (vel==O) rerurn 0; n.bIul++;
f o r ( i n ï i = O ; i<sd . l eng th ; iit) I
i f ( s a [ i ] = = O ) c o n t i n u e ; if (sQiij==lj t if (i<trunc) pp=val>> (trunc-F) ; eiss pp=val<< (i-crunc) ;
1 else / / s a [ i j = = - 1
return result;
I l 1 stacFc n i d IButterfljr(Fnt stage, int xC, ict xl) 1
1 scatic void Xutterfly2(irii szaqe, inc xO, int xl)
srcric vcid I L o e f E i e r (byte C [ 1, byre DminusC[ j , byte DplusC Il, int stage, int 1 x g i Lnc x l , in^ ï r u n c ;
long m p = mult ( C , s [s~agej lx0 1 +s [scaçel [XII , trunc) ; s [stage+l] [xO j = r n u l ~ (3plusC , s [sragel Lx01 , trunc) - t m ~ ; s [stogeii] [xl] = mult (Dr r i nüsC , s [stage] [xl] , trunc) + tmp;
static void Icl(inc srâge, int xO, i n t XI, int trunc) f ILoeffler(cûp[O] [O] ,cOp[OI [Il ,cOp[O] [23 ,stage,xO,xl,trunc) ;
k
static voici Ic3 iint stage, int x O , int xl, i n t trunc) i ILoeff' -,~er(cO?[il [Gl ,c3pCII [Ii,cOpiL] 121 ,stàqe,xO,xI,trunc);
1
scar ic void Irl (int scage, int :<O, i n t xl, inr trunc) ( ILaeffler(cûp[2! [ Q I , cOpE21 [ I l ,cUp[2] [ 2 ] ,s~~ge,xO,xl, t r unc ) ;
1
szacic voia adj u s ~ G f f s e c ( l ong stage i l , inc offset [l ) 1 for (inr i=O; i<8; F-+) ( if (offset [il CO) stage[i] >>=(-offset f i l ) ;
else if (offsec [il >O1 stâçeri] <<=offsec ii! ;
1 1
static long cclcR (int r) ( if (r<2) r e t u r n O; / / Do nothing int i. i;
lorig offsec; for (i-l, of fset=l; i<r- l ; i++) offset=(offset<<l) i 1;
/ / o f f s e r = ((lcnq]l)<<(r-2); r e t u r n offse~;
j
public static void F d c t T r u n c (short block[] [ J , int crunc [ l [ i , F n t - - orrsez[J [ I [ j ,inr r o u d t ?
f I n t i, j , k; Lcng rO, rl;
r O = calcR (round [O 1 ) ; r l = calcR (round [l! ) ;
/ * Systen.out .priztln ( 1 ; Sysrs-rn-out . p r i n c h tl'Diner?sicn O: " 1 ;
* / for (i=Q; i < a ; ii-) f
/ / I n p u t m.pging for [ j = O ; j<8; j ~ - )
s [O] [ 5 ] = ~lock[i] [map[j]];
/ / Stage I LSu tce rE l y2 (û, 0,l) ; I rl ( 0 , 2 , 3 , crunc[U] [21) ; i B u c c e r f l y 2 ( 0 , 7 , 4 1 ; s [Il E S ] = rnult (invRoot2, s [O] [ 5 j , crux 101 [3 ! ) ; s[l] [SI = mclt(invRoot2,s [O] (61, trunc[Ol [ 3 l ;
/ / Stage 3 for ( j = O ; j < 4 ; ïi+i / / Rounding
s [ 3 1 [ j l = s12J Ljl i (r0 << (-offset[O] [ 4 ] [jl-round[O]) ) ; .*ddi=4 ;
Ic3 ( 2 , 4 , 7 , c r u n c [ O j [tl) ; T c 1 (2,5,5, ~runc[O] [On ;
a d j u s t O f f s e t ( s [ 3 ] , o f f s e t [O] [ 3 ] ) ;
/ / S t a g e 4 f o r ( j = O ; j c 4 ; j++)
IButterfly2{3, j,7-j};
/ / Stage I ISc tcer f ly2 (O, O, lj ; Tr: - - - (0,2,3, trunc111 12i ; ISuizerfly2(0,7,4) ; s [ l ; [SI = mult(invRocC2,s [ O ] [ S I , tzunc[L! [311; s i l j [ 6 j = mult(inv2cot2,s [O] [ o ' ] , trunc[l] 131) ;
a c j u s t O f f s e t ( s [LI, of f sez [ I l [II 1 ; I
/ / Stage 3 for ( j = O ; j < 4 ; j - i )
s131 [ j ] = sC21 [j] i (rl <C t-offsec[ll t 4 l [jl-round[l]) ) ; -cd+=4 ;
1 lonc; max; i n r percect; System. out .pr inc ("PASSZD: pme (max) =") ; for (F=O,max=O; i<8; ii+) for ( j = O ; jc8; jt-1 if (prne[i][j]>.max) max=pmelil[jl;
for (i=Or~x=O; Fc8; i++) for ( j = O ; j c8 ; j++) . I r (prnse[i] [j!>max) max=pmse[il [jl;
percent = ( i n t ) ( (mox*100 .O) /pmseMFX) ; Systern-out . p r i n t ( (ni.â.u/10000. O) +" ("+?ercent+"%), " 1 ; perîeEt = (inrs) ( (cme-IOO. O) /omeMAX) ; syçtem. ouc.prht (orne/ ( 6 4 - IOOOO. O) ) + p e r c e n t + % , " 1 ;
f u r (in: token=s .nextToken ( ) ; token!=s . T T N b . E R ; token=s . nexzToken ( ) ) ; r e r u r n (Fr î t ) S. nvol;
1
static void FnirSerup ( i n t trunc [ ] Clr int offset [ l C I [ I ir?t round[] ) throws Lxcept ion
t i n t d l L, j;
IDCT-Trunc. init - ICCT-Trunc (prec) ;
t for (i=O; i<5; F-i)
for ( j = O ; 5 4 ; j++) offse~:d] [i: [j ] = qetInr ( s e tup ) ;
round[Q] = qeeInt (setup) ;
i
public s r a t i c void main (String orgs [ 1 ) throws Excepzion
static i n t qetïnt (Streâ-~ToKenizer s) t n r ~ w s Exception
initçetup (trunc, o f f s e t r zound) ;
for (i=C; Fc2; i++, negote=!negare) f o r ( j = O ; j<3; j++)
if (!checkLE(L[j] ,H[j 1 , negate,tzunc, offset, round) 1 re turr?;
Systom.out . p r i n c l n ("A11 t e s t passed! " ; 1
p u b l i c scaï ic void Fnitclong 1, long h)
randx = 1; z = Docbie. long~itsToDouble (Ox7fff f f ff) ; ; s=n;
?ublic sca t i c long rand( 1 !
Icrig i, j; CouSLe x;
pirSlic s t a t i c void m i n (Srrizg orgs : ! ) i
l o n g 1, ?, n; n = Long .parseLong (args l0l) ; I = Long. parseLong (args l1l: ; h = Long. pa r seLo~g (args :2j) ;