D ESIGN AND I MPLEMENTATION OF A S OFTWARE R ADIO T ESTSET FOR R ESEARCH AND L ABORATORY I NSTRUCTION Fraidun Akhi 10/30/03.

DESIGN AND IMPLEMENTATION OF A SOFTWARE RADIO TESTSET FOR RESEARCH AND LABORATORY

INSTRUCTION

Fraidun Akhi

10/30/03

CONTENTS…..

• Statement of Purpose• Introduction to Software Radios

– The Software Radio Concept– The Wireless Communications Industry– Potential Benefits – Potential Applications– Technological Hurdles to Ideal Software Radio Design– Practical Software Radio Designs– RF Front-Ends– Data Converters– Signal Processors

…...CONTENTS

• Data Converters Circuits– Digital to Analog Converter

• RF Measurements– Transmitter measurements

• Project Status and Future Development– What has been accomplished

– What remains to be done

– The potential benefits of this project to AU

……CONTENTS……

• RF Front-End Design and Implementation– The RFMD WLAN Chipset

STATEMENT OF PURPOSE

• To explore the design and implementation of a software radio testset that could be used for an undergraduate teaching lab, or as the foundation for a graduate-level research lab

• Emphasize on:– RF design and measurement capability– DSP algorithm design and implementation– Integration of the RF and DSP sections through the use of data

converter circuits– Evaluation Modules and Circuit Assembly– Shielding and Grounding Issues

• DSP Starter Kits– Serial Ports

– Code Composer Studio

SOFTWARE RADIO, THE CONCEPT

Transfer transceiver functionality from the hardware to the software domain, eliminate RF front-end

• Filtering

• Equalization

• Encoding/decoding

• Modulation/demodulation

• …..All done by software in DSP

ADC

DAC

DigitalSignal

Processor

Peripherals

Rx

Tx

THE WIRELESS PHONE INDUSTRY

• More than 1.3 billion cellular phone users in 2003

Analog4% CDMA

12%

GSM70%

TDMA10%iDEN

4%

Analog1% CDMA

20%

TDMA10%

GSM68%

iDEN1%

2001 PCS Market

2005 PCS Market

GSM v.s. CDMA

• GSM– Time Division Multiplexing

– 200 KHz – wide channels

– GMSK Modulation

• CDMA– DSSS

– 1.25 MHz – wide channels

– QPSK Modulation

THE WLAN INDUSTRY

• More than 4 million Wireless Local Area Network (WLAN) users in North America, and growing

• Many different standards competing for the market– IEEE 802.11b – DSSS, 2.4 GHz, 11 Mbps

– Bluetooth – FHSS, 2.4 GHz, 1 Mbps

– IEEE 802.11a – OFDM, 5.8 GHz, 54 Mbps

– IEEE 802.11g – OFDM, 2.4-2.483 GHz, 54 Mbps

• Backward compatible with 802.11b

– IEEE 802.15.3a – UWB, 3.1 GHz – 7.1 GHz, 110 Mbps

• Still in development

POTENTIAL BENEFITS OF SOFTWARE RADIO

• Real-time Configuration– Download new features into handsets

– All phone features can become adaptive to environment

• Adaptive control of power emissions

• Adaptive signal processing

• Multi-Standard Operation– Cellular basestations and handsets no longer becomes

obsolete with changing standards

– Interoperability between standards

……MORE POTENTIAL BENEFITS

• Power Efficiency – Some 70% of wireless transceiver power consumption is

due to RF front-end, which software radio eliminates

• Digital Performance Advantage– Digital technology is more predictable, reliable, and

immune to environmental factors

• Fewer Components, no RF-Front-End

– Cost savings

– More compact designs

POTENTIAL SOFTWARE RADIO APPLICATIONS

• Cellular Phone Systems– Can help reduce migration costs in basestations

– Can improve the performance and price of handsets

• Military / Law Enforcement – Interoperability between different units’ radios

– An effective intelligence gathering device

• Academia– Real-world implementation and analysis of signal

processing algorithms

TECHNOLOGICAL HURDLES TO IDEAL SOFTWARE RADIO DESIGN

• Analog to Digital Conversion– Fastest low power ADCs with reasonable bit-resolution sample at ~300

Msamples/s

• The Ideal software radio requires at least 10 Gsamples/s

• Processing Power– If the ADC problem was solved, could the transceiver process so many

samples?

• Multi-processor units can handle large processing loads, but these are only possible in static units such as basestations, not in handsets where low power consumption is key

PRACTICAL SOFTWARE RADIO DESIGN

• Include an RF front end to ease the requirements placed on the data converters and thus ease the processing load

• The drawbacks are bandwidth limitations of the front-end, and the loss of control over modulation/demodulation

ADC

DACPA

LNA

BPF

RF Front End

DigitalSignal

Processor

Peripherals

SUPER-HETERODYNE RF FRONT-END

• Modulate/demodulate in more than one stage• Low Power, high performance, no DC offset, very few

high-performance parts needed • Drawbacks include the high chip count, bulkier

design, narrower bandwidth

LNA

IF BPF LPF

ADC

RFf IFf

RF BPF

DIRECT CONVERSION RF FRONT-END

• Low chip count, less cost, more compact design• No image rejection problem• Drawbacks include DC offset caused by LO self-

mixing, I/Q balancing issues at RF

RF BPF

LNA

LPF

ADC

Cf

LOW-IF RF FRONT-END

• Fewer components than Super-heterodyne, no DC offset problem, design is partly digital

• Currently the best option for software radios• Drawbacks are that a higher performance ADC

is needed, I/Q imbalance problem at RF

RF BPF

LNA

IF BPF LPF

ADC

RFf IFf

Digitaldemodulation

DATA CONVERTERS

• Low power digital to analog converters available at speeds of ~800 MHz, DACs lead ADCs in speed

• The lack of fast, low-power, high-resolution ADCs is holding up the realization of software radios

– Most software radios include a low-IF RF front-end, usually with an IF less than 100 MHz

– Subsampling, whereby under-sampling of the IF (or potentially RF) carrier leads to the sampling of its image near baseband, is a potential solution to the shortfall in ADC performance

SIGNAL PROCESSORS

• ASIC (Application Specific Integrated Circuit)– Highest performance, lowest programmability

• FPGA (Field Programmable Gate Array)– Very high performance, programmability

– Ideal for semi

• DSP (Digital Signal Processor)– High performance, real-time programmability

– The ideal engine for a software radio because of its real-time configurable features

RF FRONT-END CHIPSET

BPF

Tx / RxSwitch2.442 GHz

1/2 wave2.4 GHzdipole

antenna

RFLO

IFLO

Dual PLLFrequncy

Synthesizer

SAWBPF

LNA

GainSelect BPF

2.442 GHz 374 MHz

2.068 GHz

Rx

Tx

Iout

Qout

BasebandAmp / LPF

Rx VGC

LPF

LPF

Iin

Qin

748 MHz

BPF

PA

RF2494 PCBA

RF5117 PCBA

Tx VGC

PAdriver

2.442 GHz

IFAmp

RF2436PCBA

SI4136 EVM

RF2948bPCBA

RF front-end design using the RFMD WLAN chipset

Tx

Rx

IFAmp

RF TRANSMITTER ASSEMBLY

RF RECEIVER ASSEMBLY

SHIELDING AND GROUNDING

RF Transmitter

SHIELDING AND GROUNDING

RF Receiver

DSP STARTER KITS

3.3VPowerSupply

8Mx16bSDRAM

128Kx8bFlashROM

80-Pin IOConnector

TMS320C6711DSP

80-Pin IOConnector

DIPSwitches

LEDsAD535 CodecIO Microphone

IO Speaker

ResetButton

JTAGController

JTAGHeader

1.8VPowerSupply

PowerLED

PowerJack

PC ParallelPort

Inerface

DSP TESTING

CODE COMPOSER STUDIO

MCBSP CABABILITIES

• Transfer serial data stream as fast as ~35 Mbps• Implement a number of standard or custom

serial port interfaces• Can be used to send data and sync channels

through RF link, in DSSS implementation

DSSS IMPLEMENTATION

Figure 4.5 – Data processing at the receiver

Data File

Bits d(0)....d(n)d(m)

PN Length PN

XOR

OverSample

x(m) DataTransmitRegister

MCBSP

DataReceiveRegister

MCBSPData File

Bits d'(0)....d'(n)y(m)

PN

XOR

PN Length

DownSample

d'(m)

Figure 4.4 – Data processing at the transmitter

MULTI-CHANNEL BUFFERED SERIAL PORTS

MCBSP MasterTransmitter

MCBSP SlaveReceiver

CLKX

DX

FSX

CLKX

DR

FSX

DIGITAL TO ANALOG CONVERTER

I in 1K

27

+

-

+9V

-9V

820

820 820

+

-

+

-820

820Bias

Q in 1K

27

+

-

+9V

-9V

820

820 820

+

-

+

-820

820Bias

+

-

1K

225

Bias

9VI in

Q in

100 mVpp+1.6V DC

100 mVpp+1.6V DC

0-3.3 V

0-3.3 V

All op-amps:LM6172 with

unity gainbandwidth of

100 MHz

DAC PERFORMANCE

Output at 1.25 MHz

RF TESTING

RF MEASUREMENTS

Data Signal Spectrum Spread Signal Spectrum

Direct Sequence Spread Spectrum Processing Gain

PROCESSING GAIN

• Processing (PG) is a comparison of the bandwidth of the symbol stream to that of the spread chip stream

• In the previous slide, a 16-bit PN sequence was used to spread the data sequence so:

dBPG 03.92

16log10 10

• Measured Processing gain is 7.83 dB (17.33 - 9.5), from spectrum analyzer measurements

ACCOMPLISHMENTS

• Successfully wrote and tested the DSSS programs on the MCBSPs in wired mode

• Successfully built and tested the DAC circuit with the DSK and the RF transmitter

• Successfully built and tested the RF transmitter and receiver units

LESSONS LEARNED

• The initial reason that the RFMD chipset was chosen, was that its super-heterodyne structure offered many test points for RF measurements

– EVMs were very sensitive to static and voltage surges, and thus many chips were accidentally destroyed

– Debugging of the RF circuitry took up most of the time spent on the project, and limited further software development

• If a suitable RF front end is not commercially available, perhaps a more compact chipset such as the MAX2822 single-chip direct conversion transceiver should be looked into

REMAINING WORK

• Test the ADC circuit that is currently under construction – this will close the loop

• Build a rigid single-board RF front-end in a chassis

• Use ADC and DAC daughter-cards as data converters, improve performance

• Add processing power by adding FPGA’s into the mix

WHY THE SOFTWARE RADIO PROJECT SHOULD BE CONTINUED

• Software radio is the future of the wireless industry and thus should be a focus of the Wireless Engineering program at Auburn University

• An active software radio project or lab at AU would put the it at the forefront of wireless research and development with the likes of MIT and GA Tech, both of whom put lots of research emphasis into software radio

• It would provide an educational/research setting for undergraduate/graduate students who seek to study design and implementation of wireless systems with DSPs, FPGAs, RF front-ends, antennas, and data converters