CPEN 315 - Digital System Design Chapter 10 – Instruction SET Architecture (ISA) © Logic and Computer Design Fundamentals, 4 rd Ed., Mano Prentice Hall.

CPEN 315 - Digital System Design

Chapter 10 – Instruction SET Architecture (ISA)

© Logic and Computer Design Fundamentals, 4rd Ed., ManoPrentice Hall

© Computer Organization & Design, The Hardware/Software Interface - Third Edition

Computer Organization

Layout

I/O systemInstr. Set Proc.

Digital Design

Circuit Design

Datapath & Control CPSC 414

Compiler

OperatingSystem

Application

Firmware

Coordination of many levels of abstraction Under a rapidly changing set of forces

ComputerArchitecture

Applications

OperatingSystems

Technology(a = F/m) Programming

Languages

History

cleverness

Forces on computer architecture

The big picture

Since 1946 all computers have had 5 components

MemoryROMDRAMSRAMCache

Processor Inputkeyboardmousedisk

Outputdisplayprinter

Control‘brain’

Datapath ‘brawn’

What is the significance of Computer Architecture?

It impacts every other aspect of computer/electrical engineering and computer science.

It’s exciting! Microprocessor performance growth “unmatched by other industries” [John Crawford, Intel fellow]

Processor speed has doubled every 18 months (1982-

1996)— Cars would travel at 44,000 mph and get 16,000

miles/gal.— Air travel: L.A. to N.Y. in 22 seconds.

Single-ElectronTransistor

Itanium (~ 2 billion Transistors)

Computer architecture is becoming more important as computer technology continues to advance.

What is the significance of Computer Architecture?

If you want to call yourself a “computer scientist” Programmers and computer scientists who seek to build

competitive versions of compilers, operating systems, databases and even applications will need to increase their knowledge of computer architecture and organization:

- interface between the software and hardware

- performance of a program

- hardware techniques that affect performance

Why study Computer Architecturecovered in CPEN315 CPSC330 and CPEN414?

What is “Computer Architecture”?

Computer Architecture = Instruction Set Architecture

+ Machine Organization + …..

The Instruction Set: a Critical Interface

instruction set

software

hardware

Instruction Set (IS) Architecture - continued

A very important abstraction

• interface between hardware and low-level software

• standardizes instructions, machine language bit patterns etc. IS includes anything programmers need to know to make machines language program work correctly including instructions, registers, memory access, I/O devices, etc.

Instruction set architectures:• 80x86/Pentium/K6, DEC Alpha, MIPS, SPARC (Scalable

Processor Architecture), HP workstations

From a high-level language to the language of the hardware

Control Signal Specification

Machine Interpretation

°°

High Level Language Program

Assembly Language Program

Machine Language Program

Compiler

Assembler

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw $15, 0($2)lw $16, 4($2)sw$16, 0($2)sw$15, 4($2)

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

ALUOP[0:3] <= InstReg[9:11] & MASK

RISC Characteristics: Uniform instruction format, with the opcode in the

same bit positions in every instruction, demanding less decoding.

Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally separate floating point registers)

Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations

RISC Instruction Format R-type: add $t3, $t2, $t6

I-type:addi $t2, $t3, 6

based or indexed addressing: lw $t2, 4($t0) -Load word at RAM address ($t0+4) into register $t2 -"4" gives offset from address in register $t0

RISC Instruction Format - continuedbased or indexed addressing:

sw $t2, -12($t0) - store word in register $t2 into RAM at address ($t0 -

12)

- negative offsets are fine

Jumps j target # unconditional jump to program label target

jr $t3 # jump to address contained in $t3 ("jump register")

Readregister 1

Readregister 2

Writeregister

Writedata

Writedata

Registers

ALU

Add

Zero

Readdata 1

Readdata 2

Signextend

16 32

Instruction[31–0] ALU

result

Add

ALUresult

Mux

Mux

Mux

Address

Datamemory

Readdata

Shiftleft 2

4

Readaddress

Instructionmemory

PC

1

0

0

1

0

1

Mux

0

1

ALUcontrol

Instruction [5–0]

Instruction [25–21]

Instruction [31–26]

Instruction [15–11]

Instruction [20–16]

Instruction [15–0]

RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite

Control

Simple datapath with control unit

op

rd

rt

rs

Mapping Control to Hardware

PLA structure

Let’s try Opcode = 000000What type of instruction format?

Datapath & Controlphases of R-type instruction

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31 26]

4

16 32Instruction [15 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress

Instruction “fetch”ed & PC incremented

Instruction decoded

Register read of source arguments

ALU op excuted

Data written back to register

Datapath & Controlflow of ‘load’ instruction

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [15– 11]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31– 26]

4

16 32Instruction [15– 0]

0

0Mux

0

1

ALUcontrol

Control

Shiftleft 2

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1ALU

Address

Base register $t2

Offset

Effective address $t2 + offset

Destination register $t1

Data to load into

$t1

Control Signal

“Regdest”

lw $t1, offset($t2)

rt

rs

Datapath & Controlflow of ‘load’ instruction

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [15– 11]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31– 26]

4

16 32Instruction [15– 0]

0

0Mux

0

1

ALUcontrol

Control

Shiftleft 2

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1ALU

Address

lw $t1, offset($t2)

Instruction “fetch”ed & PC incremented

Instruction decoded

Register read of source argument

Base register $t2 & offset

ALU op excuted

ALU computes sum value in $t2 and offset as address for data memory Data from

memory written back to register

Datapath & Controlflow of ‘branch equal’ instruction

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [15– 11]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31– 26]

4

16 32Instruction [15– 0]

Shiftleft 2

0Mux

0

1

ALUcontrol

Control

RegistersWriteregister

Writedata

Readdata 1

Readregister 1

Readregister 2

Signextend

1

ALUresult

Zero

Datamemory

Writedata

ReaddataM

ux

Readdata 2

Add ALUresult

Mux

0

1

Mux

1

0

ALUAddress

Register read of source arguments ALU op

excuted

subtract operation

Instruction “fetch”ed & PC incremented

Determine whether PC + 4 or branch destination address is written into the PC. MUX is set based on the zero output of the ALU

All previous slides have shown single cycle implementations Each instruction can complete within a single clock cycle

CPI = 1 But… the clock cycle is determined by the longest possible

path in the machine. Which is the longest instruction? Hint: it uses 5 functional units in series: the instruction

memory, the register file, the data memory, and the register file.

Not optimal for all instructions; must use slower clock. Alternatives: 1. Multi-cycle implementation 2. Pipeline implementation

Datapath & Controlsingle cycle implementations