CoolRunner™-II Advanced Features - II
Jan 11, 2016
CoolRunner™-II Advanced
Features - II
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Advanced CoolRunner-II Techniques-II
• On the Fly Reconfiguration (OTF)– Understanding OTF– OTF Applications
• DataGATE– Understanding DataGATE– DataGATE Applications
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On the Fly Reconfiguration (OTF)
• OTF exploits the RealDigital cell architecture• Initial pattern is loaded into a configuration shifter• The pattern first transfers into nonvolatile memory• The pattern is then read from NV to SRAM for
actual cell operation• Leaves ability to reload the NV memory as we
say, “On the Fly”
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CoolRunner-II High Level Architecture
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Behind the Scenes
ConfigurationMemory
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Reconfiguration Process
Nonvolatile Cell
Volatile Cell
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Reconfiguration Process
Blank Blank
Initial Condition
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Reconfiguration Process
Pattern 1 Blank
Nonvolatile Programmed with Pattern 1
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Reconfiguration Process
Pattern 1 Pattern 1
Both programmed with Pattern 1
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Reconfiguration Process
Pattern 2 Pattern 1
Pattern 1 in VolatilePattern 2 in Nonvolatile
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Reconfiguration Process
Pattern 2 Pattern 2
Pattern 2 in Both
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WebPACK ISE5.2i Supports
• iMPACT utility that permits OTF updates • User loads first pattern, then “inits” the part• Second pattern load occurs while first one runs• Init can be issued at any time the user wishes• After 50-100 microseconds, new pattern is running• Its that easy!
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iMPACT Menu
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Selecting the OTF
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OTF Applications
• Uploading FPGA and changing function• Building small tables in Function Blocks• Changing PicoBlaze instructions• Changing keys on stream ciphers• Board level testing
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Configure FPGA then Handle Interrupts
• At power up CPLD configures FPGA (SelectMap JEDEC)
• FPGA active,CPU configures CPLD w. Interrupt JEDEC
• CPLD active, CPU configures CPLD w. SelectMap JEDEC
• System can be power cycled as needed
FPGABitstream CR-II FPGA
CPU
InterruptJEDEC
SelectMapJEDEC
3
JTAG
Select Map
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Small Tables
• CoolRunner-II CPLD has multiple Function Blocks
• Each Function Block has Programmable Logic Array (PLA)
• PLA can also create “miniEPROM” or a table
• Can reprogram OTF• Tables can hold constants,
perform arithmetic, etc.
FB
FB FB
FB
AIM
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Reloading an Instruction Set
See PicoBlaze demonstration to see this in action!
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Re-Keying a Stream Cipher
• Encryption can be done with Linear Feedback Shift Registers (LFSR)
• Seed values and tap points can be changed OTF
• EX-OR Clear Bits to Encrypt• Changing “key” can be done
while the part operates• Fancy LFSRs exist for better
results (see Security presentation for detail)
DQ
LFSRClear Bits
Encrypted Bits
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Board Testing
• Test patterns from CPLD drive/respond to other chips on board
• CPLD is updated via JTAG from off/on board CPU
• CPLD assumes different function when not testing board
PCB
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DataGATE
• Initially defined as power saving feature– Block freely switching input signals– Can turn off clocks
• Other applications arrived– Hot plugging– Debugging– Security
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DataGATE Assertion Rail
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DataGATE Input Pin Details
Data Latch
to AIM
DataGATEAssertion Rail
InputPin
Configuration Bit
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DataGATE Timing
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Power Saving with External Pin Control
AIM
Signal drives lowto pass data
DataGATEAssertion Rail
External signaldrives high toenable data flow
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Using Internal Timer
Signal drives lowto pass data
DataGATEAssertion Rail
External clockto internal timer
Timer
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Using State Machine Controller
Signal drives lowto pass data
DataGATEAssertion RailExternal clock
Cont
rolle
rSignal A
Signal B
State Machine Inputs
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Hot Plugging with DataGATE
PCB with Logic
Rack withCard Slots
Electronics on cardslots use CoolRunner-II with DataGate
DataGATESwitch & Light
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Debugging with DataGATE
Signal drives lowto pass data
DataGATEAssertion RailExternal clock
Deb
ug T
rigge
rSignal A
Signal B
Debug Trigger Inputs
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Security with DataGATE
Signal drives lowto pass data
DataGATEAssertion RailExternal clock
Pas
swor
d Ch
ecke
rPassword
PW Strobe
Security Inputs
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Support
• Standard WebPACK ISE 5.2• CoolRunner-II Design Kit• More details for OTF in XAPP 388• More details for DataGate in XAPP 395• Additional advanced feature details in XAPP 378