Computer Science 37 Lecture 9

8/4/2019 Computer Science 37 Lecture 9

http://slidepdf.com/reader/full/computer-science-37-lecture-9 1/17

1

4.1

Lecture 9

Integer Binary Arithmetic



2

4.2

“Signing” The Result of UnsignedMultiplication and Division

The algorithms we’ll see ahead compute theunsigned productor quotient of two operands. To do signed multiplicationand division, we can record the signs of the operands, dothe unsigned operation and then correct the sign of theresult.

0

1

1

0

XORSA,SB

+ (0)- (1)- (1)

- (1)+ (0)- (1)

- (1)- (1)+ (0)

+ (0)+ (0)+ (0)

SC=Sign(C)result

SB=Sign(B)operand 2

SA=Sign(A)operand 1



3

4.3

Multiplication: In general, if the multiplicandhas n bits and the multiplier has m bits, the

product will have (n+m) bits.

Note what’s going on: we go through each bit inthe multiplier and performing a sequence ofleft-shifts and additions. This is an indicationthat to implement multiplication in hardware,one needs a shift-register and an adder.

What about the signs of the operands and thesign of the result?



4

4.4

An Algorithmfor Multiplication

Both operands are 32-bits long.

What is the size of the product?

How many registers are neededto implement this in hardware?

In general, how manyrepetitions are needed by thisalgorithm?

Done

1. TestMultiplier0

1a. Add multiplicand to product andplace the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions



5

4.5

A Simpler (?) Flowchart for the

Basic Multiplication Algorithm

test

start

0 B

C=C+A

A<<1

B>>1

reps?

done

1 0

no

yes



6

4.6

Another Algorithmfor

Multiplication

Done

1. Test

Multiplier0

1a. Add multiplicand to the left half of the product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1


Yes: 32 repetitions



7

4.7

The Multiplication Hardware for theSecond Multiplication Algorithm

MultiplierShift right

Write

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test



8

4.8

Operations on 2’s ComplementDivision: Trivial when multiplier is a power

of 2 (use a shift-register to do right shifts).Otherwise, we have to define an algorithm,but first, let’s think a bit.

Quotient: How many times does the divisor fitinto the dividend?

Remainder: After a multiple of the divisor hasbeen subtracted from the dividend, what’sleft?



9

4.9

Division:

1000 1001010-1000

1010-1000

10

1001

We do subtractionsand shifts…

Done

Test Remainder

2a. Shift the Quotient register to the left,setting the new rightmost bit to 1

3. Shift the Divisor register right 1 bit

33rd repetition?

Start

Remainder < 0


Yes: 33 repetitions

2b. Restore the original value by addingthe Divisor register to the Remainder

register and place the sum in theRemainder register. Also shift the

Quotient register to the left, setting thenew least significant bit to 0

1. Subtract the Divisor register from theRemainder register and place the

result in the Remainder register

Remainder > 0–

Divisor: 2n bitsDividend: 2n bitsQuotient: n bitsRemainder: 2n bits



10

4.10

A Simpler (?) Flowchart for theBasic Division Algorithm

start

Q<<1(1)

(0)D>>1

n+1 reps?

done

no

yes

R=R-D

R=R+DQ<<1(0)

yes no012

=−n R

divisor 000…0

000…0 dividend000…0

D =

R =Q =

2n bits

n bits

1000 1001010-1000

1010-1000

10

1001



11

4.110000 00010000 00010011D>>1

0000 00010000 00100011R0=0: Q<<1,Q0=1

0000 00110000 00100001D>>1

0000 00110000 01000001R0=0: Q<<1,Q0=1

0000 01110000 01000000D>>1

0000 01110000 10000000R0=1: +D,Q<<1,Q0=0

0000 01110000 10000000D>>1

0000 01110001 00000000R0=1: +D,Q<<1,Q0=0

0000 01110001 00000000D>>10000 01110010 00000000R0=1: +D,Q<<1,Q0=0

0000 00010000 00100001R=R-D

0000 00110000 01000000R=R-D

1111 11110000 10000000R=R-D

1111 01110001 00000000R=R-D

1110 01110010 00000000R=R-D

0000 01110010 00000000Initialize

RemainderDivisorQuotientStepIteration

72

n=4



12

4.12

The Division Hardware

64-bit ALU

Controltest

QuotientShift left

RemainderWrite

DivisorShift right

64 bits

64 bits

32 bits



13

4.13

“Signing” The Remainder

Remainder+∗= Divisor Quotient Dividend

)1()23(27

−+∗−=−

)1()24(27

++∗−=−

To avoid such confusion, we postulate:)()Remainder( Dividend SignSign =

)()( Divisor Sign Dividend Sign = )()( Divisor Sign Dividend Sign ≠

Quotient Quotient −=

)()Remainder( Dividend SignSign = )()Remainder( Dividend SignSign =

Quotient Quotient =



14

4.14

Interlude

Question: Given a positive n-bit number A, how can onecompute the two’s complement representation of (-A) withthe hardware that you know?

subtraction

0

A

-A



15

4.15

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection Overflow

a.

b.

A Few More Detailsabout the ALU

1++=−= babacRemember that in 2’s complement:

bac +=makeTo

bac −=makeTo

OP=10CarryIn=0Binvert=0

OP=10CarryIn=1Binvert=1

Bnegate=0

Bnegate=1



16

4.16Set

a31

0

ALU0 Result0

CarryIn

a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Binvert

CarryIn

Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn



17

4.17

Seta31

0

Result0a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

ALU ResultZero

Overflow

a

b

ALU operation

CarryOut

Computer Science 37 Lecture 9

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