VeriLogger Pro, by SynaptiCAD, is a complete design and verification environment for ASIC and FPGA designers. It contains a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market. Test vectors can be imported or exported from logic analyzers, pattern generators, and 3rd party VHDL, Verilog, and SPICE simulators for reuse. Simulation features include waveform viewing, optimized gate-level simulation, single-step debugging, point- and-click breakpoints, hierarchical browser for project management, and batch execution. Complete ASIC and FPGA design Environment In a typical design of a large ASIC, each contributing engineer can use a VeriLogger to develop and simulate their portion of the chip. After each portion has been synthesized and checked, the entire integrated design can be rapidly simulated and verified using VeriLogger with its optimized gate level simulation engine activated. VeriLogger interfaces to synthesis tools, place-and-route tools, and all vendor Verilog libraries. VeriLogger supports design flows using Actel, Altera, Lattice, Lucent, Quicklogic, Vantis , and Xilinx devices with full timing verification using SDF back-annotated simulation models. Graphical Test Bench Generation VeriLogger can automatically generate test bench code for your design models. Using the built-in timing diagram editor, just draw the stimulus waveforms and VeriLogger will write the test bench and simulate it with your design models. VeriLogger also includes an instant- feedback simulation mode in which any change to the design code or the waveform stimulus vectors results in an automatic re-simulation. This mode is especially useful for quickly verifying the functionality of small design blocks, making it possible to perform true unit- level testing of designs. Cut Design Costs By A Factor of 10 If you've wanted to move up to the latest design methodologies, but have hesitated because of the high entry costs, VeriLogger is your answer. If you've already moved to Verilog, but haven't been able to afford to equip all the members of your team with their own simulators, VeriLogger is your answer too. VeriLogger is 100% compatible with Verilog-XL and integrates seamlessly into an XL environment.
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
VeriLogger Pro, by SynaptiCAD, is a complete design and verification environment for ASICand FPGA designers. It contains a new type of Verilog simulation environment that combinesall the features of a traditional Verilog simulator with the most powerful graphical test vectorgenerator on the planet. Model testing is so fast in VeriLogger Pro that you can performtrue bottom-up testing of every model in your design, a critical step often skipped in therace to market. Test vectors can be imported or exported from logic analyzers, patterngenerators, and 3rd party VHDL, Verilog, and SPICE simulators for reuse. Simulation featuresinclude waveform viewing, optimized gate-level simulation, single-step debugging, point-and-click breakpoints, hierarchical browser for project management, and batch execution.
Complete ASIC and FPGA design Environment
In a typical design of a large ASIC, each contributing engineer can use a VeriLogger todevelop and simulate their portion of the chip. After each portion has been synthesizedand checked, the entire integrated design can be rapidly simulated and verified usingVeriLogger with its optimized gate level simulation engine activated. VeriLogger interfacesto synthesis tools, place-and-route tools, and all vendor Verilog libraries. VeriLogger supportsdesign flows using Actel, Altera, Lattice, Lucent, Quicklogic, Vantis , and Xilinx devices withfull timing verification using SDF back-annotated simulation models.
Graphical Test Bench GenerationVeriLogger can automatically generate test bench code for your design models. Using thebuilt-in timing diagram editor, just draw the stimulus waveforms and VeriLogger will writethe test bench and simulate it with your design models. VeriLogger also includes an instant-feedback simulation mode in which any change to the design code or the waveform stimulusvectors results in an automatic re-simulation. This mode is especially useful for quicklyverifying the functionality of small design blocks, making it possible to perform true unit-level testing of designs.
Cut Design Costs By A Factor of 10If you've wanted to move up to the latest design methodologies, but have hesitated becauseof the high entry costs, VeriLogger is your answer. If you've already moved to Verilog, buthaven't been able to afford to equip all the members of your team with their own simulators,VeriLogger is your answer too. VeriLogger is 100% compatible with Verilog-XL and integratesseamlessly into an XL environment.
Project WindowThe Project Window is used to investigate the hierarchical structure of the Verilog components,navigate source code, and set watches on signals. Each node in the tree has a context-sensitive pop-up menu that can be opened by right clicking on the node.
Show hierarchical structure of Verilog components
View signal direction, type, state
Set watches on ports, components, and signals
Context sensitive pop-up menus
Top-level component in project shown with triple brackets
Waveform ViewingEnvironmentVeriLogger's diagramwindow is used todisplay simulation resultsand to provide adrawing environment forthe graphical test benchgeneration.
Purple signals aresimulation results
Black signals arestimulus that drives thesimulation
Markers can be usedto hide sections ofsimulation for easierdocumentation
Click in timeline todisplay all waveformvalues at a particulartime
Go to Signaldeclaration in aneditor window
Simulation Button BarThe simulation and debugging functions in VeriLogger are accessed from the simulation button barlocated at the top of the main window. One of the unique features of VeriLogger is that it has twosimulation modes: Auto Run and Debug Run. The active simulation mode is displayed on the leftmost button on the simulation button bar. In Debug Run mode, simulations are started only whenthe user presses the Run or Single Step buttons (similar to a standard Verilog simulator). In Auto Runmode the simulator will automatically run a simulation each time a waveform is drawn or changedin the Diagram window. This mode makes it easy to quickly test small modules and do bottom-up testing.
Stop Simulation
Single Step
Start Simulation
Debug or Auto Run
Compiling auto-generated top level module file: C:\SynaptiCAD\Examples\add4.vFinished Phase IIEntering Phase III...Finished Phase IIIHighest level modules: syncad_topFinding handle to syncad_top.sumFinding handle to syncad_top.c_outCompile Complete.Running...0 Errors, 0 WarningsCompile time = 0.00000, Load time = 0.03000, Execution time = 0.01000
Normal exitINS Row: 8 Line: 15 Col: 1
Report - C:\SYNAPT~1\verilog.log
// VeriLogger Pro: Basic Verilog Simulation
C:\SynaptiCAD\Examples\add4.v//*******************************************
//*******************************************// (Tutorial 7 in SynaptiCad Series)
//** Full Adder ************************module fulladder(sum, c_out, x, y, c_in);output sum, c_out;input x, y, c_in;
wire a, b, c;
xor (a, x, y);xor (sum, a, c_in);
and (b, x, y);and (c, a, c_in);or (c_out, c, b);
output [3:0] sum;output c_out;input [3:0] x, y;input c_in;
wire cl, c2, c3;
fulladder fa0(sum[0], c1, x[0], y[0], c_in);
INS
//** 4-Bit Adder *****************************module FourBitAdder:sum, c_out, x, y, c_in);
endmodule
fulladder fa0(sum[0], c2, x[1], y[1], c1);fulladder fa0(sum[0], c3, x[2], y[2], c2);
Row: 17 Line: 17 Col: 20
sum[3:0]
c_out
x[3:0]
y[3:0]
c_in
0ns 50ns 100ns 150ns 550ns 585.402
4 6 7 0
‘h1 ‘h2
‘h3 ‘h4
‘hf
‘h0
‘h1 ‘h2
‘h3 ‘h4
‘hf
‘h0
F 4 7 0
‘hf
‘h0
F
0
585.0ns 0.000ps
Add SignalAdd Clock
Add BusAdd Spacer
DelayHold
Setup SampleMarkerText
Zoom InZoom Out
Zoom FullZoom Range
INVal WHI WLO HEXVALTRILOWHIGH
Diagram - simulation1.tim*
Project HierachyProject - add4test.hpj*
Compiling auto-generated top level module file: C:\SynaptiCAD\untitled1Tim.vFinished Phase IIEntering Phase III...Finished Phase IIIHighest level modules: syncad_topFinding handle to syncad_top.sumFinding handle to syncad_top.c_outCompile Complete.Running...0 Errors, 0 WarningsCompile time = 0.00000, Load time = 0.03000, Execution time = 0.01000
Normal exitINSRow: 8 Line: 15 Col: 1
Report - C:\SYNAPT~1\verilog.logDirection Type State
C:\SynaptiCAD\Examples\add4.v
Ports
Ports
Portssumc_outxyc_in
Signalsabc
Signalsabc
fulladder
Componentsfa0fa1fa2fa3
Signalsc1c2c3
<<< FourBitAdder >>>
sum[3:0]c_outx[3:0]
c_iny[3:0]
outputoutputinputinputinput
outputoutputinputinputinput
[] wire
[] wire[] wire
wire
wire
wirewirewire
wirewirewire
wirewirewirewirewire
wirewirewire
fulladderfulladderfulladderfulladder
Left click & drag to zoom in. Left click & drag with <CTRL> key to lock copy. Right click to zoom out. Simulation Good
0
VeriLogger Pro
Report View Options Window HelpSimulateEditorProjectLibrariesBusEditExportFile
Debug Run
Sim Dgm
S SS SSim Diagram & Project Verilog
verilog.log waveperl.log Breakpoints Errors Differences Grep add4.v
SETALL#1000 $stop;
Cyclize Selected Signal(s)
Hide Selected Signal(s)Edit Selected Signal(s)Go to Declaration
Group Bus <-> Virtual BusEdit Waveform Edges...
Delete Selected Signal(s)
Add Diagram to ProjectSaveSave As...SaveSave As...
CopyCut
FindFind in Files...
SaveSave AsRenamePrint
Add to ProjectAdd/Remove BreakpointOpen File
Jump to Line Number...Text Slide In...Text Slide Out...Insert Diagram Calls...
PasteUndo
Ctrl-CCtrl-X
Ctrl-F
Ctrl-S
Ctrl-P
Ctrl-O
Ctrl-G
Ctrl-VCtrl-Z
CopyCut
Ctrl-CCtrl-X
Add HDL File(s)...
Instantiate in TBenchWatch Component and Sub-componentWatch Component
Add Timing Diagram(s)...Expand ItemCopy TestBencher Template File...
New ProjectOpen Project...Save ProjectSave Project As...
Design Flow IntergrationVeriLogger smoothly integrates into existing Verilog design flows. It also supports customizationfeatures like a dynamic PLI interface for intergration with 3rd party tools and C / C++ basedsimulation models The package includes a bundled command-line simulator for batchexecution enviroments. The command-line simulator supports de facto standard commandline options and debug commands, so there’s no relearning for experienced Verilog-XLusers. And it includes a built-in Perl interpreter for writing scripts to automate common tasksin your design flow. With the built-in interpreter, you can even execute Perl scripts directlyfrom your simulation code!
Report WindowThe Report windowmanages several tabwindows which areimportant to simulationand debugging.
Simulation log filecontains allinformationgenerated by thesimulator, such ascompiler messages,and all user-generated messagesfrom $display tasksand traces are sentto this file.
Lists the breakpointsin the current project
Hyper-linked list ofsimulation errors
Comparison Button BarGraphically display the differences between compared waveforms for two timing diagramsor any set of signals. This feature is exceptionally useful when comparing two differentsimulation runs, as well as for comparing logic analyzer waveforms to a simulation run.Supports edge tolerance settings and clocked comparisons.
Compare Signals
Move to nextdifference
Editor WindowVeriLogger's editorwindows are anintegrated part of thesimulation environment. Double clicking in the Project Tree, Errors, or Breakpoints windowswill open an editor and display the relevant source code. The editor windows are also usedto display the current execution line for single-step debugging.
Display current execution line during debugging
Point and Click Break Points
Color-syntax editing
Search and Find in Files
Block Text Features
Context Sensitive Pop-up Menu
Compiling auto-generated top level module file: C:\SynaptiCAD\Examples\add4.vFinished Phase IIEntering Phase III...Finished Phase IIIHighest level modules: syncad_topFinding handle to syncad_top.sumFinding handle to syncad_top.c_outCompile Complete.Running...0 Errors, 0 WarningsCompile time = 0.00000, Load time = 0.03000, Execution time = 0.01000
Normal exitINS Row: 8 Line: 15 Col: 1
Report - C:\SYNAPT~1\verilog.log
// VeriLogger Pro: Basic Verilog Simulation
C:\SynaptiCAD\Examples\add4.v//*******************************************
//*******************************************// (Tutorial 7 in SynaptiCad Series)
//** Full Adder ************************module fulladder(sum, c_out, x, y, c_in);output sum, c_out;input x, y, c_in;
wire a, b, c;
xor (a, x, y);xor (sum, a, c_in);
and (b, x, y);and (c, a, c_in);or (c_out, c, b);
output [3:0] sum;output c_out;input [3:0] x, y;input c_in;
wire cl, c2, c3;
fulladder fa0(sum[0], c1, x[0], y[0], c_in);
INS
//** 4-Bit Adder *****************************module FourBitAdder:sum, c_out, x, y, c_in);
endmodule
fulladder fa0(sum[0], c2, x[1], y[1], c1);fulladder fa0(sum[0], c3, x[2], y[2], c2);
Row: 17 Line: 17 Col: 20
sum[3:0]
c_out
x[3:0]
y[3:0]
c_in
0ns 50ns 100ns 150ns 550ns 585.402
4 6 7 0
‘h1 ‘h2
‘h3 ‘h4
‘hf
‘h0
‘h1 ‘h2
‘h3 ‘h4
‘hf
‘h0
F 4 7 0
‘hf
‘h0
F
0
585.0ns 0.000ps
Add SignalAdd Clock
Add BusAdd Spacer
DelayHold
Setup SampleMarkerText
Zoom InZoom Out
Zoom FullZoom Range
INVal WHI WLO HEXVALTRILOWHIGH
Diagram - simulation1.tim*
Project HierachyProject - add4test.hpj*
Compiling auto-generated top level module file: C:\SynaptiCAD\untitled1Tim.vFinished Phase IIEntering Phase III...Finished Phase IIIHighest level modules: syncad_topFinding handle to syncad_top.sumFinding handle to syncad_top.c_outCompile Complete.Running...0 Errors, 0 WarningsCompile time = 0.00000, Load time = 0.03000, Execution time = 0.01000
Normal exitINSRow: 8 Line: 15 Col: 1
Report - C:\SYNAPT~1\verilog.logDirection Type State
C:\SynaptiCAD\Examples\add4.v
Ports
Ports
Portssumc_outxyc_in
Signalsabc
Signalsabc
fulladder
Componentsfa0fa1fa2fa3
Signalsc1c2c3
<<< FourBitAdder >>>
sum[3:0]c_outx[3:0]
c_iny[3:0]
outputoutputinputinputinput
outputoutputinputinputinput
[] wire
[] wire[] wire
wire
wire
wirewirewire
wirewirewire
wirewirewirewirewire
wirewirewire
fulladderfulladderfulladderfulladder
Left click & drag to zoom in. Left click & drag with <CTRL> key to lock copy. Right click to zoom out. Simulation Good
0
VeriLogger Pro
Report View Options Window HelpSimulateEditorProjectLibrariesBusEditExportFile
Debug Run
Sim Dgm
S SS SSim Diagram & Project Verilog
verilog.log waveperl.log Breakpoints Errors Differences Grep add4.v
SETALL#1000 $stop;
Cyclize Selected Signal(s)
Hide Selected Signal(s)Edit Selected Signal(s)Go to Declaration
Group Bus <-> Virtual BusEdit Waveform Edges...
Delete Selected Signal(s)
Add Diagram to ProjectSaveSave As...SaveSave As...
CopyCut
FindFind in Files...
SaveSave AsRenamePrint
Add to ProjectAdd/Remove BreakpointOpen File
Jump to Line Number...Text Slide In...Text Slide Out...Insert Diagram Calls...
PasteUndo
Ctrl-CCtrl-X
Ctrl-F
Ctrl-S
Ctrl-P
Ctrl-O
Ctrl-G
Ctrl-VCtrl-Z
CopyCut
Ctrl-CCtrl-X
Add HDL File(s)...
Instantiate in TBenchWatch Component and Sub-componentWatch Component
Add Timing Diagram(s)...Expand ItemCopy TestBencher Template File...
New ProjectOpen Project...Save ProjectSave Project As...
Integrating Hardware and Simulation Test Bench DevelopmentVeriLogger Pro acts as a two way translator between simulation and hardware environments,providing you with an integrated platform for test vector creation, analysis of results, anddetection of elusive timing problems. VeriLogger Pro reduces verification time for bothsimulation models and hardware prototypes by taking advantage of the strengths offeredby each environment.
VeriLogger verifies Hardware PrototypesVeriLogger enables you to leverage the work done during the design phase of your systemto simplify the development of a hardware test environment. VeriLogger can take waveformsgenerated during simulation of Verilog test benches to create pattern generator stimulusfiles, drastically reducing the time to create a prototyping environment. VeriLogger Pro canalso verify proper operation of hardwareby comparing logic analyzer data tosimulation results. Automatedcomparison guarantees a rigorous checkof each data point, ensuring thedetection of “small impact” errors thatare easily missed during visual inspectionof the waveforms. Another benefit ofcombining a simulation environment witha hardware prototyping setup is theability to generate timing analysisreports, to detect subtle setup and holdtiming violations in the hardwareprototype.
Hardware used to Create Verilog Test BenchesJust as design data can be transferred into the test domain to help verify hardware, thereverse process can be applied to the design and simulation of new systems. Most designsneed to interface with existing hardware, but simulation models are frequently not availablefor that hardware. Waveforms from the existing hardware can be captured with a logicanalyzer and converted to HDL test bench code or SPICE stimulus and used to test the newsystem. Instead of spending weeks developing a test bench, you can capture real worldstimulus and begin testing within minutes of capturing the data. Existing hardware can alsobe used to verify that a next-generation system's interface is compatible with the olderhardware.
“ I’m impressed with SynaptiCAD, they have a great simulator at a very accessible price. I foundit to be 100% Cadence Verilog-XL compatible. My test case simulated the same RTL code from abig FPGA (Xilinx Virtex-300/600/1000 and an Altera 10k150) in Verilog XL and in VeriLogger withno problems. Even on a machine with only 128M of RAM, VeriLogger performed well. The SynaptiCADstaff was very quick to answer any questions and I have always found them to be very responsiveand helpful. “
Gill RomeroPrincipal Consultant, ASIC Alliance Corp.
Site:www.syncad.comE-mail:[email protected]:540 953 3390Sales:800 804 7073Fax:540 953 3078520 Prices Fork Rd. Suite C4Blacksburg, Virginia 24060
Related Documents
