Page 1
Combinational Logic Gates
in CMOS
Prof. Kaushik Roy
@ Purdue Univ.
References:
Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey © UCB
Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed.,
N. H. E. Weste and K. Eshraghian
Page 2
Combinational vs. Sequential Logic
Prof. Kaushik Roy
@ Purdue Univ.
Combinational Sequential
State
Out = f(In) Out = f(In, State)
State is related to previous inputs
Stored in registers, memory etc
Page 3
Overview
Prof. Kaushik Roy
@ Purdue Univ.
• Static CMOS
– Complementary CMOS
– Ratioed Logic
– Pass Transistor/Transmission Gate Logic
• Dynamic CMOS Logic
– Domino
– np-CMOS
Page 4
Static CMOS Circuit
Prof. Kaushik Roy
@ Purdue Univ.
• At every point in time (except during the switching
transients) each gate output is connected to either
VDD or VSS via a low-resistive path
• The outputs of the gates assume at all times the
value of the Boolean function, implemented by the
circuit
• In contrast, a dynamic circuit relies on temporary
storage of signal values on the capacitance of high
impedance circuit nodes
Page 5
Digital Gates Fundamental Parameters
Prof. Kaushik Roy
@ Purdue Univ.
• Area and Complexity
• Performance
• Power Consumption
• Robustness and Reliability
Page 6
What Can Go Wrong in CMOS Logic?
Prof. Kaushik Roy
@ Purdue Univ.
• Incorrect or insufficient power supplies
• Power supply noise
• Noise on gate input
• Faulty connections between transistors
• Clock frequency too high or circuit too slow
Complementary CMOS is pretty
safe against these
Page 7
How about Ratioed or Dynamic Logic?
Prof. Kaushik Roy
@ Purdue Univ.
• All the previous and
• Incorrect ratios in ratioed logic
• Charge sharing in dynamic logic
• Incorrect clocking in dynamic logic
Page 8
Complementary CMOS
Prof. Kaushik Roy
@ Purdue Univ.
PUN
PDN
in1 in2 in3
in1 in2 in3
VDD
VSS
F = G
NMOS only
PMOS only
PUN and PDN are dual networks
Page 9
NMOS Transistors in Series/Parallel Connection
Prof. Kaushik Roy
@ Purdue Univ.
• Transistors can be thought as a switch controlled by
its gate signal
• NMOS switch closes when switch control input is
high
X Y
A B
X = Y if A = 1 and B = 1, i.e., AB = 1
• NMOS passes a strong 0 but a weak 1
X Y
A
B X = Y if A = 1 or B = 1, i.e., A + B = 1
Page 10
NMOS Transistors in Series/Parallel Connection
Prof. Kaushik Roy
@ Purdue Univ.
• Connect Y to GND
X Y
A B
X = 0 if A = 1 and B = 1, i.e., A.B = 1
• Implement the complement of PDN
X Y
A
B X = 0 if A = 1 or B = 1, i.e., A + B = 1
X = A.B
X = A + B
Page 11
PMOS Transistors in Series/Parallel Connection
Prof. Kaushik Roy
@ Purdue Univ.
• PMOS switch closes when switch control input is low
X Y
A B X = Y if A = 0 and B = 0
or A + B = 1
or A.B = 1
• PMOS passes a strong 1 but a weak 0
X Y
A
B X = Y if A = 0 or B = 0
A.B = 1
A + B = 1
Page 12
PMOS Transistors in Series/Parallel Connection
Prof. Kaushik Roy
@ Purdue Univ.
• Connect Y to VDD
X Y
A B
X = 1 if A = 0 and B = 0
• Combine series PDN and parallel PUN or parallel
PDN and series PUN to complete the logic design to
output good 1 and 0
X Y
A
B X = 1 if A = 0 or B = 0
X = A + B = A.B
X = A.B = A + B
Page 13
Complementary CMOS Logic Style Construction
Prof. Kaushik Roy
@ Purdue Univ.
• PUN is the DUAL of PDN (can be shown using
DeMorgan’s Theorems)
BABA
BAAB
• The complementary gate is inverting
– Implements NAND, NOR, …
– Non-inverting boolean function needs an inverter
,...),,(,...),,( 321321 inininFinininG
Page 14
The NAND Circuit
Prof. Kaushik Roy
@ Purdue Univ.
B
A
BA
1 1
1 0
0 1
0
1
A
B
B
Out
A
BA.
,...),,(,...),,( 321321 inininFinininG
BAG .:GND toconnected PDN
ABBAFVDD : toconnected PUN
Page 15
The NOR Circuit
Prof. Kaushik Roy
@ Purdue Univ.
B
A
1 0
0 0
0 1
0
1
A
B
A B
A + B
A . B
BA Output
Page 16
Example Gate: COMPLEX CMOS GATE
Prof. Kaushik Roy
@ Purdue Univ.
VDD
A
B
C
D
D
A
B C
OUT = D + A• (B+C)
Page 17
4-input NAND Gate
Prof. Kaushik Roy
@ Purdue Univ.
In1 In2 In3 In4
VDD
GND
Out ln2
ln1
ln2
Out
ln1
ln4
ln3
ln4 ln3
Page 18
Standard Cell Layout Methodology
Prof. Kaushik Roy
@ Purdue Univ.
VDD
VSS
Well
signalsRouting Channel
metal1
polysilicon
Page 19
Two Versions of (a+b).c
Prof. Kaushik Roy
@ Purdue Univ.
a c b a b c
xx
GND
VDDVDD
GND
(a) Input order {a c b} (b) Input order {a b c}
Page 20
Logic Graph
Prof. Kaushik Roy
@ Purdue Univ.
VDD
c
a
x
b
ca
b
GND
x
VDDx
c
b a
i
j
i
j
PDN
PUN
Page 21
Consistent Euler Path
Prof. Kaushik Roy
@ Purdue Univ.
{a b c}
Page 22
Example: x = ab+cd
Prof. Kaushik Roy
@ Purdue Univ.
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}
b
Page 23
Properties of Complementary CMOS Gates
Prof. Kaushik Roy
@ Purdue Univ.
• High noise margin
– VOH and VOL are at VDD and GND, respectively
• No static power consumption
– In steady state, no direct path between VDD and VSS
• Comparable rise and fall times under appropriate
scaling of PMOS and NMOS transistors
Page 24
Transistor Sizing
Prof. Kaushik Roy
@ Purdue Univ.
• For symmetrical response (dc, ac)
• For performance
• Input dependent
• Focus on worst-case
Page 25
Propagation Delay Analysis - The Switch Model
Prof. Kaushik Roy
@ Purdue Univ.
Page 26
Analysis of Propagation Delay
Prof. Kaushik Roy
@ Purdue Univ.
• Assume CL dominates
• Assume Rn = Rp = resistance
of minimum sized NMOS
inverter
• For tpLH
– Worst case when only one
PMOS pulls up the output node
– tpLH RpCL
• For tpHL
– Worst case when two NMOS in
series
– tpHL 2RnCL
Page 27
3-Input NAND Gate
Prof. Kaushik Roy
@ Purdue Univ.
inc out
inb
ina
rise-time: 1 transistor (simple)
fall-time: 3 transistor in series
for linear approximation: take 3xRon
Page 28
3-Input NAND Gate
Prof. Kaushik Roy
@ Purdue Univ.
inc out
inb
ina
If mn = 3mp
for equal fall and rise time:
Take Wn = Wp
If mn = 2mp
for equal fall and rise time:
Take Wn = (3/2)Wp
Page 29
Design for Worst Case
Prof. Kaushik Roy
@ Purdue Univ.
Page 30
3-input NAND Gate with Parasitic Capacitors
Prof. Kaushik Roy
@ Purdue Univ.
inc
out
inb
ina
Cp+load
Ca
Cb
Cc
P1 P2 P3
N3
N2
N1
Page 31
Worst Case Approximation Using Lumped RC Model
Prof. Kaushik Roy
@ Purdue Univ.
))(()( 321 loadpcbaNNN
pulldownpulldowndf
CCCCRRR
CRt
(We ignore the constant term 0.69 or 1.22)
Page 32
Distributed RC Effects
Prof. Kaushik Roy
@ Purdue Univ.
C C C C C
R R R R R
2
.
2
)1( nCnRnnRCtn
Worst case under lumped model: tn = nR.nC
Page 33
Effect of Fan-In and Fan-Out on Delay
Prof. Kaushik Roy
@ Purdue Univ.
ln2
ln1
ln2
Out
ln1
ln4
ln3
ln4 ln3
• Fan-out: number of gates connected
– 2 gate capacitance per fan-out
• Fan-in: number of inputs to a gate
– Quadratic effect due to increasing
resistance and capacitance
FOaFIaFIatd 3
2
21
Page 34
tp as a function of Fan-In
Prof. Kaushik Roy
@ Purdue Univ.
1 3 5 7 9fan-in
0.0
1.0
2.0
3.0
4.0
t p (
nsec)
tpHL
tp
tpLHlinear
quadratic
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
Page 35
Progressive Sizing
Prof. Kaushik Roy
@ Purdue Univ.
• When parasitic capacitance
is significant (e.g., when fan-
in is large), needs to
consider distributed RC
effect
• Increasing the size of M1 has
the largest impact in terms of
delay reduction
• M1 > M2 > M3 > … > MN
ln3
lnN
Out
ln1
ln2
M1
M2
M3
MN
Page 36
Delay Optimization by Transistor Ordering
Prof. Kaushik Roy
@ Purdue Univ.
ln3
lnN
Out
ln1
ln2
M1
M2
M3
MN
Critical signal next to supply
Critical path
ln3
lnN
Out
ln1
ln2
M1
M2
M3
MN
Critical signal next to output
Critical path