Clocked Synchronous State Machine Design •Design a clocked synchronous state machine with two inputs, A and B and a single output Z that is equal to 1 if: –A has the same value at each of the two previous clock ticks, or –B has been 1 since the last time that the first condition was true. •Otherwise Z should be 0.
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Clocked Synchronous State Machine Design Set...Clocked Synchronous State Machine Design •Design a clocked synchronous state machine with two inputs, A and B and a single output Z
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Clocked Synchronous State Machine Design
•Design a clocked synchronous state machine with two inputs, A and B and a single output Z that is equal to 1 if:–A has the same value at each of the two previous clock ticks, or–B has been 1 since the last time that the first condition was true.
•Otherwise Z should be 0.
Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
Output00 01 11 10 Z
Initial State INIT 0
S*
MeaningInput - AB
S
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 0Got a 1 on A A1 0
S*
MeaningInput - AB
S
Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Got two equal A OK
S*
MeaningInput - AB
S
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Got two equal A OK ? OK OK ? 1
S*
MeaningInput - AB
S
Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
• Try the sequence (A,B) = (1,0), (1,0), (1,1), (0,0).
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Two equal, A=0 last OK0 OK0 OK0 OK1 A1 1Two equal, A=1 last OK1 A0 OK0 OK1 OK1 1
S*
MeaningInput - AB
S
State Minimization
• Equivalence:– For a given input, two states are
equal if their outputs are the same, and their next state is the same or an equivalent one.
Output0 1 Z
A A B 0B C D 0C A D 0D E F 1E A F 1F G F 1G A F 1
S*
Input - XS
State Assignment• Procedures concerned with
methods for assigning binary values to states in such a way as to reduce the cost of the combinational circuit that drives the flip-flops.
• Methods:– Choose an initial coded state
which the machine can easily be forced to at reset.
– Minimize the number of state variables that change on each transition.
– Maximize the number of state variables that do not change
State Assignment• Methods:– Exploit symmetries by assigning
state variables differing only in one bit to both states or group of states.
– If there are unused states, then choose the best of the available state-variable combinations to achieve the foregoing goal.
– Decompose the set of state variables into individual bits or fields, with well defined meaning.
– Consider using more than the minimum number of state variables to make decomposed assignments possible.
State Assignment
Assignment Table 7-7Possible state assignments for the state machine in Table 7-6.
State Name
Simplest Q1–Q3
Decomposed Q1–Q3
One-hot Q1–Q5
Almost One-hot Q1–Q4
INIT 000 000 00001 0000
A0 001 100 00010 0001
A1 010 101 00100 0010
OK0 011 110 01000 0100
OK1 100 111 10000 1000
• Unused states:– Minimal risk – assumes that it is
possible for the state machine to get into one unused or illegal state.
– Minimal cost – assumes that the state machine will never enter an unused state.
Designing State Machines Using State Diagrams
• State-diagram design is simpler but it is more prone to errors.– State table is an exhaustive listing
of the next states for each state/input combination. No ambiguity is possible.
– When constructing a state diagram there is no guarantee that the transition expressions written on the arcs leaving a particular state, cover all input combination exactly once.
Designing State Machines Using State Diagrams
• Design a state machine to control the tail lights of a 1965 Ford Thunderbird. The tail lights are composed of three light on each side which operate for the turns in the manner shown in the picture below.
• Q2 identifies LEFT or RIGHT turn.• HAZ state of 100.
Table 7 -16State assignment for T-bird tail-lights state machine.
State Q2 Q1 Q0
IDLE 0 0 0
L1 0 0 1
L2 0 1 1
L3 0 1 0
R1 1 0 1
R2 1 1 1
R3 1 1 0
LR3 1 0 0
Designing State Machines Using State Diagrams
S Q2 Q1 Q0 Transition Expression S∗ Q2∗ Q1∗ Q0∗ Table 7-17 Transition list for T-bird tail-lights state machine.
IDLE 0 0 0 (LEFT + RIGHT + HAZ)′ IDLE 0 0 0
IDLE 0 0 0 LEFT ⋅ HAZ′ ⋅ RIGHT′ L1 0 0 1
IDLE 0 0 0 HAZ + LEFT ⋅ RIGHT LR3 1 0 0
IDLE 0 0 0 RIGHT ⋅ HAZ′ ⋅ LEFT′ R1 1 0 1
L1 0 0 1 HAZ′ L2 0 1 1
L1 0 0 1 HAZ LR3 1 0 0
L2 0 1 1 HAZ′ L3 0 1 0
L2 0 1 1 HAZ LR3 1 0 0
L3 0 1 0 1 IDLE 0 0 0
R1 1 0 1 HAZ′ R2 1 1 1
R1 1 0 1 HAZ LR3 1 0 0
R2 1 1 1 HAZ′ R3 1 1 0
R2 1 1 1 HAZ LR3 1 0 0
R3 1 1 0 1 IDLE 0 0 0
LR3 1 0 0 1 IDLE 0 0 0
Feedback Sequential Circuits
• Fundamental mode circuits:– Most common example of
feedback sequential circuits.– Inputs are not normally allowed
to change simultaneously.• Feedback sequential circuits
may be Mealy or Moore circuits.
• A circuit with n feedback loops has n binary state variables and 2n states.
Feedback Sequential Circuits
• Analysis:– Assumes that input changes occur one
at a time to allow enough time between successive changes for the circuit to settle into a internal stable state.
– Break the feedback loops so that the next value stored in each loop can be predicted as a function of the circuit inputs and the current value stored in all loops.
• Simultaneous input changes don’t always cause unpredictable behavior.
Races• A race is said to occur when multiple
internal variables change state as a result of a single input changing state.
• Noncritical race: the final state does not depend on the order in which the state variables change.
• Starting at state 011/00 change CLK to 1.
CLK D
Y1 Y2 Y3 00 01 11 10
000 010 010 000 000
001 011 011 000 000
010 010 110 110 000
011 011 111 111 000
Y1∗ Y2∗ Y3∗
100 010 010 111 111
101 011 011 111 111
110 010 110 111 111
111 011 111 111 111
Races• Critical race: the final state depends on the
order in which the state variables change.• State 010/10 has been changed from 000 to
110.• Try starting at state 011/00 change CLK to
1 and see what state you end up at.
CLK D
Y1 Y2 Y3 00 01 11 10
000 010 010 000 000
001 011 011 000 000
010 010 110 110 110
011 011 111 111 000
Y1∗ Y2∗ Y3∗
100 010 010 111 111
101 011 011 111 111
110 010 110 111 111
111 011 111 111 111
State Tables and Flow Tables
• Once it has been determined that a transition table does not have any critical races, the state-variable combinations can be named and outputs can be determined to obtain a state/output table.
CLK D
S 00
S0 S2 , 01
S1 S3 , 10
S2 S2 , 01
S3 S3 , 10
S* , Q QN
S4 S2 , 01
S5 S3 , 10
S6 S2 , 01
S7 S3 , 10
01
S2 , 01
S3 , 10
S6 , 01
S7 , 10
S2 , 01
S3 , 10
S6 , 01
S7 , 10
11
S0 , 01
S0 , 10
S6 , 01
S7 , 10
S7 , 11
S7 , 10
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
S0 , 01
S7 , 11
S7 , 10
S7 , 11
S7 , 10
CLK D
Y1 Y2 Y3 00 01 11 10
000 010 010 000 000
001 011 011 000 000
010 010 110 110 000
011 011 111 111 000
Y1∗ Y2∗ Y3∗
100 010 010 111 111
101 011 011 111 111
110 010 110 111 111
111 011 111 111 111
State Tables and Flow Tables
• Flow table eliminates:– Rows for unused internal states (states
that are stable for no input combination).– Next state entries for total states that
cannot be reached from a stable total state as the result of a single input change.
• It eliminates multiple hops and show only the ultimate destination of each transition.
CLK D
S 00
S0 S2 , 01
S1 S3 , 10
S2 S2 , 01
S3 S3 , 10
S* , Q QN
S4 S2 , 01
S5 S3 , 10
S6 S2 , 01
S7 S3 , 10
01
S2 , 01
S3 , 10
S6 , 01
S7 , 10
S2 , 01
S3 , 10
S6 , 01
S7 , 10
11
S0 , 01
S0 , 10
S6 , 01
S7 , 10
S7 , 11
S7 , 10
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
S0 , 01
S7 , 11
S7 , 10
S7 , 11
S7 , 10
CLK D
S 00
S0 S2 , 01
S2 S2 , 01
S3 S3 , 10
S6 S2 , 01
S* , Q QN
S7 S3 , 10
01
S6 , 01
S6 , 01
S7 , 10
S6 , 01
S7 , 10
11
S0 , 01
–– , –
–– , –
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
–– , –
S7 , 10
State Tables and Flow Tables
• Assume internal state S0/10.• Change D to 1, then 0.• Change clock to 0.• Change D to 1, then 0.• What happens when clock changes
to 1.
CLK D
S 00
S0 S2 , 01
S2 S2 , 01
S3 S3 , 10
S6 S2 , 01
S* , Q QN
S7 S3 , 10
01
S6 , 01
S6 , 01
S7 , 10
S6 , 01
S7 , 10
11
S0 , 01
–– , –
–– , –
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
–– , –
S7 , 10
SSI Latches andFlip-Flops
• PLDs and FPGAs have to a large extent eliminated their use.