Project Number: JKM-2A03 Class-D Audio Amplifier A Major Qualifying Report: submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE in partial fulfillment of the requirements for the Degree of Bachelor of Science by ______________________________________________ Alex C. DiDonato ______________________________________________ Ryan T. Dupuis ______________________________________________ Tyler W. Folsom Date: April 29, 2004 Approved: __________________________________________ __________________________________________ Professor John McNeill Project Advisor Professor Demetrios Papageorgiou Project Advisor 1
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Project Number: JKM-2A03
Class-D Audio Amplifier
A Major Qualifying Report:
submitted to the Faculty
of the
WORCESTER POLYTECHNIC INSTITUTE
in partial fulfillment of the requirements for the
Degree of Bachelor of Science
by
______________________________________________ Alex C. DiDonato
______________________________________________ Ryan T. Dupuis
______________________________________________ Tyler W. Folsom
Date: April 29, 2004
Approved:
__________________________________________ __________________________________________Professor John McNeill
2.1 WHAT IS CLASS-D...................................................................................................................................................10 2.2 METHODS OF ACHIEVING CLASS-D.........................................................................................................................12
2.2.1 Pulse Width Modulation ....................................................................................................................................12 2.2.2 Sigma-Delta Modulation....................................................................................................................................15 2.2.3 Digital Signal Processing ..................................................................................................................................18
4 PROJECT EVOLUTION..............................................................................................................................................62 4.1 FIRST PCB...............................................................................................................................................................62 4.2 SECOND PCB...........................................................................................................................................................63 4.3 THIRD PCB..............................................................................................................................................................65 4.4 FOURTH PCB...........................................................................................................................................................67
5 TESTING AND RESULTS ...........................................................................................................................................68 5.1 EFFICIENCY TESTING...............................................................................................................................................68 5.2 “DEAD-ZONE”.........................................................................................................................................................71 5.3 ACOUSTIC CLARITY.................................................................................................................................................75 5.4 OUTPUT POWER.......................................................................................................................................................76 5.5 SIGNAL TO NOISE RATIO .........................................................................................................................................78 5.6 EFFICIENCY LOSS ....................................................................................................................................................80
From the calculations in the Power MOSFET section of this report, one can see that the
efficiency of the Fairchild FDP038AN06A0 is adequate enough for us to achieve our goal of 95%
et or exceeded 95% efficiency at our test frequency of 192 kHz,
this mo
not
efficiency. While other MOSFETs m
del was the most efficient. This has been made possible by a small Rds value and reasonably
small Qg value. These two specifications are the most significant in gaining efficiency.
As Rds or Qg increase, efficiency decreases proportionally. These specifications are also
inversely related which means that a When manufacturing a MOSFET a design consideration has to be
made because it is not possible to decrease both Rds and Qg at the same time. Currently it is
38
possible to decrease both factors at the same time. Perhaps a different fabrication process will some day
minimize these limiting factors. However, since Rds is a much larger factor to consider, we chose the
MOSFET with the least DC-on resistance.
Semiconductor technology continues to advance every year. New ways of making faster, higher-
power, and smaller devices are being discovered all the time.15 These minimize both the size and cost of
the electronic devices. Next year there will be an even better selection of MOSFETs to implement and
raise efficiency once again. The most important factors to look for when deciding on any switching
device would be its DC-on resistance, u re in excess of 10 MHz. The advent of
lity. If employed correctly, it may safeguard the overall output of the amplifier from variations in
the rail
nless switching speeds a
these new components shall push the limits of efficiency and give engineers the tools they need to make
amplifiers switch faster and ultimately produce higher fidelity sound.
2.7 Controls Theory
A certain level of control must be implemented in the system to protect against the frequent
instability of an automobile environment. Feedback is a common method for dealing with this
instabi
voltages and unwanted energy produced by the signal processing. A simple block diagram of the
system gives a better understanding of how the output can be used to correct these simple problems.
39
Sigma DeltaModulation
AnalogInput H-Bridge Low Pass
Filter
Feedback
Figure 27: Block Diagram
ent, the output will remain high
the output should not deviate from the input apart from the
ain.
t voltage as a midpoint, relative voltage swings can be
duty cycle of the Sigma-Delta modulated signal. For instance, if the
average voltage of a PowerNet system is 48 Volts and voltage drops to 44 Volts, the duty cycle must
increase by 8.33%.
A main concern of this MQP is to maintain a certain level of total harmonic distortion (THD).
Since the rail voltage of the H-bridge is entirely dependent on the automobile’s PowerNet voltage, a
wide range of values must be tolerated without alteration to the speaker output. This means that if a
lower voltage is present, then the output may need to remain “high” for a longer period of time to reach
an equivalent analog value. Conversely, if a higher rail voltage is pres
for a shorter period of time. If done properly,
g
Figure 28 shows that as the rail voltage changes, the duty cycle must be changed to achieve a
steady output. By using the average outpu
calculated and used to modify the
%33.848
4448=
−=
−=
i
if
VVV
DutyCycle Conversely, the duty cycle must be
decreased by 8.33% if rail voltage rises to 52 Volts.
40
Figure 28: Duty Cycle
order for this theory to work.
All other noise generated will be attenuated by the output low-pass filter. Theoretically, the output
should be a clean representation of the input.
ing of a system will be done. For this
reason, it will be show on the most basic level how the amplifier will be tested in terms of power and
efficiency. Please note the following figure.
This same technique serves a dual purpose. In addition to opposing the effects of rail voltage
swings, some of the excess energy generated by the switching output can be negated. The control circuit
must be fast enough, i.e. clock speed remains much higher than 20 kHz, in
2.8 Test Measurement Methodology
It is often times overlooked as to how the actual test
Figure 29: Testing Diagram
41
By measuring both the voltage and current at the power supply, the input power of the amplifier
can be determined using the following formula:
VIPIN ∗=
By finding the RMS voltage out of the amplifier, the output power of the amplifier can be
etermined using the following formula: d
RV 2
POUT =
From the actual power of the amplifier, the efficiency can be calculated. The theoretical
efficiency has already been determined in the MOSFET section of this paper. If the measured output is
divided by the input power, this will yield the efficiency of the amplifier.
EfficiencyInputPower
rOutputPowe=
If a 1Ω load was used for testing in lab, the testing equipment would have to be capable of
handling 42 Amps of current. Such equipment is expensive, and might not be readily available.
However, we will not be testing at such a low load impedance.
42
3 Design The design of a Class-D car audio amplifier is a complex and faceted undertaking. The design
stage of any project requires the most time and effort, and is also the most crucial to success. The design
considerations we took into account for this project were signal processing, power output and
amplification, filtering, thermal relief, and printed circuit board layout.
3.1 Sigma Delta Modulation The signal processing scheme that we chose was Sigma-Delta Modulation (Σ-∆). It is an analog-
to-digital conversion (ADC) method that is an adapted version of delta-modulation. A brief description
of this technique can be found in the section on Sigma-Delta Modulation.
ents.
Background information
Transforming Σ-∆ into a reality is not a difficult process and can be broken down into several designable
stages fairly easily. This section will focus on the design of these sections and the workings of the
whole system.
Previous to designing the circuitry involved in transforming an analog input signal into several
quasi-digital gate drive signals, one must understand the whole amplifier as a system. Using control
theory, one is able to map the signal flow and its transformation from stage to stage. Figure 30 below
shows a basic Sigma-Delta Modulation scheme with no additional compon
Figure 30: Basic Sigma-Delta Modulation
The open loop response of this system would look something like a pole at the integration
constant and a -20dB/dec slope thereafter. This is due to its transfer function int
1)(τs
sH = where τint
is the integrator time constant. Ideally, noise would be introduced mostly at the switching frequency of
the system but would be minimal at audible listening levels due to the inherent noise-shaping
characteristic of Sigma-Delta. distribution of energy in the 16 Figure 31 shows the normal (average)
43
h ics of this noise. One can see the decline in magnitude within the audible band. All higher
frequency noise is filtered out using a low-pass filter as described in the Filter section of this report.
armon
Figure 31: Noise Spectrum
In the design of our amplifier, we chose to modify the basic modulation scheme depicted in
in our H-bridge
onfiguration separately. This control over all the MOSFETs simultaneously was crucial in creating a
three-level output signal. The functionality of how the MOSFETs create these three states can be found
in further detail in the Power Stage section of this report. This additional control would minimize power
loss from drain to source switching, given the following equation:
Figure 30. By adding a second 1-bit quantizer, or comparator, we were able to generate four separate
gate signals to drive the four n-channel enhancement mode MOSFET devices
c
][)(21 WattsfttIVP sOFFONoinDS =+=−
.17
Discussion of this topic can be found in the Efficiency section of the report. This more advanced Sigma-
Delta Modulation scheme is shown in Figure 32.
Figure 32: Three-Level Sigma-Delta Modulation
44
The signal path can be described using Figure 32 above as a visual aide. First, (1), the signal
arrives at the amplifier from the audio source as an analog waveform of either music or a test tone.
Since S
rms. This
keep track of this error, continuous integration takes place resulting in a “sum of errors” waveform at
them in such anner to switch the four MOSFET devices. At location 5, the signal is very much still
digital but greatly amplified to the level of +/- the rail voltage. After the amplified signal is filtered
igma-Delta Modulation requires a feedback loop in order to take the difference from input versus
output, signal 7 is best described as a scaled down version of the output. Signal 2 is therefore the
difference between the input and output wavefo may also be called the “error.” In order to
signal 3. Using two 1-bit quantizers, four quasi-digital streams, signal 4, are generated to control the
gates of the H-bridge. The power stage of the amplifier receives these streams and is able to interpret
a m
using a 2-pole Butterworth filter, the result is signal 6, an amplified version of the original analog signal.
This loop is continued indefinitely.
Now that the system has been described, each module involved can be delineated separately.
Starting with the integrator, the schematic in Figure 33 shows the basic configuration.
Figure 33: Integrator
The integrator portion of the signal processing loop shown above has three important tasks. The
first is to take the difference between input and feedback. This is shown in the blue square marked Delta
including a pair of resistors whose center is the output. Since the input and output are roughly the same
but opposite in sign, one can expect this waveform to fluctuate closely around zero volts. While testing,
we did not capture this waveform since the magnitude was essentially zero. The second task is to
45
compute the integral of the signal at its negative input terminal. The final duty required for the
integrator to accomplish is the addition of a zero as illustrated in the next paragraph.
As described in the Stability section of this report, it is necessary to implement both a pole and
zero into the integration of the signal to achieve stability. The zero of the integrator was determined to
be 20 kHz using a Miller integrator equation of CR
fz
z π21
=
the resistor v
. The pole of the integrator was determined
by using the same equation, however this time alue used to determine the pole was taken
from the negative feedback of the integrator. This yielded a pole at 7 kHz using the equation
CRf
pp π2
1= .18
The next stage of Sigma-Delta Modulation was to implement comparators as high and low 1-bit
quantizers. This was actually performed by using two comparators whose negative inputs saw either a
voltage slightly higher or lower than zero. This voltage margin was called the “dead-zone” voltage due
to the fact that any output of the integrato is level resulted in zero switching of the
finely tune this margin using a plug-and-check method. The resistor value that yielded the least
r between zero and th
output. We found that the calculation of such a value is a trivial matter since, in testing, it was best to
crossover distortion and optimal switching efficiency was 620Ω. Using this ratio of resistors, the
corresponding voltage for the dead-zone was computed to be mVk
VVDZ 90620100
620*15 =Ω+Ω
Ω= . The
need and application of a resistor divider network to accomplish this voltag
e margin can be read about in
e Dead-Zone section of this report. As the sum of errors was compared to these near zero voltages,
TTL logic level voltages are sent to a D-latch flip-flop which converts the two outputs to four quasi-
digital streams: ,
th
1Q 1Q , 2Q , and 2Q . Figure 34 shows the resistive voltage divider, comparators, and
flip-flop.
46
Figure 34: Quantizers
If and the 1Q 2Q waveforms are plotted on the same axis, this gives the illusion of three-level
a-Delta switching. While this waveform does not directly exist, the output of the H-bridge does
follow the switching pattern seen in Figure 35. To further clarify, what appears to be switching either
or negativ
Sigm
positive e is really a change in polarity at the load. However this three-level state is what the
load thinks it is seeing, which is why we say that it does not directly exist.
Figure 35: Three-Level Switching
47
Since the H-Bridge is described in a different section of this report, we can jump to the final
division of designing the signal processing segment of the amplifier. The feedback attenuation block is
simply an instrumentation amplifier, or In-amp, that has been calibrated to the specific gain of our
amplifier.
Figure 36: Feedback Attenuation
We were able to determine the values of these resistors by using the low frequency gain of the
system, 2R
A −= .19 In our case, the amplification factor of the amplifier is about 30, so R2 must be 30
times greater than R1. This com
1R
pletes the Sigma-Delta Modulation signal processing piece of our report
. Because the signal is three-level, there are 3 possible
and is now important to discuss the power output and final stage of the amplifier.
3.2 Power Stage After the input signal passes through our Sigma-Delta Modulation scheme, we then devised a
way to control the MOSFETs of the H-Bridge
output configurations that the MOSFETs must be in. Figure 37 shows the three possible MOSFET
configurations.
48
Figure 37: Three possible MOSFET configurations
In order to achieve the three states shown above, we had to use all the resources available to us.
This meant that we had to use all four outputs of the flip-flop to control the MOSFETs individually. To
accomplish this goal, we used the output of the 1Q pin from the flip-flop to control the A-side High
MOSFET (BH) to be turned on. The way the flip-flop is configured, this corresponds to the
MOSFET, otherwise known as AH. This means that if the logic output sees a high, it triggers this
MOSFET on. On the flip side, if the logic output sees a negative high, then we want the B-Side High
2Q pin.
e to achieve this, the AL
These two states are what control the majority of the switching; however there are still two more
connections to be made.
When the AH MOSFET is on, the AL MOSFET must be off. In ord r
1MOSFET was connected to the Q output pin of the flip-flop. This ensures that the AH MOSFET and
the AL MOSFET will never be both on or off at the same time. The same type of configuration occurs
on the B-Side. When the BH MOSFET is on, the BL MOSFET must be off to prevent a short to ground
as well. This means the BL MOSFET must be connected to the 2Q output pin of the flip-flop to ensure
it is always opposite from the BH MOSFET.
This leads us into a discussion of the final configuration of the MOSFETs, which we will call the
zero state. For the time duration when neither the AH or the BH MOSFETs are on, we need a third
state, zero. During this time, we turn both the AL and the BL MOSFETs on, grounding both sides of the
speaker. Having this third state is what allows us to maximize efficiency because we are not wasting
energy when not needed.
49
The output from our Sigma-Delta Modulation is what tells the MOSFETs when to turn off and
on, but there is one other device that was not yet mentioned. Between the flip-flop and the MOSFETs is
would be under normal operating
conditi
Transfer functions are equations that help relate both gain and phase shift to a circuit. A typical
transfer function has the form
a driver chip. A driver chip was chosen for two reasons. The first reason is because it has built in logic
protection to ensure that 42 Volts is never shorted to ground. The second reason is because the driver
chip we chose can source up to 1 Amp of current per gate drive. What this means is that it will turn each
of the MOSFETs off and on with more power, resulting in quicker turn-on and turn-off times. The
actual schematic of the Power Stage can be found in the Appendix.
3.3 System Stability A major concern in designing our amplifier was how stable it
ons. A circuit must be able to operate without unwanted resonance that may be damaging to its
components. Each part of the amplifier was tackled by finding their individual transfer functions to
avoid unwanted resonance. This section of the report discusses the different parts of the amplifier and
how they each help or hurt the stability of the system.
)()()(
sPsZsH = . The two polynomials, Z(s) and P(s), allow the zeros and
poles of the system to be found. Zeros are values for s that make Z(s) = 0 and the overall gain of the
system zero. Poles are values that make P(s) = 0 and the overall gain infinite20. In addition, a zero
produces a phase-shift of +90° while a pole produces a phase-shift of -90°. 21
The low pass filter used in the power output stage of the amplifier plays a large role in
aintai
initely, causing the system to crash.
Now, instead of the negative feedback being able to correct for any imperfection in the output as
described in the Sigma-Delta section of the report, the noise is reinforced. It is preferable to have a
phase at which gain is 0dB of 145°or less.22 This is also called the phase margin, or difference between
m ning stability. This filter is 2nd order, which means it has two cutoff frequencies. These
frequencies are calculated in the Filter section of this report to be at 14 kHz and 40 kHz. Together these
two poles (low-pass cutoffs) add an additional -90° of phase shift to frequencies above each of their
cutoffs. If the open-loop gain at these frequencies approaching -180° phase shift is not less than 1, or
0dB, resonance may become a problem. This could be detrimental to any system taking negative
feedback from the output because the resonance could oscillate indef
50
0dB phase and -180°. Later in this section it is shown that a phase margin of 35° is required for
stability.
The other source of poles and zeros comes from the Miller integrator used in Sigma-Delta
processing. It was determined that our system could not tolerate any more poles without zeros, therefore
an additional resistor was added in series with the capacitor of the integrator. Please reference the
Sigma-Delta section of this report for this schematic and cutoff frequency calculation. The pole of the
integrator was located at 7 kHz while the zero was introduced at 20 kHz. The location of the zero was
chosen purposely close to the 14 kHz pole of the output low-pass filter. This zero would offset the
phase shift and decrease the attenuation [in dB per decade] caused by the pole. The result of this action
is such that neither pole nor zero h
The cancellation of pole and zero then allowed us to determine the frequency at which to make
ulation was not a
mple one to make. Therefore a graphical method was used to determine this value. First, we had to
determine the DC gain of our system. Using the equation below, it was computed to be the following:
ave an overall effect on the system.
our integration pole while maintaining a phase margin greater than 35°. This calc
si
⎟⎟⎠
⎞⎜⎜⎝
⎛=
IN
OUT
VVA log20
⎟⎠⎞
⎜⎝⎛=
VVA
642log20
dBA 16=
We then decided to draw a Bode Plot of our system. The DC gain of our amplifier is 16dB and
therefore can be regarded at the starting point of our Bode Plot. Figure 38 helps illustrate the graphical
method we used in obtaining the integrator pole. By reducing the frequency of this pole location, the
magnitude curve is shifted down and phase margin decreased. Conversely, increasing the frequency of
the integrator pole shifts the magnitude cu argin increased. The value at which the
sulting phase margin is 35° is 7 kHz and can be seen in Figure 38.
rve up and phase m
re
51
Figure 38: Graphical Bode Plot Method
The final bode plot of the system can then be plotted. This can be seen in Figure 39.
Figure 39: Bode Plot
From Figure 39 one can see that the system is stable. This is justified by the phase margin of
about 35°. In this amplifier, the output filter relies on a 4Ω load for stability. If the gain of the amplifier
was increased or load changed to different impedance, the system may become unstable.
52
3. ilter One of the most critical stages of our amplifier was our filter. Without it, a sinusoidal input
would remain in the form of a three-level Sigma-Delta Modulated output. This signal would contain a
great deal of unwanted high frequency content. This energy at frequencies up to the fastest resp
4 F
onse
frequency of the driver chip may be potentially dam ging to a speaker and would use any speaker wire
as an antenna for radiating EMI. In order to solve this problem, a low-pass filter was introduced to the
circuit to cutoff any frequencies higher than approximately 20 kHz. This is because the human ear can
only hear from 20-20 kHz, so any frequencies higher than this would result in wasted energy that the
y
e Stability section
of this report.
Separating the poles of the filter turned out to be a much more difficult task than anticipated.
Early in the project, we knew that inductors would have to be ordered. Originally, we thought that we
would be able to run a 1Ω load, resulting in nearly 50 Amps of current to be drawn through the
inductors. Because of the high current rating of the inductors required for our specifications, the
inductors had to be custom made. This resulted in a fairly costly investment for our amplifier, so once
we had the inductors in our possession, we could not afford to send away for new ones. This posed a bit
of a problem for our design. In order to determine the cut-off frequencies for our filter, the two
equations below were used.
a
speaker would try to play.
Originally, we thought we could create a second order Butterworth filter with a double pole at 20
kHz. However, the filter got slightl more complicated when we introduced our Sigma-Delta circuit.
The problem that arose was that we then had to be concerned with the stability of our system. The
details on the stability of our system can be found in the Stability section of this report. From a design
standpoint the only thing we needed to know was that the poles had to be separated, meaning that there
could not be a double pole at 20 kHz. Again, the reasoning for this can be found in th
1
LRf
CL
∗=
∗
π
π
2
2
2
f =1
53
Notice that the inductor value is used to obtain both cut-off frequencies. This means that
because we were stuck with our original inductor value of 22.5 µH, we were limited in the range of cut-
off frequencies we could obtain. Also, thinking ahead to the testing of our amplifier, we decided to stick
with a fixed load resistance of 4Ω. This meant that the cut-off frequency for f2 was predetermined.
kHzHL
Rf 145.222
222 =
∗Ω
=∗
=µππ
Notice that the cut-off frequency is only 14 kHz. This is a design trade-off that we had to make
in keeping our original inductor values. Although the first cut-off frequency is lower than 20 kHz, most
people can only hear up to 16 we decided as a group that it
as one design decision we were willing to live with. The benefit of purchasing new inductors was not
40 below.
kHz.23 By taking that into consideration,
w
worth the small increase in cut-off frequency of the low-pass filter. Also notice that a resistance of 2Ω
was used in the equation instead of 4Ω. This is because in an H-bridge configuration, there are two
separate filters, one for each half of the bridge. This can be seen in Figure
Figure 40: H-Bridge Filter Configuration
When trying to design a filter for an H-Bridge configuration, the easiest way to approach the
e. What this means is that it is necessary to divide the
situation is to look at only half the bridge at a tim
bridge in half. If that is done, you will notice that the inductor value and capacitor values remain the
same. The only variable that changes is the resistive load, because half would belong to each side of the
filter. Please refer to Figure 41.
54
Figure 41: H-Bridge Filter Half Representation
The circuitry remains exactly the same, and you will notice that there is still a 4Ω load in place.
However, when looking at the filter half representation, only 2Ω belongs to each filter, which is the
reasoning behind the 2Ω being used in the f2 equation rather than the 4Ω.
After we accepted the first cut-off frequency to be 14 kHz, it was then time to set the second cut-
flexibility to change the capacitor val ce again we already had purchased several 0.1 µF
capacitors, so we decided to use those as well. This was not as big of a concern be
off frequency. Notice that the inductor value is also included in this equation, but we do have the
ue. On
cause we had the
ability to add as many 0.1 µF as we wanted, giving us a range of overall capacitance. Knowing that our
first cut-off frequency was 14 kHz, we decided to make the second cut-off frequency approximately 40
kHz. This would be well past the audible range, but still low enough in frequency to reduce EMI.
Using the formula for f1, we were able to compute what capacitor value was desirable to yield a cut-off
frequency of 40 kHz.
FCCH
kHzCL
f µµππ
7.05.222140
21
1 =→∗
=→∗
=
Based on this formula, the capacitance value that should be used is 0.7 µF. This would be easy
to obtain from the 0.1 µF capacitors that we already had by configuring 7 of them in parallel. Figure 42
shows how the filter may look from a schematic perspective.
55
Figure 42: H-Bridge Filter Design Configuration
One of the reasons that w in parallel rather than one big
apacitor was to reduce the equivalent series resistance, or ESR of the capacitors. The ESR is a
lcula
e decided to use multiple capacitors
c
ca ted resistance at a particular frequency. As the frequency increases, the ESR decreases linearly.
This was an important factor to take into consideration because at low frequencies, the ESR is relatively
high, measuring at 1.6Ω for the capacitors we chose. However, AC current through this series resistance
would be lower at low frequency since dtdvCI = . A high ESR would be detrimental to our efficiency,
and will be talked about in further detail in the Efficiency Losses section of this report.
Although the configuration shown in Figure 42 would have worked, this was not the layout that
we chose for our filter. If you count the total number of capacitors in the circuit, you will find that 14
capacitors would be necessary in order to produce our filter. There is a way to reduce the total number
of capacitors used that create the same filtering effects. The way to achieve that is to use some of the
apacitors across the load instead. Please refer to Figure 43 for further clarification. c
56
Figure 43: H-Bridge Filter Configuration
By placing some of the capacitors across the load, they essentially become twice as effective.
This is because they contribute to both sides of the H-Bridge filter, rather than one side at a time. Notice
that if the 4 capacitors across the load count for each side, then that yields an overall capacitance of
0.8µF, not 0.7µF. Well this is true. We decided that we wanted a symmetrical looking board, and in
order to achieve that, three rows of 4 capacitors would have to be used. We decided that this was also a
design tradeoff we were willing to accept because the difference between 0.7 µF and 0.8 µF resulted in a
cut-off frequency of 40 kHz and 37 kHz respectively. Also notice that the total capacitor count was
reduced from 14 to 12, while still increasing the effective capacitance. Had we not added the capacitors
across the load, and still wanted 0.8 µF of effective capacitance, then a capacitor count of 16 would have
been necessary instead of the 12 we used in our filter design.
3.5 Heat sink For the testing of our project, we knew that the MOSFETs used for our H-Bridge would get hot
due to the fast switching speeds. To increase the p ance, a large heat sink was created to help
aintai
erform
m n a reasonable temperature for the MOSFETs. Two different considerations were taken into
account. The first consideration was to build a heat sink for testing purposes. The second consideration
was to design a heat sink for marketing purposes. If this amplifier is to be marketable, the heat sink
would have to be large enough to keep the MOSFETs cool for long durations of playtime. However, for
57
the testing of our amplifier in lab, we decided that 15 minutes of playing time would be more than
sufficient to test the amplifier and obtain our results. It was decided to construct an adequate heat sink
for our purposes of testing in lab, and to design another that would be used as both a housing and a heat
sink if the amplifier was put into production.
For testing purposes, two heat sinks were fabricated out of a solid piece of aluminum. The
aluminum was donated to us by A & R Plastics Inc. as well as their machine shop for fabrication of our
ensions of 2.25”x 2”x 1.375”. An actual picture of the heat sink used for testing can be seen
Figure 44 below.
heat sinks. The design of the heat sinks presented some constraints. One constraint was how wide the
heat sinks could be by the amount of space we had on our board between components. Our second
constraint was the depth of the heat sink, which was limited by the depth of our board.
We chose aluminum for the design of our heat sink because of its light weight and thermal
properties. Secondly, in order to maximize the surface area of the heat sink to the ambient air, cooling
fins were added to the design. Generally the more cooling fins that a heat sink has, the better job it will
do at keeping the components cool. The heat sink was made larger than necessary, but in our situation it
was best to over estimate the need for thermal protection. This yielded two identical heat sinks with
overall dim
in
Figure 44: Heat sink used for testing
Figure 45: Heat sink shown with supports
One of the problems that we encountered with such a large heat sink was the weight of the
finished product. The heat sink could have been made smaller, but since the product was already
finished, we thought it would be best to leave it alone. Because we had a machine shop at our disposal,
we decided to drill and tap some supports into the fins of the heat sink. This would allow us to use
58
Teflon screws to support the weight of the excessively large heat sink. After it was mounted to the
board, the idea worked out quite well. Figure 45 shows a heat sink mounted to the MOSFETs with
supports in place to help reduce the load the MOSFETs would have to carry. Although it may not look
as professional as it should, the idea worked, and so did the heat sinks. We were able to play music,
which causes the most amount of switching, for approximately 15 minutes before the heat sinks started
to get too hot. We were able to conduct all of our testing with the heat sinks shown.
In the event that our amplifier is to be sold in today’s market, the amplifier would have to be
contained in a solid casing of some sort. This means that the heat sinks can not be two large objects
attached to the MOSFETs. Instead, the MOSFETs would be placed at the very edge of the board, and
the casing surrounding the am ould be incorporated into the
esign for what would hopefully be fan cooled. In addition to this casing being used as both a heat sink
ore all
thers. This was the case in the design of our PCB as well. In particular, high-power switching
MOSFET devices were a major concern and had to be dealt with carefully. We knew that under the
high current and fast switching they would be subjected to, heat was an issue. In order to deal with the
thermal protection of the MOSFET devices, large heat sinks would be required. Through our experience
with other audio amplifiers we were able to determine their best location. By aligning the TO-220
packages along the edges of the PCB and facing heat sink tabs outward, we would be able to effectively
build as large of a heat sink as necessary. All other devices were not as much of a concern in this stage
of PCB design.
plifier would double as a heat sink. Fins w
d
and an outer housing unit, it would also serve as an EMI shield which was discussed in the Background
section of this report. The actual fabrication of this type of device was not made, however it is
important to point out the need for a housing in the event of a continuing MQP or for marketing
purposes.
3.6 Printed Circuit Board The design and layout of any printed circuit board is a very cognitive task. One must first
analyze the components that will ultimately populate the board and their needs. Secondly, the basic
shape of the board can be determined. Thirdly, any components including input and output terminals
requiring special locations can be placed. Lastly, the remainder of parts can be laid out using good
engineering practices described in this section.
Often times certain components require special locations and must be considered bef
o
59
Figure 46: Placement of MOSFETs for Heat Sink
Determining the fundamental shape of our board was one of the more elementary steps in laying
out our design. While many basic and industry standard
ape is still the rectangle. Since our design followed a strict flow of information in one direction, an
forms and sizes may have worked, the most
sh
elongated rectangle certainly seemed the most reasonable model. This would allow for as much surface
area as required by heat sinks as well as minimizing wasted space.
The layout of the final board design was the next step to take place. As mentioned previously,
the flow of our signal path was strictly unidirectional if feedback were ignored. Therefore we found it
best to divide the PCB into sections, much like our circuit for both simplicity and practicality. One side
of the board was clearly designated as the signal processing portion whereas the other was reserved for
the power output section. These two divisions are distinct from one another in their requirements so
were best left separate. On one hand, the signal-processing side is filled with mixed signals and high-
transient voltage transmission lines. Adversely, the power output stage of the amplifier requires large
ground planes, many wide current paths, and spacing between thermally dangerous components.
60
Figure 47: Two Separate Sections of Board Layout
Good engineering practices should always be used when designing a printed circuit board. There
are several rules of thumb that we used. The first and foremost was to allow high transient voltages their
own paths and ground planes while keeping them short. What this means is to avoid running other
traces either over or under these paths in a multilevel board. Failing to do so will certainly affect signal
tegritin y as each trace acts as a transmitter and receiver. This is due to the fact that the traces are
capacitively and inductively coupled. The second rule that we used was relative to any high current
paths. These traces should be kept as wide as possible to minimize the trace resistance, and wherever
possible, power planes should be used. Any high current path that is too narrow will not have negligible
resistance. In our design using a 4Ω load, we measured currents in excess of 10 Amps. From a power
loss perspective even a 0.1Ω trace would burn up to 10W of power, or 2.5% of the total. This loss could
greatly set back our efficiency goal. Another method of keeping these traces short was to place power,
ground, and speaker connections on the power output side of the board. By following these layout rules,
we believe that efficiency and signal integrity can be maximized.
61
4 Project Evolution In order for us to complete the project with a working amplifier, several board designs were used
to achieve our goal. At first we started small, and eventually worked our way to a professional looking
printed circuit board for the testing our amplifier. This section of the report will explain how the project
evolved and how we ended at out final result.
4.1 First PCB Once the design was finalized in the respect that we were using a MOSFET H-Bridge
configuration that was controlled by a driver chip, it was time to perform some testing. The simplest
way would have been to use a breadboar wever breadboards contain capacitance
e laid out, we decided to wire the power stage of
ur amplifier using primarily 22ga wire for most of the connections; however 16ga wire was used to
e ply to the MOSFET bridge, the bridge to the load, and the bridge to ground. This
ps of current would be traveling, and we wanted to ensure that the wire would be
d to wire the circuit; ho
and inductance between the traces, so our results would not have been as accurate as we would have
hoped. Also, we knew that we would be drawing approximately 2.5 Amps of current, and this reached
the threshold of what we considered to be too much for a breadboard to handle. Pulling such a large
amount of current through the breadboard could have caused it to melt, which would have been a safety
concern in lab, and also could have damaged the components we were trying to test. Because of this, we
decided to use a PC board that we would wire ourselves using a design layout that would minimize
interference with transient currents as described in the PCB design section of our report.
After much debate as to how the board would b
o
conn ct the power sup
is where the 2.5 Am
able to handle the large current draw. Soldering the wires to all the components proved to be much
more difficult than anticipated. In many cases, there were 3 wires attached to a single pin. This made it
difficult because after one wire was soldered in place, one would then have to heat up the pin a second
or a third time to add the additional wiring. In doing so, the previous wires that were already attached
had the tendency to fall off because the solder was heating back into a liquid state. It took some time to
complete, but you can see the end result depicted in Figure 48.
62
Figure 48: Original PCB
As you can see, we tried our best to keep the board layout as neat as possible to simplify
troubleshooting. The huge coils that you can see at the top of the picture are our inductors used for the
low a t being ordered,
so h rd,
but through the use of banana connectors, we were ab
poi o chunk of aluminum we cut to
use a
for the heat sinks that were created later in the project.
4.2 S
r original PC Board was working properly and all the capacitor values, resistor values,
work with for further testing.
he program that was chosen to create the board layout was Ultiboard 2001, and at first it was difficult
to use, but we got used to it and it worked out very nicely. We then sent out the board to be created
using a company called Advanced Circuits.24 We looked into several vendors to create our board,
however they were not only the cheapest, but also had a free quote by uploading some of our files that
-p ss filter. When we started the board layout, the custom wound inductors were jus
we ad no idea they would be so large. Because of this, they are hanging off the edge of the boa
le to make it work regardless. Another thing to
nt ut is the large black block attached to the MOSFETs. This was a
as heat sink. The aluminum served the purposes we needed it for, and also gave us some practice
econd PCB
After ou
diodes, etc. were finalized, we then decided to create a real PCB where we would get a more
professional looking board that minimized transient currents, trace inductance and capacitance even
further. We knew we still had the signal processing to work on, but for the time being, we thought that
having a professional PCB would make things neater and a lot easier to
T
63
even told us where we had flaws in our design. Every flaw that the program found in our design was
minor enough that the board could be produced immediately. Most flaws were clearance issue such as a
hole being too close to the edge of the board, but since the board size was not etched in stone, they just
expanded the board for us where it needed it. To our surprise, the turnaround time was only a few days.
We were expecting a turnaround time of a week or two. Also, another observation that we made was
that whether you bought 1 board or 4 boards, the price remained the same. This is because setting up the
equipment to create your board takes the most time, and after that, the material cost for the board itself
and the solder used to coat it is insignificant.
but more importantly it was a very neat design with a lot of thought put into the board layout, and the
plane t was drilled for it
• A keep out area on the power plane for the banana jacks used for speaker connections was
ard of the ground were forgotten • Many soldering pads were too small, making it very difficult to solder to •
When our board arrived, we were very happy with our product. It was very impressive looking,
product was paying off. However, the first draft if you will of our project did have a few flaws.
Fortunately however, nothing was catastrophic to the forward progress of our project. The flaws that we
found in our first board were as follows:
• The ground pins of the BNC connectors were not connected to our ground• The signal pin of the BNC connector was slightly too large for the hole tha
forgotten • Mounting holes to elevate the bo
A keep out area on the power plane was forgotten around the driver chip to make soldering easier
• The drill holes for the RJ45 jack were much too large, making the solder contact only on one side of each pin.
• A few of the diode and capacitor holes were slightly larger than necessary • The power and ground pins for the voltage regulator were reversed, requiring surgery on our
PCB
Although most of the issues had to do with hole sizes, luckily in almost all cases, the holes were
larger than needed. Had the situation been reversed, we would have run into a much larger problem.
Even where the BNC hole was too small, we were still able to make it fit after some TLC. Our first
professional looking PCB can be seen in Figure 49 and Figure 50 below.
64
Figure 49: Second PCB Ground Plane (Top) Figure 50: Second PCB 42V Power Plane (Bottom)
For this board, the MOSFETs were separated by pairs on each half of the board. Because of this,
a new heat sink had to be created. Unfortunately we do not have a picture of this board fully populated,
but t fabrica eat sink
that it was for the first one because we now had som ur belt.
we
ere pleased with the results from the first board. This time however the board was about 3 times the
cost of what it was the first time because of the considerable size difference. This ate up about half of
our budget, but it was well worth it. The good news about this board was that because it was our second
iteration of the power stage, there were no mistakes this time around. However, there were a couple in
our new section for signal processing. Originally we thought that we could use two inputs for our driver
chip, but after the board was already returned to us completed, we realized that we needed to control all
four MOSFETs individually. This meant that we had to cut a couple of the traces off the board, and add
4 more. This was probably the most cosmetic damage that we had to put our board through. The only
other mistakes on our part was a via that somehow connected one of our traces to the 42 Volt power
plane by accident, and our feedback loops had to be switched. This was easily corrected by switching
one of the leads for two resistors. To make it look slightly more appealing, we hid one of the resistors
his did give us a chance to improve our tion skills. It was much easier to create this h
e experience under o
4.3 Third PCB
After making all the necessary corrections to our second PCB and adding all the components for
our sigma delta signal processing, we were ready to send out for another professional PCB. This would
be our third board to work with. We once again sent the board out to Advanced Circuits because
w
65
under the board, so that as you looked at the top of the board, you only saw 1 resistor at a 45 degree
angle rather than 2 crossing resistors. This was the board that we used for all of our testing on the
amplifier. The board itself can bee seen in Figure 51 and Figure 52.
Figure 51: Third PCB Ground Plane (Top) Figure 52: Third PCB 42V Power Plane (Bottom)
The populated board that was used for testing can be seen in Figure 53 below. As you can see, a
massive heat sink was created. We put a lot more time into this design because we knew that audio
applications play at a wide range of frequencies, causing the MOSFETs to switch much more often that
if they were playing a sine wave. The more switching that takes place, the hotter the MOSFETs will get.
This is why the heat sinks are so much larger than the previous ones, and also have fins on them to
provide more surface area to the ambient air, which increases the thermal properties of the heat sink.
66
Figure 53: Third PCB Fully Populated
4.4 Fourth PCB
After correcting the mistakes that were found in our third PCB, we decided to create a fourth PCB with
all the BNC connectors removed, and the board made as small as possible. We did this with the hopes
that we might be able to send out one last board, but unfortunately, we ran out of both money and time.
is however a great place to pick up from if this project gets continued in the future. The PCB is ready
to be sent out with all the mistakes already corrected in the program. Also added to the board were
twice as many bypass capacitors for the 42 Volt power source. It also was important to see how small
we could get the amplifier in size without the BNC connectors on there. They were necessary for
oubleshooting, but now that the bugs are worked out of the amplifier, they just get in the way. The
It
tr
board layout for our final PCB as well as the previous ones can be found in the appendix.
67
5 Testing and Results
In this section of the report, we will guide you through the process of how we tested various
aspects of our amplifier, and explain to you the results we obtained.
5.1 Efficiency Testing
The goal of this project was to design and build a Class-D amplifier that achieves an efficiency
of 95%. In order to determine that we met this specification it is first importan ethod of
which data can be collected. Using th d need to determine input and output
ower. This section will illustrate the tools and techniques used to determine efficiency as well as an
ine input and output power.
here are several methods by which power can be calculated, but the resources that were available to us
were slightly limited. However, by utilizing the simple equations below, we were able to determine
both input and output power of our amplifier.
t to discuss the m
e resources available we woul
p
explanation of our final results.
It was necessary to use three measurement devices in order to determ
T
VIPower *=
RVPower
2
=
Since the BK Precision regulated power supply we were using gave a current reading as well as a
voltage reading, we chose to use the P = IV equation for input power. We were somewhat limited by the
itor the input voltage directly on the board using an HP 34401A multimeter
ccurate to six significant figures.
The output power was measured using only one device at a time. For this task, we chose to use a
Tektronix TDS 210 digital real-time oscilloscope. With this device we were able to capture snap-shots
f the output waveform as shown in Figure 54.
accuracy of this device since it was accurate only to one-tenth of an ampere. On the other hand, we
would be able to easily mon
a
o
68
Figure 54: Oscilloscope Snapshot
When connected to a computer, data could be uploaded into a spreadsheet to find the RMS, or
root-mean squared, voltage. This was solved using the following equation.
n
VVAvg n
OUTi
OUT
∑=
2
2 )(
)( 2OUTRMS VAvgV =
The equation for output power was simply RO
temperature was apparently negligible because the load resistance measured to be the same at both
ambient room temperature and at 140°F.
Finally, the ratio of input and output powers was solved for and recorded as the percentage
efficiency of the amplifier.
VP RMS2
= . The change in resistance due to
[%]IN
OUT
PPEfficiency =
The efficiency in comparison to clock speed of the Sigma-Delta Modulation was our most
critical measurement. This relation is essential in determining the sampling frequency at which yields
69
the highest efficiency. By using a HP33120A to generate an array of clock waveforms we were able to
graph the results at several frequencies ranging from 250 kHz to 4 MHz. Figure 55 below shows the
These important specifications are therefore RDS and QG. This is discussed in the Background
section on efficiency but is important to note that both RDS and QG should be minimized. These two
factors greatly affect efficiency and follow the following power loss curve as shown in Figure 65.
Figure 65: Powe Loss
Our decision to select the Fairchild FDP038AN06A0 PowerTrench MOSFET was based on
finding the perfect match for our application. We needed a device with at least a 60 Volt break down
voltage and a 50 Amp continuous current limit based on a 1Ω load. Since we found that with higher
break down voltage, RDS increased, we chose a MOSFET with a break down voltage at our bare
minimum of 60 Volts.
Other decreases in efficiency are due to the filter components. Losses from either the capacitors
r are either conductively or in their AC characteristics.
A primary concern in our filter design was the inductors. After calculating the appropriate
values for these components, we needed to send our specifications to a custom winding company for
r
or inductors can be calculated using several known equations given throughout this section. Methods by
which these elements dissipate powe
81
manufacture. Each inductor had to withstand the same amount of current as each MOSFET. Using a
1Ω resistive load, this current would peak to 50 Amps at 50 Volts. Therefore, above average gauge wire
had to be used. The windings were made with 10 gauge wire and RDC of less than 20mΩ. Now that all
the conduction loss resistances are known, the total conduction loss can be calculated from the
MOSFET, inductor, and load values.
( )( ) ( )( )( )( )
( )( )( )
Wmm
mmRRRRRVLC
VRRLC
WattsIVLossDCConduction
inductorMOSGETrail
u r
ddrop
13.5208.324
208.32*4222*..
2.
][*)(
2
2
2
2
=Ω+Ω+Ω+Ω
=+++
=
⎥⎦
⎤⎡⎤⎡ ⎞⎛ +
==
Some additional power loss is due to the capacit r would be lossless and
return each bit of energy it had stored. However, the ESR (Equivalent Series Resistance) rating of a
capacitor is a particular evaluation of quality given to each series of manufactured devices. Ideally this
value would be zero and therefore would have no AC resistance. In order to calculate the ESR for a
given capacitor, one must start by finding its dissipation factor. In our case, we used capacitors with a
dissipation factor of < 1% @ 20°C at 1 kHz. Using a value of 1% and the following equations, we can
lve for the ESR at a switching frequency of 192 kHz.
RRRV
RRR ind ctoMOSGETLoad
railrail
inductorMOSGETLoad
inductorMOSFET
2*
2. ⎢
⎣ ++⎥⎦
⎢⎣
⎟⎟⎠
⎜⎜⎝ ++
=
inductorMOSGETLoad
ors. A perfect capacito
so
XcESR
=δ
CfXc
π21
=
CfESR
πδ
2=
Ω== mkHzuF
ESR 83)192)(1.0(2
01.π
ESR is not constant and changes greatly with frequency. Figure 66 shows the ideal and actual
impedance of a 0.01 µF capacitor.
82
Figure 66: Actual vs. Ideal 0.01uF Capacitor Impedance28
Using the equations for current and ESR, the power dissipated in the capacitors can be found.
dtdVCI =
OfVCI **∆=
)192(*)84(*)1.0( kHzVuFI =
AI 6.1=
WmAofcapsRIP 4.316)83*9.12()*#( 22 =Ω==
Figure 67 shows power loss versus dissipation factor. This is very helpful when determining
how much loss is acceptable when selecting capacitors.
83
Figure 67: Power Loss vs. Dissipation Factor
Additionally, we have plotted the power loss versus switching frequency since we have a very dynamic range of switching frequencies that may be encountered during audio amplification. See Figure 69.
a) Maximum Switching Speed [Hz] – the fastest a device can switch on and off based on its rise
time and fall time. Since Hertz is simply the reciprocal of time in seconds, we can calculate the maximum switching speed by adding the rise and fall times and dividing 1 by this number.
b) Conduction Loss (DC) [Watts] – power loss due to current flowing from the drain to source of a MOSFET device. This equation assumes DC current or current that is steady. In order to calculate DC loss, we can begin with the equation P=I*V where V is the rail voltage and current is the drain-source current. Since we are only concerned with one of the MOSFETS, we can divide by 2. The voltage across each MOSFET is given by the ratio of its resistance relative to
the resistance of the load, dsLoad
ds
RRR
22+
. The drain-source current is then the ratio of the rail
voltage over the total resistance of the MOSFETs and the load, dsLoad
ds
RRV
2+. The simplified
conduction loss equation can be found in the table above. c) Switching Power Loss (Gate-Source) – power loss due to the charging of the gate-source
capacitance of the system in order to reach the gate-source voltage. This can be found by multiplying the gate charge (Qg), gate-source voltage (Vgs), and switching speed (fclk).
d) Switching Power Loss (Drain-Source) – power loss due to the charging of the drain-source capacitance of the system in order to reach the drain-source voltage. Equation was taken from Power Electronics and Drives, p2-9
LM111/LM211/LM311Voltage Comparator1.0 General DescriptionThe LM111, LM211 and LM311 are voltage comparators thathave input currents nearly a thousand times lower thandevices like the LM106 or LM710. They are also designed tooperate over a wider range of supply voltages: from standard±15V op amp supplies down to the single 5V supply used forIC logic. Their output is compatible with RTL, DTL and TTLas well as MOS circuits. Further, they can drive lamps orrelays, switching voltages up to 50V at currents as high as50 mA.
Both the inputs and the outputs of the LM111, LM211 or theLM311 can be isolated from system ground, and the outputcan drive loads referred to ground, the positive supply or thenegative supply. Offset balancing and strobe capability areprovided and outputs can be wire OR’ed. Although slowerthan the LM106 and LM710 (200 ns response time vs 40 ns)
the devices are also much less prone to spurious oscilla-tions. The LM111 has the same pin configuration as theLM106 and LM710.
The LM211 is identical to the LM111, except that its perfor-mance is specified over a −25˚C to +85˚C temperature rangeinstead of −55˚C to +125˚C. The LM311 has a temperaturerange of 0˚C to +70˚C.
2.0 Featuresn Operates from single 5V supplyn Input current: 150 nA max. over temperaturen Offset current: 20 nA max. over temperaturen Differential input voltage range: ±30Vn Power consumption: 135 mW at ±15V
3.0 Typical Applications (Note 3)
Offset Balancing
DS005704-36
Strobing
DS005704-37
Note: Do Not Ground Strobe Pin. Output is turned off when current ispulled from Strobe Pin.
Increasing Input Stage Current (Note 1)
DS005704-38
Note 1: Increases typical common mode slew from 7.0V/µs to 18V/µs.
*Absorbs inductive kickback of relay and protects IC from severe voltagetransients on V++ line.Note: Do Not Ground Strobe Pin.
Strobing off Both Input and Output Stages (Note 2)
DS005704-42
Note: Do Not Ground Strobe Pin.
Note 2: Typical input current is 50 pA with inputs strobed off.
Note 3: Pin connections shown on schematic diagram and typical applications are for H08 metal can package.
Positive Peak Detector
DS005704-23
*Solid tantalum
Zero Crossing Detector Driving MOS Logic
DS005704-24
LM11
1/LM
211/
LM31
1
www.national.com 2
4.0 Absolute Maximum Ratings forthe LM111/LM211 (Note 10)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Total Supply Voltage (V84) 36VOutput to Negative Supply Voltage (V74) 50VGround to Negative Supply Voltage (V14) 30VDifferential Input Voltage ±30VInput Voltage (Note 4) ±15VOutput Short Circuit Duration 10 sec
Operating Temperature RangeLM111 −55˚C to 125˚CLM211 −25˚C to 85˚C
Lead Temperature (Soldering, 10 sec) 260˚CVoltage at Strobe Pin V+−5VSoldering Information
Dual-In-Line PackageSoldering (10 seconds) 260˚C
Small Outline PackageVapor Phase (60 seconds) 215˚CInfrared (15 seconds) 220˚C
See AN-450 “Surface Mounting Methods and Their Effecton Product Reliability” for other methods of solderingsurface mount devices.
ESD Rating (Note 11) 300V
Electrical Characteristics (Note 6)for the LM111 and LM211
Parameter Conditions Min Typ Max Units
Input Offset Voltage (Note 7) TA=25˚C, RS≤50k 0.7 3.0 mV
Input Offset Current TA=25˚C 4.0 10 nA
Input Bias Current TA=25˚C 60 100 nA
Voltage Gain TA=25˚C 40 200 V/mV
Response Time (Note 8) TA=25˚C 200 ns
Saturation Voltage VIN≤−5 mV, IOUT=50 mA 0.75 1.5 V
TA=25˚C
Strobe ON Current (Note 9) TA=25˚C 2.0 5.0 mA
Output Leakage Current VIN≥5 mV, VOUT=35V 0.2 10 nA
TA=25˚C, ISTROBE=3 mA
Input Offset Voltage (Note 7) RS≤50 k 4.0 mV
Input Offset Current (Note 7) 20 nA
Input Bias Current 150 nA
Input Voltage Range V+=15V, V−=−15V, Pin 7 −14.5 13.8,-14.7 13.0 V
Pull-Up May Go To 5V
Saturation Voltage V+≥4.5V, V−=0 0.23 0.4 V
VIN≤−6 mV, IOUT≤8 mA
Output Leakage Current VIN≥5 mV, VOUT=35V 0.1 0.5 µA
Positive Supply Current TA=25˚C 5.1 6.0 mA
Negative Supply Current TA=25˚C 4.1 5.0 mA
Note 4: This rating applies for ±15 supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is equal to thenegative supply voltage or 30V below the positive supply, whichever is less.
Note 5: The maximum junction temperature of the LM111 is 150˚C, while that of the LM211 is 110˚C. For operating at elevated temperatures, devices in the H08package must be derated based on a thermal resistance of 165˚C/W, junction to ambient, or 20˚C/W, junction to case. The thermal resistance of the dual-in-linepackage is 110˚C/W, junction to ambient.
Note 6: These specifications apply for VS=±15V and Ground pin at ground, and −55˚C≤TA≤+125˚C, unless otherwise stated. With the LM211, however, alltemperature specifications are limited to −25˚C≤TA≤+85˚C. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single5V supply up to ±15V supplies.
Note 7: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1 mA load. Thus, theseparameters define an error band and take into account the worst-case effects of voltage gain and RS.
Note 8: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive.
Note 9: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. Do not short the strobe pinto ground; it should be current driven at 3 to 5 mA.
Note 10: Refer to RETS111X for the LM111H, LM111J and LM111J-8 military specifications.
Note 11: Human body model, 1.5 kΩ in series with 100 pF.
LM111/LM
211/LM311
www.national.com3
5.0 Absolute Maximum Ratings forthe LM311 (Note 12)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Total Supply Voltage (V84) 36VOutput to Negative Supply Voltage (V74) 40VGround to Negative Supply Voltage (V14) 30VDifferential Input Voltage ±30VInput Voltage (Note 13) ±15VPower Dissipation (Note 14) 500 mWESD Rating (Note 19) 300VOutput Short Circuit Duration 10 sec
Operating Temperature Range 0˚ to 70˚CStorage Temperature Range −65˚C to 150˚CLead Temperature (soldering, 10 sec) 260˚CVoltage at Strobe Pin V+−5VSoldering Information
Dual-In-Line PackageSoldering (10 seconds) 260˚C
Small Outline PackageVapor Phase (60 seconds) 215˚CInfrared (15 seconds) 220˚C
See AN-450 “Surface Mounting Methods and Their Effecton Product Reliability” for other methods of solderingsurface mount devices.
Electrical Characteristics (Note 15)for the LM311
Parameter Conditions Min Typ Max Units
Input Offset Voltage (Note 16) TA=25˚C, RS≤50k 2.0 7.5 mV
Input Offset Current(Note 16) TA=25˚C 6.0 50 nA
Input Bias Current TA=25˚C 100 250 nA
Voltage Gain TA=25˚C 40 200 V/mV
Response Time (Note 17) TA=25˚C 200 ns
Saturation Voltage VIN≤−10 mV, IOUT=50 mA 0.75 1.5 V
TA=25˚C
Strobe ON Current (Note 18) TA=25˚C 2.0 5.0 mA
Output Leakage Current VIN≥10 mV, VOUT=35V
TA=25˚C, ISTROBE=3 mA 0.2 50 nA
V− = Pin 1 = −5V
Input Offset Voltage (Note 16) RS≤50K 10 mV
Input Offset Current (Note 16) 70 nA
Input Bias Current 300 nA
Input Voltage Range −14.5 13.8,−14.7 13.0 V
Saturation Voltage V+≥4.5V, V−=0 0.23 0.4 V
VIN≤−10 mV, IOUT≤8 mA
Positive Supply Current TA=25˚C 5.1 7.5 mA
Negative Supply Current TA=25˚C 4.1 5.0 mA
Note 12: “Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isfunctional, but do not guarantee specific performance limits.”
Note 13: This rating applies for ±15V supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is equal to thenegative supply voltage or 30V below the positive supply, whichever is less.
Note 14: The maximum junction temperature of the LM311 is 110˚C. For operating at elevated temperature, devices in the H08 package must be derated basedon a thermal resistance of 165˚C/W, junction to ambient, or 20˚C/W, junction to case. The thermal resistance of the dual-in-line package is 100˚C/W, junction toambient.
Note 15: These specifications apply for VS=±15V and Pin 1 at ground, and 0˚C < TA < +70˚C, unless otherwise specified. The offset voltage, offset current andbias current specifications apply for any supply voltage from a single 5V supply up to ±15V supplies.
Note 16: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with 1 mA load. Thus, theseparameters define an error band and take into account the worst-case effects of voltage gain and RS.
Note 17: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive.
Note 18: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. Do not short the strobepin to ground; it should be current driven at 3 to 5 mA.
Note 19: Human body model, 1.5 kΩ in series with 100 pF.
8.1 CIRCUIT TECHNIQUES FOR AVOIDINGOSCILLATIONS IN COMPARATOR APPLICATIONS
When a high-speed comparator such as the LM111 is usedwith fast input signals and low source impedances, the out-put response will normally be fast and stable, assuming thatthe power supplies have been bypassed (with 0.1 µF disccapacitors), and that the output signal is routed well awayfrom the inputs (pins 2 and 3) and also away from pins 5 and6.
However, when the input signal is a voltage ramp or a slowsine wave, or if the signal source impedance is high (1 kΩ to100 kΩ), the comparator may burst into oscillation near thecrossing-point. This is due to the high gain and wide band-width of comparators like the LM111. To avoid oscillation orinstability in such a usage, several precautions are recom-mended, as shown in Figure 1 below.
1. The trim pins (pins 5 and 6) act as unwanted auxiliaryinputs. If these pins are not connected to a trim-pot, theyshould be shorted together. If they are connected to atrim-pot, a 0.01 µF capacitor C1 between pins 5 and 6will minimize the susceptibility to AC coupling. A smallercapacitor is used if pin 5 is used for positive feedback asin Figure 1.
2. Certain sources will produce a cleaner comparator out-put waveform if a 100 pF to 1000 pF capacitor C2 isconnected directly across the input pins.
3. When the signal source is applied through a resistivenetwork, RS, it is usually advantageous to choose an RS'of substantially the same value, both for DC and fordynamic (AC) considerations. Carbon, tin-oxide, andmetal-film resistors have all been used successfully incomparator input circuitry. Inductive wirewound resistorsare not suitable.
4. When comparator circuits use input resistors (eg. sum-ming resistors), their value and placement are particu-larly important. In all cases the body of the resistorshould be close to the device or socket. In other wordsthere should be very little lead length or printed-circuitfoil run between comparator and resistor to radiate orpick up signals. The same applies to capacitors, pots,etc. For example, if RS=10 kΩ, as little as 5 inches oflead between the resistors and the input pins can result
in oscillations that are very hard to damp. Twisting theseinput leads tightly is the only (second best) alternative toplacing resistors close to the comparator.
5. Since feedback to almost any pin of a comparator canresult in oscillation, the printed-circuit layout should beengineered thoughtfully. Preferably there should be agroundplane under the LM111 circuitry, for example, oneside of a double-layer circuit card. Ground foil (or, posi-tive supply or negative supply foil) should extend be-tween the output and the inputs, to act as a guard. Thefoil connections for the inputs should be as small andcompact as possible, and should be essentially sur-rounded by ground foil on all sides, to guard againstcapacitive coupling from any high-level signals (such asthe output). If pins 5 and 6 are not used, they should beshorted together. If they are connected to a trim-pot, thetrim-pot should be located, at most, a few inches awayfrom the LM111, and the 0.01 µF capacitor should beinstalled. If this capacitor cannot be used, a shieldingprinted-circuit foil may be advisable between pins 6 and7. The power supply bypass capacitors should be lo-cated within a couple inches of the LM111. (Some othercomparators require the power-supply bypass to be lo-cated immediately adjacent to the comparator.)
6. It is a standard procedure to use hysteresis (positivefeedback) around a comparator, to prevent oscillation,and to avoid excessive noise on the output because thecomparator is a good amplifier for its own noise. In thecircuit of Figure 2, the feedback from the output to thepositive input will cause about 3 mV of hysteresis. How-ever, if RS is larger than 100Ω, such as 50 kΩ, it wouldnot be reasonable to simply increase the value of thepositive feedback resistor above 510 kΩ. The circuit ofFigure 3 could be used, but it is rather awkward. See thenotes in paragraph 7 below.
Leakage Currents
DS005704-72
LM11
1/LM
211/
LM31
1
www.national.com 10
8.0 Application Hints (Continued)
7. When both inputs of the LM111 are connected to activesignals, or if a high-impedance signal is driving thepositive input of the LM111 so that positive feedbackwould be disruptive, the circuit of Figure 1 is ideal. Thepositive feedback is to pin 5 (one of the offset adjust-ment pins). It is sufficient to cause 1 to 2 mV hysteresisand sharp transitions with input triangle waves from afew Hz to hundreds of kHz. The positive-feedback signalacross the 82Ω resistor swings 240 mV below the posi-
tive supply. This signal is centered around the nominalvoltage at pin 5, so this feedback does not add to theVOS of the comparator. As much as 8 mV of VOS can betrimmed out, using the 5 kΩ pot and 3 kΩ resistor asshown.
8. These application notes apply specifically to the LM111,LM211, LM311, and LF111 families of comparators, andare applicable to all high-speed comparators in general,(with the exception that not all comparators have trimpins).
DS005704-29
Pin connections shown are for LM111H in the H08 hermetic package
FIGURE 1. Improved Positive Feedback
DS005704-30
Pin connections shown are for LM111H in the H08 hermetic package
FIGURE 2. Conventional Positive Feedback
LM111/LM
211/LM311
www.national.com11
8.0 Application Hints (Continued)
9.0 Typical Applications (Pin numbers refer to H08 package)
DS005704-31
FIGURE 3. Positive Feedback with High Source Resistance
Zero Crossing Detector Driving MOS Switch
DS005704-13
100 kHz Free Running Multivibrator
DS005704-14
*TTL or DTL fanout of two
LM11
1/LM
211/
LM31
1
www.national.com 12
9.0 Typical Applications (Pin numbers refer to H08 package) (Continued)
10 Hz to 10 kHz Voltage Controlled Oscillator
DS005704-15
*Adjust for symmetrical square wave time when VIN = 5 mV†Minimum capacitance 20 pF Maximum frequency 50 kHz
Driving Ground-Referred Load
DS005704-16
*Input polarity is reversed when using pin 1 as output.
Using Clamp Diodes to Improve Response
DS005704-17
TTL Interface with High Level Logic
DS005704-18
*Values shown are for a 0 to 30V logic swing and a 15V threshold.†May be added to control speed and reduce susceptibility to noise spikes.
LM111/LM
211/LM311
www.national.com13
9.0 Typical Applications (Pin numbers refer to H08 package) (Continued)
Crystal Oscillator
DS005704-19
Comparator and Solenoid Driver
DS005704-20
Precision Squarer
DS005704-21
*Solid tantalum†Adjust to set clamp level
LM11
1/LM
211/
LM31
1
www.national.com 14
9.0 Typical Applications (Pin numbers refer to H08 package) (Continued)
Low Voltage Adjustable Reference Supply
DS005704-22
*Solid tantalum
Positive Peak Detector
DS005704-23
*Solid tantalum
Zero Crossing Detector Driving MOS Logic
DS005704-24
Negative Peak Detector
DS005704-25
*Solid tantalum
LM111/LM
211/LM311
www.national.com15
9.0 Typical Applications (Pin numbers refer to H08 package) (Continued)
Precision Photodiode Comparator
DS005704-26
*R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by an order of magnitude.
Switching Power Amplifier
DS005704-27
LM11
1/LM
211/
LM31
1
www.national.com 16
9.0 Typical Applications (Pin numbers refer to H08 package) (Continued)
Switching Power Amplifier
DS005704-28
LM111/LM
211/LM311
www.national.com17
10.0 Schematic Diagram (Note 20)
DS005704-5
Note 20: Pin connections shown on schematic diagram are for H08 package.
LM11
1/LM
211/
LM31
1
www.national.com 18
11.0 Connection Diagrams
Note 21: Also available per JM38510/10304
Metal Can Package
DS005704-6
Note: Pin 4 connected to case
Top ViewOrder Number LM111H, LM111H/883 (Note 21) , LM211H or LM311H
See NS Package Number H08C
Dual-In-Line Package
DS005704-34
Top ViewOrder Number LM111J-8, LM111J-8/883 (Note 21),
LM311M, LM311MX or LM311NSee NS Package Number J08A, M08A or N08E
Dual-In-Line Package
DS005704-35
Top ViewOrder Number LM111J/883 (Note 21)
See NS Package Number J14A or N14A
DS005704-33
Order Number LM111W/883 (Note 21), LM111WG/883See NS Package Number W10A, WG10A
Order Number LM111W/883, LM111WG/883NS Package Number W10A, WG10A
LM11
1/LM
211/
LM31
1
www.national.com 22
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
National SemiconductorCorporationAmericasTel: 1-800-272-9959Fax: 1-800-737-7018Email: [email protected]
National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: [email protected]
National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507
www.national.com
LM111/LM
211/LM311
VoltageC
omparator
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
• UIS Capability (Single Pulse and Repetitive Pulse)
• Qualified to AEC Q101
Formerly developmental type 82584
Applications
• Motor / Body Load Control
• ABS Systems
• Powertrain Management
• Injection Systems
• DC-DC converters and Off-line UPS
• Distributed Power Architectures and VRMs
• Primary Switch for 12V and 24V systems
D
G
SDRAIN (FLANGE)
DRAINSOURCE
GATE
TO-262ABFDI SERIES
TO-220ABFDP SERIES
DRAIN
DRAIN
GATE
SOURCE(FLANGE)
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality
systems certification.
Symbol Parameter Ratings UnitsVDSS Drain to Source Voltage 60 V
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
80V/2.5A Peak, High Frequency Full Bridge FET DriverThe HIP4081A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081A can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081A can switch at frequencies up to 1MHz and is well suited to driving Voice Coil Motors, high-frequency switching power amplifiers, and power supplies.
For example, the HIP4081A can drive medium voltage brush motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load.
A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching.
The Application Note for the HIP4081A is the AN9405.
Features
• Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V Logic Levels
• Very Low Power Consumption
• Undervoltage Protection
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Pinout
Ordering Information
PARTNUMBER
TEMP RANGE (oC) PACKAGE PKG. NO.
HIP4081AIP -40 to 85 20 Ld PDIP E20.3
HIP4081AIB -40 to 85 20 Ld SOIC (W) M20.3
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1BHB
BHI
DIS
VSS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
HIP4081A (PDIP, SOIC)TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrapdiode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin tomaintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI highlevel input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high levelinput. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to15V (no greater than VDD).
4 VSS Chip negative supply, generally will be ground.
5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connectedexternally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V(no greater than VDD).
6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connectedexternally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V(no greater than VDD).
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI highlevel input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high levelinput. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay ofboth high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees noshoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay ofboth low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees noshoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrapdiode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin tomaintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side ofbootstrap capacitor to this pin.
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.
16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side ofbootstrap capacitor to this pin.
20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
HIP4081A
7
HIP4081A
Timing Diagrams
FIGURE 1. INDEPENDENT MODE
FIGURE 2. BISTATE MODE
FIGURE 3. DISABLE FUNCTION
U/V = DIS = 0
XLI
XHI
XLO
XHO
TLPHL THPHL
THPLH TLPLH TR(10% - 90%)
TF(10% - 90%)
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4.
FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC
HIP
4081A
14
HIP
4081A
R22 1
Q3
L1
JMPR2
JMP
R5
R31
R33
CR2
R23
R24
R27
R28
R26
1
Q4
1
Q2JMPR3
U1
R21
GND
L2
C3
C4
JMPR4
JMPR1
R30
CR1
U2
R34
R32
I
O
C8R29
C7
C6
C5
CY
CX
1
Q1
COM+12V
B+
IN1
IN2
AHO
BHO
ALO
BLOBLS
BLS
LDEL
HD
EL
DIS
ALS
ALS
O
+ +
HIP
4080
/81
FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN
HIP
4081A
15
HIP4081A
E20.3 (JEDEC MS-001-AD ISSUE D)20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 20 20 9
Rev. 0 12/93
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
CL
E
eA
C
eB
eC
-B-
E1INDEX
1 2 3 N/2
N
AREA
SEATING
BASEPLANE
PLANE
-C-
D1
B1B
e
D
D1
AA2
L
A1
-A-
0.010 (0.25) C AM B S
eA-C-
Dual-In-Line Plastic Packages (PDIP)
HIP4081A
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate andreliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resultfrom its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HIP4081A
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
INDEXAREA
E
D
N
1 2 3
-B-
0.25(0.010) C AM B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M20.3 (JEDEC MS-013-AC ISSUE C)20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N 20 20 7
α 0o 8o 0o 8o -
Rev. 0 12/93
Small Outline Plastic Packages (SOIC)
HIP4081AHIP4081A
LF155/LF156/LF256/LF257/LF355/LF356/LF357JFET Input Operational AmplifiersGeneral DescriptionThese are the first monolithic JFET input operational ampli-fiers to incorporate well matched, high voltage JFETs on thesame chip with standard bipolar transistors (BI-FET™ Tech-nology). These amplifiers feature low input bias and offsetcurrents/low offset voltage and offset voltage drift, coupledwith offset adjust which does not degrade drift orcommon-mode rejection. The devices are also designed forhigh slew rate, wide bandwidth, extremely fast settling time,low voltage and current noise and a low 1/f noise corner.
FeaturesAdvantagesn Replace expensive hybrid and module FET op ampsn Rugged JFETs allow blow-out free handling compared
with MOSFET input devicesn Excellent for low noise applications using either high or
low source impedance — very low 1/f cornern Offset adjust does not degrade drift or common-mode
rejection as in most monolithic amplifiersn New output stage allows use of large capacitive loads
(5,000 pF) without stability problemsn Internal compensation and large differential input voltage
capability
Applicationsn Precision high speed integratorsn Fast D/A and A/D convertersn High impedance buffersn Wideband, low noise, low drift amplifiers
n Logarithmic amplifiersn Photocell amplifiersn Sample and Hold circuits
Common Featuresn Low input bias current: 30pAn Low Input Offset Current: 3pAn High input impedance: 1012Ωn Low input noise current:n High common-mode rejection ratio: 100 dBn Large dc voltage gain: 106 dB
Uncommon FeaturesLF155/LF355
LF156/LF256/LF356
LF257/LF357(AV=5)
Units
j Extremelyfast settlingtime to0.01%
4 1.5 1.5 µs
j Fast slewrate
5 12 50 V/µs
j Wide gainbandwidth
2.5 5 20 MHz
j Low inputnoisevoltage
20 12 12
Simplified Schematic
00564601
*3pF in LF357 series.
BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation.
December 2001LF155/LF156/LF256/LF257/LF355/LF356/LF357
AC Electrical CharacteristicsTA = TJ = 25˚C, VS = ±15V
Symbol Parameter Conditions
LF155/355 LF156/256/356B
LF156/256/356/LF356B
LF257/357
Units
Typ Min Typ Typ
SR Slew Rate LF155/6:AV=1,
5 7.5 12 V/µs
LF357: AV=5 50 V/µs
GBW Gain Bandwidth Product 2.5 5 20 MHz
ts Settling Time to 0.01% (Note 7) 4 1.5 1.5 µs
en Equivalent Input NoiseVoltage
RS=100Ωf=100 Hz 25 15 15
f=1000 Hz 20 12 12
in Equivalent Input CurrentNoise
f=100 Hz 0.01 0.01 0.01
f=1000 Hz 0.01 0.01 0.01
CIN Input Capacitance 3 3 3 pF
Notes for Electrical CharacteristicsNote 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,TA. The maximum available power dissipation at any temperature is PD=(TJMAX−TA)/θJA or the 25˚C PdMAX, whichever is less.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: Unless otherwise stated, these test conditions apply:
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com3
Notes for Electrical Characteristics (Continued)
LF155/156 LF256/257 LF356B LF355/6/7
Supply Voltage, VS ±15V ≤ VS ≤ ±20V ±15V ≤ VS ≤ ±20V ±15V ≤ VS ±20V VS= ±15V
TA −55˚C ≤ TA ≤ +125˚C −25˚C ≤ TA ≤ +85˚C 0˚C ≤ TA ≤ +70˚C 0˚C ≤ TA ≤ +70˚C
THIGH +125˚C +85˚C +70˚C +70˚C
and VOS, IB and IOS are measured at VCM = 0.
Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5µV/˚C typically) for each mV of adjustment from its originalunadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.
Note 5: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, TJ. Due to limitedproduction test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambienttemperature as a result of internal power dissipation, Pd. TJ = TA + θJA Pd where θJA is the thermal resistance from junction to ambient. Use of a heat sink isrecommended if input bias current is to be kept to a minimum.
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kΩ resistors for the LF155/6. It is the time required for the error voltage (the voltageat the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, AV = −5,the feedback resistor from output to input is 2kΩ and the output step is 10V (See Settling Time Test Circuit).
Note 8: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outsideguaranteed limits.
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwisespecified.
Input Bias Current Input Bias Current
00564637 00564638
Input Bias Current Voltage Swing
00564639 00564640
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 4
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwisespecified. (Continued)
Supply Current Supply Current
00564641 00564642
Negative Current Limit Positive Current Limit
00564643 00564644
Positive Common-ModeInput Voltage Limit
Negative Common-ModeInput Voltage Limit
00564645
00564646
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com5
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwisespecified. (Continued)
Open Loop Voltage Gain Output Voltage Swing
00564647 00564648
Typical AC Performance CharacteristicsGain Bandwidth Gain Bandwidth
0056464900564650
Normalized Slew Rate Output Impedance
0056465100564652
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 6
Typical AC Performance Characteristics (Continued)
Output Impedance LF155 Small Signal Pulse Response, A V = +1
00564653
00564605
LF156 Small Signal Pulse Response, A V = +1 LF155 Large Signal Pulse Response, A V = +1
00564606 00564608
LF156 Large Signal PulsResponse, A V = +1 Inverter Settling Time
00564609
00564655
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com7
Typical AC Performance Characteristics (Continued)
Inverter Settling Time Open Loop Frequency Response
00564656 00564657
Bode Plot Bode Plot
00564658 00564659
Bode Plot Common-Mode Rejection Ratio
00564660 00564661
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 8
Typical AC Performance Characteristics (Continued)
Power Supply Rejection Ratio Power Supply Rejection Ratio
00564662 00564663
Undistorted Output Voltage Swing Equivalent Input Noise Voltage
00564664
00564665
Equivalent Input NoiseVoltage (Expanded Scale)
00564666
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com9
Detailed Schematic
00564613
*C = 3pF in LF357 series.
Connection Diagrams (Top Views)
Metal Can Package (H)
00564614
Order Number LF155H, LF156H, LF256H, LF257H,LF356BH, LF356H, or LF357H
See NS Package Number H08C*Available per JM38510/11401 or JM38510/11402
Dual-In-Line Package (M and N)
00564629
Order Number LF356M, LF356MX, LF355N, or LF356NSee NS Package Number M08A or N08E
Application HintsThese are op amps with JFET input devices. These JFETshave large reverse breakdown voltages from gate to sourceand drain eliminating the need for clamps across the inputs.Therefore large differential input voltages can easily be ac-commodated without a large increase in input current. Themaximum differential input voltage is independent of thesupply voltages. However, neither of the input voltagesshould be allowed to exceed the negative supply as this willcause large currents to flow which can result in a destroyedunit.
Exceeding the negative common-mode limit on either inputwill force the output to a high state, potentially causing a
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 10
Application Hints (Continued)
reversal of phase to the output. Exceeding the negativecommon-mode limit on both inputs will force the amplifieroutput to a high state. In neither case does a latch occursince raising the input back within the common-mode rangeagain puts the input stage and thus the amplifier in a normaloperating mode.
Exceeding the positive common-mode limit on a single inputwill not change the phase of the output however, if bothinputs exceed the limit, the output of the amplifier will beforced to a high state.
These amplifiers will operate with the common-mode inputvoltage equal to the positive supply. In fact, thecommon-mode voltage can exceed the positive supply byapproximately 100 mV independent of supply voltage andover the full operating temperature range. The positive sup-ply can therefore be used as a reference on an input as, forexample, in a supply current monitor and/or limiter.
Precautions should be taken to ensure that the power supplyfor the integrated circuit never becomes reversed in polarityor that the unit is not inadvertently installed backwards in asocket as an unlimited current surge through the resultingforward diode within the IC could cause fusing of the internalconductors and result in a destroyed unit.
All of the bias currents in these amplifiers are set by FETcurrent sources. The drain currents for the amplifiers aretherefore essentially independent of supply voltage.
As with most amplifiers, care should be taken with leaddress, component placement and supply decoupling in orderto ensure stability. For example, resistors from the output toan input should be placed with the body close to the input tominimize “pickup” and maximize the frequency of the feed-back pole by minimizing the capacitance from the input toground.
A feedback pole is created when the feedback around anyamplifier is resistive. The parallel resistance and capacitancefrom the input of the device (usually the inverting input) to ACground set the frequency of the pole. In many instances thefrequency of this pole is much greater than the expected 3dBfrequency of the closed loop gain and consequently there isnegligible effect on stability margin. However, if the feedbackpole is less than approximately six times the expected 3 dBfrequency a lead capacitor should be placed from the outputto the input of the op amp. The value of the added capacitorshould be such that the RC time constant of this capacitorand the resistance it parallels is greater than or equal to theoriginal feedback pole time constant.
Typical Circuit ConnectionsVOS Adjustment
00564667
• VOS is adjusted with a 25k potentiometer
• The potentiometer wiper is connected to V+
• For potentiometers with temperature coefficient of 100ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/˚C/mV of adjustment
• Typical overall drift: 5µV/˚C ±(0.5µV/˚C/mV of adj.)
Driving Capacitive Loads
00564668
* LF155/6 R = 5k
LF357 R = 1.25k
Due to a unique output stage design, these amplifiershave the ability to drive large capacitive loads and stillmaintain stability. CL(MAX) . 0.01µF.
Overshoot ≤ 20%
Settling time (ts) . 5µs
LF357. A Large Power BW Amplifier
00564615
For distortion ≤ 1% and a 20 Vp-p VOUT swing, power bandwidth is:500kHz.
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com11
Typical ApplicationsSettling Time Test Circuit
00564616
• Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5
• FET used to isolate the probe capacitance
• Output = 10V step
• AV = −5 for LF357
Large Signal Inverter Output, V OUT (from Settling Time Circuit)
LF355
00564617
LF356
00564618
LF357
00564619
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 12
Typical Applications (Continued)
Low Drift Adjustable Voltage Reference
00564620
• ∆ VOUT/∆T = ±0.002%/˚C
• All resistors and potentiometers should be wire-wound
• VOS adjust the LF156 to minimize quiescent error
• RT: Tel Labs type Q81 + 0.3%/˚C
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com13
Typical Applications (Continued)
Precision Current Monitor
00564631
• VO = 5 R1/R2 (V/mA of IS)
• R1, R2, R3: 0.1% resistors
• Use LF155 for
j Common-mode range to supply range
j Low IBj Low VOS
j Low Supply Current
8-Bit D/A Converter with Symmetrical Offset Binary Operation
00564632
• R1, R2 should be matched within ±0.05%
• Full-scale response time: 3µs
EO B1 B2 B3 B4 B5 B6 B7 B8 Comments
+9.920 1 1 1 1 1 1 1 1 Positive Full-Scale
+0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale
−0.040 0 1 1 1 1 1 1 1 (−) Zero-Scale
−9.920 0 0 0 0 0 0 0 0 Negative Full-Scale
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 14
Typical Applications (Continued)
Wide BW Low Noise, Low Drift Amplifier
00564670
• Parasitic input capacitance C1 . (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts withfeedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1.
Boosting the LF156 with a Current Amplifier
00564673
• IOUT(MAX).150mA (will drive RL≥ 100Ω)
• No additional phase shift added by the current amplifier
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com15
Typical Applications (Continued)
3 Decades VCO
00564624
R1, R4 matched. Linearity 0.1% over 2 decades.
Isolating Large Capacitive Loads
00564622
• Overshoot 6%
• ts 10µs
• When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX):
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 16
Typical Applications (Continued)
Low Drift Peak Detector
00564623
• By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf.
• Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp.
• Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2.
• Maximum input frequency should be << 1⁄2πRfCD2 where CD2 is the shunt capacitance of D2.
Non-Inverting Unity Gain Operation for LF157
00564675
Inverting Unity Gain for LF157
00564625
LF155/LF156/LF256/LF257/LF355/LF356/LF357
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Typical Applications (Continued)
High Impedance, Low Drift Instrumentation Amplifier
00564626
• System VOS adjusted via A2 VOS adjust
• Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift
LF15
5/LF
156/
LF25
6/LF
257/
LF35
5/LF
356/
LF35
7
www.national.com 18
Typical Applications (Continued)
Fast Sample and Hold
00564633
• Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)
• Acquisition time TA, estimated by:
• LF156 develops full Sr output capability for VIN ≥ 1V
• Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop
• Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2
LF155/LF156/LF256/LF257/LF355/LF356/LF357
www.national.com19
Typical Applications (Continued)
High Accuracy Sample and Hold
00564627
• By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.
No VOS adjust required for A2.
• TA can be estimated by same considerations as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
Molded Dual-In-Line Package (N)Order Number LF356N
NS Package Number N08E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: [email protected]
National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507
www.national.com
LF155/LF156/LF256/LF257/LF355/LF356/LF357JFE
TInputO
perationalAm
plifiers
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Low Power Consumption, 40-µA Max ICC Typical tpd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
description/ordering information
The ’HC74 devices contain two independentD-type positive-edge-triggered flip-flops. A lowlevel at the preset (PRE) or clear (CLR) inputs setsor resets the outputs, regardless of the levels ofthe other inputs. When PRE and CLR are inactive(high), data at the data (D) input meeting the setuptime requirements are transferred to the outputson the positive-going edge of the clock (CLK)pulse. Clock triggering occurs at a voltage leveland is not directly related to the rise time of CLK.Following the hold-time interval, data at theD input can be changed without affecting thelevels at the outputs.
ORDERING INFORMATION
TA PACKAGE† ORDERABLEPART NUMBER
TOP-SIDEMARKING
PDIP – N Tube of 25 SN74HC74N SN74HC74N
Tube of 50 SN74HC74D
SOIC – D Reel of 2500 SN74HC74DR HC74
Reel of 250 SN74HC74DT
–40°C to 85°C SOP – NS Reel of 2000 SN74HC74NSR HC74
SSOP – DB Reel of 2000 SN74HC74DBR HC74
Tube of 90 SN74HC74PW
TSSOP – PW Reel of 2000 SN74HC74PWR HC74
Reel of 250 SN74HC74PWT
CDIP – J Tube of 25 SNJ54HC74J SNJ54HC74J
–55°C to 125°C CFP – W Tube of 150 SNJ54HC74W SNJ54HC74W
LCCC – FK Tube of 55 SNJ54HC74FK SNJ54HC74FK† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR1D
1CLK1PRE
1Q1Q
GND
VCC2CLR2D2CLK2PRE2Q2Q
SN54HC74 . . . J OR W PACKAGESN74HC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2DNC2CLKNC2PRE
1CLKNC
1PRENC1Q
1D 1CLR
NC
2Q 2QV 2C
LR
1QG
ND
NC
SN54HC74 . . . FK PACKAGE(TOP VIEW)
CC
NC – No internal connection
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.
SN54HC74, SN74HC74DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H† H†
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0† This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive(high) level.
logic diagram (positive logic)
PRE
CLK
D
CLR
Q
Q
C
C
C
C
C
C
C
C
C
C
TG
TG TG TG
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2. The package thermal impedance is calculated in accordance with JESD 51-7.
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)
PARAMETER TEST CONDITIONS VCCTA = 25°C SN54HC74 SN74HC74
UNITPARAMETER TEST CONDITIONS VCCMIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 4 80 40 µA
Ci 2 V to 6 V 3 10 10 10 pF
SN54HC74, SN74HC74DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwisenoted)
VCCTA = 25°C SN54HC74 SN74HC74
UNITVCCMIN MAX MIN MAX MIN MAX
UNIT
2 V 6 4.2 5
fclock Clock frequency 4.5 V 31 21 25 MHz
6 V 0 36 0 25 0 29
2 V 100 150 125
PRE or CLR low 4.5 V 20 30 25
t Pulse duration6 V 17 25 21
nstw Pulse duration2 V 80 120 100
ns
CLK high or low 4.5 V 16 24 20
6 V 14 20 17
↑
2 V 100 150 125
↑
Data 4.5 V 20 30 25
t Setup time before CLK↑6 V 17 25 21
nstsu Setup time before CLK↑2 V 25 40 30
ns
PRE or CLR inactive 4.5 V 5 8 6
6 V 4 7 5
↑
2 V 0 0 0
th Hold time, data after CLK↑ 4.5 V 0 0 0 ns
6 V 0 0 0
switching characteristics over recommended operating free-air temperature range, CL = 50 pF(unless otherwise noted) (see Figure 1)
PARAMETERFROM TO
VCCTA = 25°C SN54HC74 SN74HC74
UNITPARAMETER(INPUT) (OUTPUT)
VCCMIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 10 4.2 5
fmax 4.5 V 31 50 21 25 MHz
6 V 36 60 25 29
2 V 70 230 345 290
PRE or CLR Q or Q 4.5 V 20 46 69 58
t d6 V 15 39 59 49
nstpd2 V 70 175 250 220
ns
CLK Q or Q 4.5 V 20 35 50 44
6 V 15 30 42 37
2 V 28 75 110 95
tt Q or Q 4.5 V 8 15 22 19 ns
6 V 6 13 19 16
operating characteristics, TA = 25°CPARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 35 pF
VOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMSPULSE DURATIONS
thtsu
50%
50%50%10%10%
90% 90%
VCC
VCC
0 V
0 V
tr tf
ReferenceInput
DataInput
50%High-Level
Pulse 50%VCC
0 V
50% 50%
VCC
0 V
tw
Low-LevelPulse
VOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50%10%10%
90% 90%
VCC
VOH
VOL
0 V
tr tf
Input
In-PhaseOutput
50%
tPLH tPHL
50% 50%10% 10%
90%90%VOH
VOLtrtf
tPHL tPLH
Out-of-PhaseOutput
TestPoint
From OutputUnder Test
CL = 50 pF(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.C. For clock inputs, fmax is measured when the input duty cycle is 50%.D. The outputs are measured one at a time with one input transition per measurement.E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MCFP002A – JANUARY 1995 – REVISED FEBRUARY 2002
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F14) CERAMIC DUAL FLATPACK
0.360 (9,14)0.250 (6,35)
87
141
0.235 (5,97)
0.004 (0,10)
0.026 (0,66)
4 Places
0.015 (0,38)
0.045 (1,14)
0.335 (8,51)
0.008 (0,20)
0.045 (1,14)
Base and Seating Plane
0.005 (0,13) MIN
0.019 (0,48)
0.390 (9,91)
0.260 (6,60)
0.080 (2,03)
4040180-2/C 02/02
0.360 (9,14)0.250 (6,35)
0.280 (7,11) MAX
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification only.E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
MECHANICAL DATA
MLCC006B – OCTOBER 1996
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358(9,09)
MAX
(11,63)
0.560(14,22)
0.560
0.458
0.858(21,8)
1.063(27,0)
(14,22)
ANO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342(8,69)
MIN
(11,23)
(16,26)0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)0.938
(28,99)1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)0.064 (1,63)
(7,80)0.307
(10,31)0.406
(12,58)0.495
(12,58)0.495
(21,6)0.850
(26,6)1.047
0.045 (1,14)
0.045 (1,14)0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
121314151618 17
11
10
8
9
7
5
432
0.020 (0,51)0.010 (0,25)
6
12826 27
19
21B SQ
A SQ22
23
24
25
20
0.055 (1,40)0.045 (1,14)
0.028 (0,71)0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a metal lid.D. The terminals are gold plated.E. Falls within JEDEC MS-004
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
BB AC AD
0.325 (8,26)0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060(26,92)
0.940(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775(19,69)
(18,92)0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY20 pin vendor option
4040049/E 12/2002
9
80.070 (1,78)
A
0.045 (1,14)0.020 (0,51) MIN
16
1
0.015 (0,38)0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)0.260 (6,60)
M0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100VARIATION
AAC
D
D
D0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE8 PINS SHOWN
8
0.197(5,00)
A MAX
A MIN(4,80)0.189 0.337
(8,55)
(8,75)0.344
14
0.386(9,80)
(10,00)0.394
16DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)0.010 (0,25)
0.010 (0,25)
0.016 (0,40)0.044 (1,12)
0.244 (6,20)0.228 (5,80)
0.020 (0,51)0.014 (0,35)
1 4
8 5
0.150 (3,81)0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).D. Falls within JEDEC MS-012
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,207,40
0,550,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,605,00
15
0,22
14
A
28
1
2016
6,506,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M0,15
0°–8°
0,10
0,090,25
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-153
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