Chapter 8 Basics of SOC Testing

Chapter 8Chapter 8Basics of SOC TestingBasics of SOC Testing

Jin-Fu LiAdvanced Reliable Systems (ARES) LabAdvanced Reliable Systems (ARES) LabDepartment of Electrical Engineering

National Central UniversityNational Central UniversityJhongli, Taiwan

Outline

IntroductionSOC Test ChallengeSOC Test ChallengeSOC Test Access MechanismsSOC T t C t l A hit tSOC Test Control Architectures

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

What is an SOC? Definition

Integration of multiple cores (e.g., microprocessor, digital signal processor, RAM, ROM, flash memory, I/Os, and analog components which make a complete system) onto a single chip complete system) onto a single chip

FPGAADC

DSPCPU

FPGAFlash Memory

UDL

ADC

DSPCPU

DRAM

UDL

MPEG SRAM SRAMDRAM


What are Cores? Definition

Predefined, pre-verified complex functional blocks, also k IP i l known as IPs, virtual components

ExamplesP C ARM MIPS IBM P PCProcessor Cores: ARM, MIPS, IBM PowerPCPeripherals: MMU, DMA ControllerInterface: PCI USB UARTInterface: PCI, USB, UARTMultimedia: JPEG compression, MPEG decoderNetworking: Ethernet Controller, MAC

Various core description levelsSoft cores: register-transfer level (synthesizable HDL)Firm cores: gate-level netlist (Verilog netlist)Hard cores: layout (GDS2)


Traditional & Core-Based IC Design

Traditional IC designIC is designed from scratchgReuse of small modules: standard-cell library and memory modules

Core-based IC designReuse of large modules: cores, IP, virtual Reuse of large modules: cores, IP, virtual componentsDivide-and-conquer design methodologyq g gyDefinition of standards to make reuse easyReduce time-to-market


Difference Between SOB and SOC

IC Design

System-on-Board (SOB)

Core Design

System-on-Chip (SOC)

g

IC Verification

IC M f t i

Core Verification

AnalogyIC Manufacturing

IC Test

AnalogyReuse of predeisgnedcomponents in a system

SOB Design SOC DesignDifference

Cores in SOC are g

SOB Verification

SO f

SOC Verification

SOC M f t i

fabricated and tested inthe final system

SOB Manufacturing

SOB Test

SOC Manufacturing

SOC Test [Zorian, et al.-ITC97]


What are The Test Challenges? Distributed design and test development

Mixed technologies: logic, processor, memory, g g p yanalog

Need various ATPG/DFT/BIST/other techniques

Multiple hardware description levels for coresNeed test plan for the various levels

Diff t id d SOC t t Different core providers and SOC test developers

Need standard for test integrationNeed standard for test integration

Deeply embedded coresNeed electronic test access mechanismNeed electronic test access mechanism

Core/test reuseN d l d l t t h i


Need plug-and-play test mechanism

What are The Test Challenges? Hierarchical core reuse

Need hierarchical test management

SOC-level test optimizationTest time can be extremely large

Need parallel testing or test schedulingTest power must be considered

N d l d i t t h d liNeed low-power design or test schedulingTestable design automation

Need new testable design tools and flowNeed new testable design tools and flowTest economic consideration

Need to determine test strategy and overall test planeed to dete e test st ategy a d o e a test p a

SOC yield improvementLarge amount of defect-sensitive memory cores


Large amount of defect sensitive memory coresNeed cost-effective repair techinques

Generic Test Access Structure

FPGA

Flash MemoryADC

Wrapper

DSPCPU UDL

SinkTAM

DRAM

Source Test Access Mechanism (TAM)TAM

MPEG SRAM SRAMDRAM

[Y. Zorian, et al.-ITC98]


1500 Test Scalable Structure

User Defined Parallel TAMSourceSource SinkSink

1500 Wrapper

TAMTAM--outoutTAMTAM--inin

1500 Wrapper

TAMTAM--outoutTAMTAM--inin

Core1

1500 Wrapper

CoreN

1500 Wrapper

FinFin FoutFout FinFin FoutFout

WIR WIRWSIWSI WSIWSIWSOWSO WSOWSO

User Defined

WSC

User-Defined Test Controller


1500 Parallel TAM Configuration

WPC Daisychained TAM

WPI WPO

WPPENA ENA WPP WPPENA

Core Core Core

WrapperWSP

WSOWSIWrapper

WSPWrapper

WSPWSPWSI

WSC

WSP WSP


Standardized Plug & Play Wrapper Serial Ports

1500 Parallel TAM Configuration

WPC Bussed TAM

WPI WPO


Core Core Core

WrapperWSO

Wrapper WrapperWSP

WSOWSI

WSC

WSP WSP


P1500 Parallel TAM Configuration

Direct Access TAMWPOWPI

WPC

WPIWPC

WPOWPO

WPIWPC

WPI


WPI WPI

Core Core Core

WrapperWSO

Wrapper WrapperWSP

WSOWSI

WSC

WSP WSP


TAM ImplementationsMany TAM implementation have been reportedExamples:p

Multiplexed accessReused system bus (AMBA)TransparencyBoundary ScanScalable TAMs (Test bus, TestRail)

On one SOC, different TAMs may co-exist


Multiplexed Access [E. J. Marinissen, ITC98]

(a): Multiplexing architecture; (b) daisy-chain architecture; (c) Distributed architecture

Core A Core AN

Core Ana

N

Core B Core B Core Bnb

na

N

Core C Core C Core Cnc

ICIC IC

( )


(a) (b) (c)

Test Shell/TestRail [E. J. Marinissen, ITC98]

Every core is wrapped with a TestShellThe TestShell is the test data transport mechanismTCM is a standardized test control mechanism in h Sh llthe TestShell

The host is the environment in which the core is embeddedembedded

hostTestShell TestShell

TCM TCMTCM

IP A IP BTestRail


Test Shell/TestRail [E. J. Marinissen, ITC98]

TCMTCMShell

host

Core A

TCM

TestRail 1

1616

16

TCM

Core B

TCM

Core C

16

16

ShellShell

Core B Core C

TCM

16 16

Shell

TCMCore E

TCM

2ShellShell

Core D Core FTestRail 210

810


SOC Test Control ArchitecturesTAP Linking Module (TLM) architecture

ICB

ICNTC CBSR CBSRCBSR

BSR

CBSR

NTC TAP’ed

Core

TAP’ed

Core

TAP’ed

Core

TAP1

NTC

TAP2 TAP3 TAP4

X Y Z

TAP Linking Module (TLM)

SEL ENA SELSELSEL ENA ENAENA

TDI TCK TMS TRST* TDO

The TLM operates to enable and connect one or more

[Lee Whetsel, ITC97]


The TLM operates to enable and connect one or more TAPs to be accessed via the IC’s test pins

SOC Test Control ArchitecturesTAP TLM:

TLM architecture TAP TLM:

SEL[Lee Whetsel, ITC97]

TAP1 TAP4TAP3TAP2

M

Enable 1,2,3,4

TDO4 Enable

LC4LC3LC2

3SMU

MUX

TDO4TDO3TDO2TDO1

Enable

SEL1 SEL2 SEL3 SEL4

TLM TAP:

LC

ENA

TAP Linking Module (TLM)

XSEL1 SEL2 SEL3 SEL4

TDO

ENA1 ENA2 ENA3 ENA4

ENA


Reset*

TLM-Select

TAPSEL0,1

The TLM communicates with TAPs via select (SEL), enable (ENA) and Link Control (LC). After power up, or test reset, the TLM



( ) p p, ,defaults to connecting TAP1 to the test pins

SOC Test Control ArchitecturesModified state diagram

TMS=1 Test Logic Reset

ENA:TMS=1:0Or TMS=0

ResetData

Register Scan

InstructionRegister

SENA:TMS=0:xENA:TMS=1:1Run Test/

Idle

ScanTMS=1

ScanTMS=1

Select DRS Select IRS

Capture DR

Shift DR Shift IR

Capture IR

Unlinked Stroble

Update DR Update IR

TMS=1ENA:TMS=1:1

Stroble

State

SENA:TMS=1:1

ENA:TMS=1:0Or

TMS 0

Link change state

ENA=0,TAP disableENA=1,TAP enable


ENA:TMS=0:x TMS=0state

SOC Test Control ArchitecturesCAS-BUS architecture

T t

[Benabdenebi, DATE00]

TestControllerN

Core Access Switch

CAS 1 CAS 2 CAS 3 CAS 4 CAS 5

P

CORE 1 CORE 2 CORE 3 CORE 4 CORE 5CORE 1 CORE 2 CORE 3 CORE 4 CORE 5


SOC Test Control ArchitecturesTest types supported by CAS-BUS

CAS1(N/P)

CAS2(N/1)

CAS3(N/P)NN

BIST

( )(N/P) ( )(N/1) ( )(N/P)NNPP PP

BIST CAS1

core1

CAS2

core2core1 core2

sourcesource

sinksink

SOC TestController

core3 core4

CAS4 CAS3

ee

CAS4

CAS4 CAS3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22( )

CAS4(N/1 or P)

SOC Test Control ArchitecturesCAS Architecture

cfcftcktck

updateupdatecfcf

configconfig

c0c0 c1c1 ckck

configconfig configconfig

SWITCH N/P

c0c0 c1c1 ckck

controlcontrol SISI SOSOInstruction registerInstruction registerInstruction registerInstruction register

1500 Wrapper1500 Wrapper

IP COREIP CORE


IP COREIP CORE

SOC Test Control ArchitecturesCAS functional modes

Instruction configconfig

Configration mode Bypass mode Test mode


Configration mode Bypass mode Test mode

Hierarchical Test Methodology [J.-F. Li, et al.,IEEE Micro 02]

HTM1

TRST_UP TCK_UP TDO_UPTMS_UPTDI_UP

TDI_C TCS_DN TDO_CTDO_HTDI_HECS

MBIWCI TAPWCI

HTM2

MBI

Core 1(P1500)

WCI WCICore 3(P1500)

Core 4(P1500)

Core 5(JTAG)

Core 2

TAM 2(JTAG)(BISTed RAM)

TAM 1


TAM input TAM output

Hierarchical Test Procedure [J.-F. Li, et al.,IEEE Micro 02]

Test ConfigurationLoad the instructions for the wrappers and ppmemory BIST interfaces (MBIs)

TAM SpecificationpSpecify the cores to be tested by the TAM

Test TransportationTest TransportationImport the test patterns and export the test responsesresponses


An Example

HTM1

TRST_UP TCK_UP TDO_UPTMS_UPTDI_UP

TDI_C TCS_DN TDO_CTDO_HTDI_HECS

MBIWCI TAPWCI

HTM2

MBI

Core 1(1500)

WCI WCICore 3(1500)

Core 4(1500)

Core 5(JTAG)

Core 2

TAM 2(JTAG)(BISTed RAM)

TAM 1


TAM input TAM output

Hierarchical Test Manager

Boundary RegisterTest Manager

Selection Register

Bypass Register

Instruction Decoder

Selection Register

Instruction Register

Instruction Decoder

ECS0FSM WCS Encoder

ECS0ECS1ECS2

TMS TMS_N

TDI

TDI

TMS TCK TRST

TCKTRST

_TCK_NTRST_N

TDI CTDI_UP

TDO_UP

TDI_CTDI_H

TDO_CTDO H

SwitchBox


TDO_HHierarchical Test Interface

Chapter 8 Basics of SOC Testing

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