Chapter 3

Chapter 3-Praposed Scheme

3.1 FIFO

FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of non-trivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading.

A synchronous FIFO is a FIFO where the same clock is used for both reading and writing. An asynchronous FIFO uses different clocks for reading and writing. Asynchronous FIFOs introduce metastability issues. A common implementation of an asynchronous FIFO uses a Gray code (or any unit distance code) for the read and write pointers to ensure reliable flag generation. One further note concerning flag generation is that one must necessarily use pointer arithmetic to generate flags for asynchronous FIFO implementations. Conversely, one may use either a "leaky bucket" approach or pointer arithmetic to generate flags in synchronous FIFO implementations.

Examples of FIFO status flags include: full, empty, almost full, almost empty, etc.

Master Interface

Master SMC

DataReg[31:0]

AddrReg[31:0]

FIFO32x8

Rst_I

ADDR_I[4:0]

Dat_I[31:0]

Cyc_I

Lock_I

Sel_I[7:0]

WE_I

Ws

Clk_I

Clk_I

Rst_I

ACK_I

Dat_I[31:0]

The first known FIFO implemented in electronics was done by Peter Alfke in 1969 at Fairchild Semiconductors. Peter Alfke was a Director at Xilinx.

FIFO full/empty

In hardware FIFO is used for synchronization purposes. It is often implemented as a circular queue, and thus has two pointers:

1. Read Pointer/Read Address Register2. Write Pointer/Write Address Register

Read and write addresses are initially both at the first memory location and the FIFO queue is

Empty.

FIFO EmptyWhen read address register reaches to write address register, the FIFO triggers the Empty signal.

FIFO FULLWhen write address register reaches to read address register, the FIFO triggers the FULL signal.

In both cases, the read and write address end up being equals. To distinguish the two situations, a simple and robust solution is to add one extra bit for each read and write address which is inversed each time the address wrap. With this in place, the conditions are:

FIFO EmptyWhen read address register equals to write address register, the FIFO is empty.

FIFO FULLWhen read address LSBs equal to write address LSBs and extra MSBs are different, the FIFO is full.

3.2 Master State Machine Controller

Here is an example of a designing a master state machine controller, worked out from start to finish.

Step 1: Describe the machine in words.

In this example, we’ll be designing a controller for an elevator. The elevator can be at one of two floors: Ground or First. There is one button that controls the elevator, and it

has two values: Up or Down. Also, there are two lights in the elevator that indicate the current floor: Red for Ground, and Green for First. At each time step, the controller checks the current floor and current input, changes floors and lights in the obvious way.

Step 2: Draw the FSM diagram

DownUp

Up

Ground First[Red off, Green on][Red on, Green off]

Down

In this diagram, the bubbles represent the states, and the arrows represent state transitions. The arrow labels indicate the input value corresponding to the transition. For instance, when the elevator is in the Ground state, and the input is Up, the next state is First. The information in the brackets indicates the output values for the lights in each state.

Step 3: Select numbers to represent states and values

Before converting the above FSM diagram to a circuit, we need to represent every value in our example as a binary number. Here is some convenient numbers to use.

Ground = 0 Down = 0 Off = 0First = 1 Up = 1 On = 1

So here’s the FSM diagram with the words replaced by numbers

01

1

0 1[Red = 0, Green = 1][Red = 1, Green = 0]

0

Step 4: Write the truth table

From the FSM diagram, it’s easy to read off the correct truth table.

CurrentState Input NextState Red Green0 0 0 1 00 1 1 1 01 0 0 0 11 1 1 0 1

Step 5: Draw a “big picture” view of the circuit

Here is the finite-state machine circuit, with many details missing. The variable names have been abbreviated. The dashed boxes indicate the parts (let’s call them “sub-circuits”) that we still need to design.

I OutputR

Next- State DNS CS Sub- CircuitSub- Circuit Flip

CSCLK

FlopG

All FSM circuits will have a form similar to this. Our example has two states, and so we need only one D flip-flop. An FSM with more states would need more flip-flops. Ourexample has one input (labeled “I” in the figure), but in general there may be many inputs, or none at all. Also, an FSM may not have any outputs, in which case the “Output Sub-Circuit” would be omitted.

In our example, the Output Sub- Circuit has two outputs, R and G. To make things simpler, let’s break this into two further sub -circuits: a sub -circuit that computes R,

and another sub-circuit that computes G. After making this change, every dashed box (i.e. every sub-circuit that we still need to design) has exactly one output. This is the easiest form to work with.

Step 6: Find Boolean expressions

For each sub-circuit that we need to design, we’ll write a Boolean expression that expresses its output as a function of its inputs. We derive these expressions from the truth table we wrote in Step 4. There is a very general method for doing this, which we’ll illustrate on the Next-State Sub-Circuit.

The Next-State Sub-Circuit has two inputs, I and CS, and one output, NS. From the truth table, we see that NS is 1 in exactly two cases:

1. CS = 0 and I = 1 2. CS = 1 and I = 1

So we simply write a Boolean expression that covers all and only these cases:

NS = ((not CS) and I) or (CS and I)

Notice that each case is represented by an AND subexpression, and the whole expression is the OR of these subexpressions. This technique can be used on a truth table of any size.

Of course, this Boolean expression can be simplified. To do this, we need some rules of Boolean logic. Here are the most useful ones:

1. A or 1 = 1

2. A or 0 = A 3. A and 1 = A 4. A and 0 = 0 5. (not A) or A = 1 6. (not A) and A = 0 7. not (not A) = A 8. (A or B) and C = (A and C) or (B and C)

Now we can simplify our Boolean expression:

NS = ((not CS) and I) or (CS and I)= ((not CS) or CS) and I [using rule 8]= 1 and I [using rule 5]= I [using rule 3]

And so NS = I. Of course, for this simple example, this could have been easily seen just by inspecting the truth table.

Similarly, we find the Boolean expressions for the other sub-circuits are:

R = not CSG = CS