Chapter 15 Integrated Circuits - FKE · Speed (propagation delay) and power consumption are the two most important performance parameters of a digital IC. Speed-power product (SPP)

Basic IC Characteristics Important IC Parameters Variations of TTL TTL vs CMOS CMOS Operation & Evolution

Chapter 15Integrated Circuits

SKEE1223 Digital Electronics

Mun’im/Arif/Izam

FKE, Universiti Teknologi Malaysia

December 8, 2015


Overview1 Basic IC Characteristics

PackagingLogic FamiliesDatasheets

2 Important IC ParametersDC Supply VoltageLogic LevelsNoise MarginPropagation DelayFanout & FaninPower

3 Variations of TTL4 TTL vs CMOS

Transistor TypesTTL Operation & Evolution

5 CMOS Operation & Evolution


Packaging

Integrated Circuits

Known as IC or chipPackaging

From 4-6 pins to hundredsSeveral packaging technologies availableIn ceramic or plasticThese packages have metal leads that are the conductivewire that connect electricity from the outside world to thesilicon inside the packageLeads between packages are connected with small coppertraces on a printed circuit board (PCB), and the packageleads are soldered to the PCB


Packaging

IC Levels of Integration

Complexity Number of gates ExampleSSI ≤ 12 Individual gatesMSI 12 – 100 Flip-flops, registersLSI 100 – 10,000 MicrocontrollerVLSI 10,000 – 1,000,000 68000 microprocessorULSI ≥ 1,000,000 i7 microprocessor


Logic Families

Logic Families

Logic Family : A collection of different IC’s that havesimilar circuit characteristicsThe circuit design of the basic gate of each logic family isthe sameThe most important parameters for evaluating andcomparing logic families include:

Logic LevelsPower DissipationPropagation delayNoise marginFan-out ( loading )


Logic Families

Example Logic Families

RTL (resistor-transistor logic), DTL (diode-transistor logic)Earliest developed

TTL (transistor-transistor logic)Still available, used occasionally7400 series, refined over generationsMost rugged – least susceptible to electrical damageConsumes more power than CMOS – not suitable forbattery operated devices

CMOS (complimentary metal-oxide semiconductor )Lowest power consumptionUsed to be slow, but fast todayMost common logic family – used in all microprocessorsEasily damaged by static discharge & voltage spikes

BiCMOS, ECL, GaAsSpeedy, but use more power, more expensive or harder touse


Datasheets

Datasheets

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Limits

Symbol Parameter Min Typ Max Unit TestR=onditions

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IIH Input HIGH =urrent—g° md V== XRMdXxRVIN XR/g—RV

IIL InputRLOWR=urrent ——g, md V== XRMdXxRVIN XR—g,RV

IOS ShortR=ircuitR=urrentRMNoteR°i —H— —°—— md V== XRMdX

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Symbol Parameter Min Typ Max Unit TestR=onditions

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PinoutsPackages/DimensionsVoltages and CurrentsNoise MarginPower DissipationPropagation DelaySpeed-Power ProductFan-In, Fan-Out


DC Supply Voltage

DC Supply Voltage

All digital ICs have at least two pins that are connected to thepower rails.

TTL CMOSPositive supply voltage VCC VDDNegative supply voltage GND or VEE VSS

For TTL, VCC is +5 V ± 0.5 V.A TTL gate may be destroyed if the limit is exceeded.

CMOS gates are tolerant to power supply voltagevariations

The power supply ranges from +1.8 V to +18 V.⇓ voltage, ⇓ power consumption⇑ voltage, ⇑ speed.


Logic Levels

Logic Levels

TTL and CMOS use voltages to represent logic levels. Ideally, asingle voltage value is specified for each logic level.

VCC (power) → Logic 1GND (ground) → Logic 0

In reality, a range of voltages is specified for each logic level.


Logic Levels

HIGH Level Electrical Parameters

For a high-state gate driving a second gate, we define:

Parameter DescriptionVOH High-level output voltage, the minimum voltage level

that a logic gate will produce as a logic 1 output.VIH High-level input voltage, the minimum voltage level that

a logic gate will recognize as a logic 1 input. Voltagebelow this level will not be accepted as high.

IOH High-level output current, current that flows from anoutput in the logic 1 state under specified load condi-tions.

IIH High-level input current, current that flows into an inputwhen a logic 1 voltage is applied to that input.


Logic Levels

LOW Level Electrical Parameters

For a low-state gate driving a second gate, we define:

Parameter DescriptionVOL Low-level output voltage, the maximum voltage level

that a logic gate will produce as a logic 0 output.VIL Low-level input voltage, the maximum voltage level that

a logic gate will recognize as a logic 0 input. Voltagebelow this level will not be accepted as low.

IOL Low-level output current, current that flows from an out-put in the logic 0 state under specified load conditions.

IIL Low-level input current, current that flows into an inputwhen a logic 0 voltage is applied to that input.


Logic Levels

TTL vs CMOS Logic Levels

High

Low

Undefined

VCC = 4.5 - 5.5 V

VOH = 2.8 V

VIH = 2.4 V

VIL = 0.8 V

VOL = 0.4 V

TTL.

High

Low

Undefined

VCC = 5 V

VOH = 4.9 V

VIH = 3.85 V

VIL = 1.35 V

VOL = 0.1 V

CMOS.


Noise Margin

Noise Margin

If noise in the circuit is high enough it can push a logic 0 upor drop a logic 1 down into the indeterminate or “illegal”regionNoise margin is maximum amount of noise that the circuitcan withstand.

Low

HighHigh

Low

Notallowed

Undefined

5V

0V

5V

0V

V = 2.8VOH

V = 0.4VOL

IH

V = 0.8VIL

VOH

OL

V = 2.4VIH

ILV

V

V

High levelnoise margin

Low-levelnoise margin


Noise Margin

Noise Margin

Noise Margin for logic high is:

VNH = VOH −VIH

Noise Margin for logic low is:

VNL = VIL−VOL


Propagation Delay

Propagation Delay

Propagation delay is the delay from a change in input to achange on the output.

tPHL – delay from an input is given to the time theoutput changes from high to low.

tPLH – delay from an input is given to the time theoutput changes from low to high.

50%

50%

Input

Output

tPLH

tPHL


Fanout & Fanin

Fanout for TTL

The fanout is the number of standard loads that anoutput can drive.Exceeding the fanout may result in incorrect circuitoperation and may destroy the devices


Fanout & Fanin

Fanout for CMOS

Fanout is much higher for CMOS devices than for TTLdevices.IIL and IIH are extremely small for CMOS (< 1µA).Calculating fanout as we did for TTL might yield fanout of4000 for CMOS, compared to 10 for standard TTL.However, increased fanout results in increased delay dueto input capacitance.


Fanout & Fanin

Fan-In

Number of input signals to a gate.Not an electrical propertyFunction of the manufacturing process

NAND gate with a fan in of 8.


Power

Power Dissipation

Static/quiescentDue to passive componentsNo input signal

DynamicDue to charging and discharging capacitances throughresistancesVaries with operating frequency

Example:74LS-TTL power dissipation : 5 mW/gate, regardless offrequency74HC-CMOS power dissipation : 0.0025 µW/gate static,but increase proportionally to frequencyAt 1 MHz, both consume about the same power


Power

Speed-Power Product

Speed (propagation delay) and power consumption are thetwo most important performance parameters of a digital IC.Speed-power product (SPP) – a simple means formeasuring and comparing the overall performance of an ICfamily (the smaller, the better).Example, an IC has:

an average propagation delay of 10 nsan average power dissipation of 5 mWthe speed-power product = (10 ns) x (5 mW) = 50picoJoules (pJ)


Power

SPP of Various Logic Families

CMOS TTL74HC 4000 74 74S 74LS 74AS 74ALS 74F

Propagation delay (ns) 8 50 10 3 10 1.5 4 3Power consumption (mW/gate)Static 0.000025 0.001 10 20 2 8 1 4@ 100 kHz 0.17 0.1 10 20 2 8 1 4Max clock freq. (MHz) 40 12 35 125 40 200 70 100Speed-Power Product@ 100 kHz(pJ) 1.4 11 90 60 18 13.6 4.8 12Fan-Out:LS loads 10 4 40 20 50 20 50 50Same series >100 >100 10 20 20 40 20 33Low-level input current (mA) 0.001 0.001 -1.6 -2.0 -0.4 -0.5 -0.2 -0.6


Wired-AND

Open collector outputs connected together to a commonpull-up resistorAny collector can pull the signal line lowLogically an AND gate

A

B

C

ABC

VCC


Tri-State Logic

Usually used to bus multiple signals on the same wireOnly one gate output is enabled, all others must bedisabledDisabled gates look like high-impedance (Hi-Z) to bus andtherefore do not interfere with other gates putting signalson the bus

Device 1(e.g., CPU)

Device 2(e.g., Memory)

Device 3(e.g., I/O)

Communications bus

32


Transistor Types

TTL vs CMOS

TTL→ Transistor-Transistor LogicUses BJT (bipolar junction transistor)

MOS→ Metal Oxide SemiconductorUses FET (field effect transistor)

MOS has three subfamiliesPMOS (P-channel FET)NMOS (N-channel FET)CMOS (Complimentary, uses both types, most common)


TTL Operation & Evolution

TTL Circuit OperationA standard TTL gate

A B ICQ1 Q1 Q2 Q3 Q4 Y0 0 + ON OFF OFF ON 10 1 + ON OFF OFF ON 11 0 + ON OFF OFF ON 11 1 - OFF ON ON OFF 0


TTL Operation & Evolution

TTL Evolution


CMOS Circuit OperationCMOS Inverter

Input Q1 Q2 Output0 ON OFF 11 OFF ON 0


CMOS Evolution


CMOS Logic Trends

Reduction in supply voltages12V→ 5V→ 3.3V→ 2.5V→ 1.8V→ 1.5V · · ·

Reduction in power dissipation results inLower costHigher integrationImproved reliability

Approximately double the number of transistors per chipevery 18 months

The famous Moore’s Law – observed by Gordon Moore in1965


Moore’s Law


SKEE1223

https://www.openlearning.com/courses/SKEE1223x

https://www.openlearning.com/courses/SKEE1223x

Chapter 15 Integrated Circuits - FKE · Speed (propagation delay) and power consumption are the two most important performance parameters of a digital IC. Speed-power product (SPP)

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