CHAPTER 1 – ABSTRACT › ~kuzuah › BSc_Thesis.pdf · 1 CHAPTER 1 – ABSTRACT The field of micromachined sensors and actuators, offen reffered to as “MEMS”, has been growing

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CHAPTER 1 – ABSTRACT

The field of micromachined sensors and actuators, offen reffered to as “MEMS”, has

been growing at an exciting place in recent years. Using tools originally developed for the

silicon integrated circuit industry, people are now fabricating miniaturized transducers and

structures from silicon and other materials. In many cases, these new devices offer their

conventional counterparts, including great reduction in siz, new functions that could not

otherwise be realized, the capability to include on-chip signal processing/control circuitry,

reductions in per-unit cost, and the ability to fabricate scaled and multimodal arrays.

In this theses I design a RF switch which can be used in many RF circuits such as

digitally controlled electronic antenna matching circuits, tranmit/receive switches.

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CHAPTER 2 – GENERAL PERSPECTIVE OF DESIGN

2.1. RF SWITCH

RF switch is a kind of relay which is spesifically designed for RF applications. These

RF switches have a broad varietyof where active and passive components can be switched into

or out of RF circuits. Example applications are digitally conroled antenna matching circuits,

transmit/receive switches, phase shifters for phassed array radars, input filters, tuning circuits,

and a number of others

In my design I used a comb drive for the actuator of the switch. Moreover I designed a

automatic control system to control switch. These two systems designed separetly on different

chip, then wire bonded each other. Because the integration of microelectronics with MEMS is a

key component to the success of most MEMS devices. By placing electronics closer to sensors

and actuators, the device performance is improved. Several different approaches have been

taken in the integration of electronics with MEMS. The hybrid approach, in which the

electronics and MEMS are wire bonded into a single package has long been the industry

standard. This is the simplest approach is not batch produced, can suffer from large

capacitances and inductive losses in wires and can result in a large final product. The

embedded or monolithic approach, in which the electronics are fabricated on the same substrate

as the MEMS, provides excellent performance and benefits from batch fabrication. However,

because the electronics and MEMS are fabricated on the same substrate, the processing is

extremely complex and the MEMS and electronics processes must be compatible. The

increased complexity of the process can drive up cost and impact process yield.

Flip chip MEMS has emerged as an excellent alternative to the above methods. This method

involves fabricating the electronics and MEMS as separate parts and then attaching them, face-

toface, with solder bumps. Flip chip provides good device performance with little or no area

penalty and most importantly, it provides complete process independence of the MEMS and

the electronics. This allows the manufacturer to optimize the performance of each component

separately. Flip chip also allows the building of the electronics and MEMS on substrate types

other than silicon.

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2.2. Flip Chip MEMS

Flip chip is a general term that describes a method of attaching an IC (or MEMS chip) to

substrate. The substrate can be another chip, a PC board, a special carrier or a multichip

module. More specifically, flip chip is a technology in which one chip is placed face down (flip

chipped) on to the substrate and attached through solder bumps that provide both mechanical

and electrical connection. Flip chip provides a much higher interconnection density than

traditional methods (i.e. wire bonding) because the interconnections are distributed across the

entire chip surface rather than being restricted to the periphery of the chip. When applied to

MEMS, flip chip provides an alternative to the traditional integration methods of either hybrid

packaging or embedded (monolithic) electronics integration. Since flip chip allows the IC to be

placed directly over a MEMS device, there is little or no area penalty and the electronics are

electrically much closer to the sensor or actuator thus improving performance. In cases where

the MEMS device must be exposed to the environment (e.g. an optical device), the electronics

can be attached to one side of the MEMS device. Once the two chips are joined by flip chip,

the attached pair can be mounted in a traditional package. An outer pad ring on the bottom

(larger) chip provides wire bonding pads for connection to the package.

2.3. Flip Chip Process

The flip chip process developed by MCNC uses electroplated solder to create bumps for

attachment. The electroplating method provides a cost effective method of fabricating small

bumps with small pitches. Figure 2.1 Figure 2.5 illustrate the bump fabrication process wich is

performed on the Ecosys IC wafers for use in the SmartMUMPs program.

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Figure 2.1 The bumping process begins with a finished, passivated IC wafer. The solder bumps

are fabricated on the exposed I/O's.

The process begins by sputtering a layer of metal known as the under bump metallurgy, or

UBM on the finished ECOSYS wafer (Figure 2.1). The UBM is a solder wettable metal that

acts as both a plating base and a good contact for the solder bump after reflow. A second metal

layer is evaporated and patterned by liftoff to form the solder dam that confines the bump

upon reflow (Figure 2.2). The holes in the solder dam are centered on the underlying I/O's. A

thick layer of photoresist is then patterned to form the solder plating template and the solder is

electroplated (Figure 2.3). The template is then removed and the solder is reflowed to produce

a solder bump confined at the base by the solder dam (Figure 2.4). After the reflow, the

solder dam and UBM are removed (Figure 2.5). At this point, the wafer can be diced and the

individual chips are ready for die attach. Figure 2.6 is a scanning electron micrograph of the

bumps after reflow.

Figure 2.2 The under bump metallurgy (UBM) is sputtered. This is followed by the thermal

evaporation and liftoff patterning of the solder dam metallurgy. The solder dam is a non solder

wettable metal that confines the solder during

reflow to create the solder bump.

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Figure 2.3 A thick layer of photoresist is patterned to create a plating template. The solder is

then electroplated to the desired thickness.

Figure 2.4 The plating template is removed and the wafers are heated to reflow the solder.

Figure 2.5 The solder dam and UBM is etched to expose the original passivation layer. The

wafer can now be diced and the individual chips are ready for flip chip attach to the MUMPs

chip.

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Figure 2.6 Scanning electron micrograph of solder bumps after reflow. At this point the chip is

ready for die attach.

The die attach process is performed on the chip level. Because solder is attacked in the

HF used for releasing the MEMS devices, the release must be performed before die attach. The

ECOSYS chip is pretreated in a plasma process that eliminates the need for flux to attach the

solder joints,. This "fluxless solder" technique, known as PADS (Plasma Assisted Dry

Soldering), has the added benefit of not requiring a post solder clean which would expose the

MEMS devices to wet chemicals causing stiction problems. After plasma treatment, the chips

are aligned (Figure 2.7), contacted and the solder is reflowed. Figure 2.8 is a picture of a joined

pair following reflow. After solder reflow, the joined pair can be placed in a

traditional package and wire bonded (Figure 2.9).

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Figure 2.7 The MEMS chip is aligned so that the appropriate pads are in contact and the solder

is heated to reflowtemperature providing both mechanical and electrical contact. In this case

the MEMS chip is the smaller of the two and it is attached on top of the IC. For SmartMUMPs,

the MEMS chip is larger and the IC is mounted on top of the MEMS chip and the wirebond

pads are on the MEMS die.

Figure 2.8 Photograph of a joined pair after solder reflow.

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Figure 2.9 The joined MEMS/IC pair is die and wire bonded to a standard package.

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CHAPTER 3 – MEMS PROCESS

In this design open three-layer polisilicon surface micromachining process is used.

3.1. Three-Layer Polysilicon Surface Micromachining Process

The Multi-User MEMS Processes, or MUMPs ® , is a commercial program that

provides cost-effective, proof-of-concept MEMS fabrication to industry, universities, and

government worldwide. MEMSCAP offers three standard processes as part of the MUMPs ®

program: PolyMUMPs, a three-layer polysilicon surface micromachining process:

MetalMUMPs, an electroplated nickel process; andSOIMUMPs, a silicon-on-insulator

micromachining process.

The following is a general process description and user guide for PolyMUMPs, which

is designed for general-purpose micromachining of MEMS.

FIGURE 3.1 Cross sectional view showing all 7 layers of the PolyMUMPs process (not to

scale).

Figure 3.1 is a cross section of the three-layer polysilicon surface micromachining

PolyMUMPs process. This process has the general features of a standard surface

micromachining process: (1) polysilicon is used as the structural material, (2) deposited oxide

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(PSG) is used as the sacrificial layer, and silicon nitride is used as electrical isolation between

the polysilicon and the substrate. The process is different from most customized surface

micromachining processes in that it is designed to be as general as possible, and to be capable

of supporting many different designs on a single silicon wafer. Since the process was not

optimized with the purpose of fabricating any one specific device, the thicknesses of the

structural and sacrificial layers were chosen to suit most users, and the layout design rules were

chosen conservatively to guarantee the highest yield possible.

3.2. Process Overview

The PolyMUMPs process is a three-layer polysilicon surface micromachining process

derived from work performed at the Berkeley Sensors and Actuators Center (BSAC) at the

University of California in the late 80's and early 90's. Several modifications and enhancements

have been made to increase the flexibility and versatility of the process for the multi-user

environment. The process flow described below is designed to introduce inexperienced users to

polysilicon micromachining. The text is supplemented by detailed drawings that show the

process flow in the context of building a typical micromotor.

The process begins with 100 mm n-type (100) silicon wafers of 1-2 W-cm resistivity.

The surface of the wafers are first heavily doped with phosphorus in a standard diffusion

furnace using POCl 3 as the dopant source. This helps to reduce or prevent charge feedthrough

to the substrate from electrostatic devices on the surface. Next, a 600 nm low-stress LPCVD

(low pressure chemical vapor deposition) silicon nitride layer is deposited on the wafers as an

electrical isolation layer. This is followed directly by the deposition of a 500 nmLPCVD

polysilicon film--Poly 0. Poly 0 is then patterned by photolithography, a process that includes

the coating of the wafers with photoresist (Figure 3.2), exposure of the photoresist with the

appropriate mask and developing the exposed photoresist to create the desired etch mask for

subsequent pattern transfer into the underlying layer (Figure 3.3). After patterning the

photoresist, the Poly 0 layer is then etched in an RIE (Reactive Ion Etch) system (Figure 3.4).

A 2.0 µm phosphosilicate glass (PSG) sacrificial layer is then deposited by LPCVD (Figure

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3.5) and annealed @1050°C for 1 hour in argon. This layer of PSG, known as First Oxide, is

removed at the end of the process to free the first mechanical layer of polysilicon. The

sacrificial layer is lithographically patterned with the DIMPLES mask and the dimples are

transferred into the sacrificial PSG layer by RIE, as shown in Figure 3.6. The nominal depth of

the dimples is 750 nm. The wafers are then patterned with the third mask layer, ANCHOR1,

and reactive ion etched (Figure 3.7). This step provides anchor holes that will be filled by the

Poly 1 layer. After etching ANCHOR1, the first structural layer of polysilicon (Poly 1) is

deposited at a thickness of 2.0 µm. A thin (200 nm) layer of PSG is deposited over the

polysilicon and the wafer is annealed at 1050°C for 1 hour (Figure 3.8). The anneal dopes the

polysilicon with phosphorus from the PSG layers both above and below it. The anneal also

serves to significantly reduce the net stress in the Poly 1 layer. The polysilicon (and its PSG

masking layer) is lithographically patterned using a mask designed to form the first structural

layer POLY1. The PSG layer is etched to produce a hard mask for the subsequent polysilicon

etch. The hard mask is more resistant to the polysilicon etch chemistry than the photoresist and

ensures better transfer of the pattern into the polysilicon. After etching the polysilicon (Figure

3.9), the photoresist is stripped and the remaining oxide hard mask is removed by RIE.

After Poly 1 is etched, a second PSG layer (Second Oxide) is deposited and

annealed(Figure 3.10). The Second Oxide is patterned using two different etch masks with

different objectives. The POLY1_POLY2_VIA level provides for etch holes in the Second

Oxide down to the Poly 1 layer. This provide a mechanical and electrical connection between

the Poly 1 and Poly 2 layers. The POLY1_POLY2_VIA layer is lithographically patterned and

etched by RIE (Figure 3.11). The ANCHOR2 level is provided to etch both the First and

Second Oxide layers in one step, thereby eliminating any misalignment between separately

etched holes. More importantly, the ANCHOR2 etch eliminates the need to make a cut in First

Oxide unrelated to anchoring a Poly 1 structure, which needlessly exposes the substrate to

subsequent processing that can damage either Poly 0 or Nitride. The ANCHOR2 layer is

lithographically patterned and etched by RIE in the same way as POLY1_POLY2_VIA.

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Figure 3.12 shows the wafer cross section after both POLY1_POLY2_VIA and

ANCHOR2 levels havebeen completed. The second structural layer, Poly 2, is then deposited

(1.5 µm thick) followed by the deposition of 200 nm PSG. As with Poly 1, the thin PSG layer

acts as both an etch mask and dopant source for Poly 2 (Figure 3.1.13). The wafer is annealed

for one hour at 1050 C to dope the polysilicon and reduce the residual film stress. The Poly 2

layer is lithographically patterned with the seventh mask (POLY2) and the PSG and

polysilicon layers are etched by RIE using the same processing conditions as for Poly 1. The

photoresist then is stripped and the masking oxide is removed (Figure 3.1.14). The final

deposited layer in the PolyMUMPs process is a 0.5 µm metal layer that provides for probing,

bonding, electrical routing and highly reflective mirror surfaces. The wafer is patterned

lithographically with the eighth mask (METAL) and the metal is deposited and patterned using

lift-off. The final, unreleased structure is shown in Figure 3.15. The wafers are diced, sorted

and shipped to the PolyMUMPs user for sacrificial release and test. Figure 3.16 shows the

device after sacrificial oxide release. The release is performed by immersing the chip in a bath

of 49% HF (room temperature) for 1.5-2 minutes. This is followed by several minutes in DI

water and then alcohol to reduce stiction followed by at least 10 minutes in an oven at 110° C.

Generally the participants receive their dice and perform the sacrificial oxide release in their

own facility. For those participants who request it, release of their dice at MEMSCAP's facility

can be arranged for an additional fee. The following provides a graphical representation of the

process steps.

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FIGURE 3.2. The surface of the starting n-type (100) wafers are heavily doped with

phosphorus in a standard diffusion furnace using POCl 3 as the dopant source. A 600 nm

blanket layer of low stress silicon nitride (Nitride) is deposited followed by a blanket layer of

500 nm polysilicon (Poly 0). The wafers are then coated with UV-sensitive photoresist.

FIGURE 3.3. The photoresist is lithographically patterned by exposing it to UV light

through the first level mask (POLY0) and then developing it. The photoresist in exposed areas

is removed leaving behind a patterned photoresist mask for etching.

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FIGURE 3.4. Reactive ion etching (RIE) is used to remove the unwanted polysilicon.

After the etch, the photoresist is chemically stripped in a solvent bath. This method of

patterning the wafers with photoresist, etching and stripping the remaining photoresist is used

repeatedly in the PolyMUMPs process.

FIGURE 3.5. A 2.0 µm layer of PSG is deposited on the wafers by low pressure

chemical vapor deposition (LPCVD). This is the first sacrificial layer.

FIGURE 3.6. The wafers are coated with photoresist and the second level (DIMPLE) is

lithographically patterned. The dimples, 750 nm deep, are reactive ion etched into the first

oxide layer. After the etch, the photoresist is stripped.

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FIGURE 3.7. The wafers are re-coated with photoresist and the third level

(ANCHOR1) is lithographically patterned. The unwanted oxide is removed in an RIE etch and

the photoresist is stripped.

FIGURE 3.8. A blanket 2.0 µm layer of un-doped polysilicon is deposited by LPCVD

followed by the deposition of 200 nm PSG and a 1050°C/1 hour anneal. The anneal serves to

both dope the polysilicon and reduce its residual stress.

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FIGURE 3.9. The wafer is coated with photoresist and the fourth level (POLY1) is

lithographically patterned. The PSG is first etched to create a hard mask and then Poly 1 is

etched by RIE. After the etch is completed, the photoresist and PSG hard mask are removed.

FIGURE 3.10. The Second Oxide layer, 0.75 µm of PSG, is deposited on the wafer.

This layer is patterned twice to allow contact to both Poly 1 and substrate layers.

FIGURE 3.11. The wafer is coated with photoresist and the fifth level

(POLY1_POLY2_VIA) is lithographically patterned. The unwanted Second Oxide is RIE

etched, stopping on Poly 1, and the photoresist is stripped.

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FIGURE 3.12. The wafer is re-coated with photoresist and the sixth level (ANCHOR2)

is lithographically patterned. The Second and First Oxides are RIE etched, stopping on either

Nitride or Poly 0, and the photoresist is stripped. The ANCHOR2 level provides openings for

Poly 2 to contact with Nitride or Poly 0.

FIGURE 3.13. A 1.5 µm un-doped polysilicon layer is deposited followed by a 200 nm

PSG hardmask layer. The wafers are annealed at 1050°C for one hour to dope the polysilicon

and reduce residual stress.

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FIGURE 3.14. The wafer is coated with photoresist and the seventh level (POLY2) is

lithographically patterned. The PSG hard mask and Poly 2 layers are RIE etched and the

photoresist and hard mask are removed. All mechanical structures have now been fabricated.

The remaining steps are to deposit the metal layer and remove the sacrificial oxides.

FIGURE 3.15. The wafer is coated with photoresist and the eighth level (METAL) is

lithographically patterned. The metal (gold with a thin adhesion layer) is deposited by lift-off

patterning which does not require etching. The side wall of the photoresist is sloped at a

reentrant angle, which allows the metal to be deposited on the surfaces of the wafer and the

photoresist, but provides breaks in the continuity of the metal over the reentrant photoresist

step. The photoresist and unwanted metal (atop the photoresist) are then removed in a solvent

bath. The process is now complete and the wafers can be coated with a protective layer of

photoresist and diced. The chips are sorted and shipped.

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FIGURE 3.16. The structures are released by immersing the chips in a 49% HF

solution. The Poly 1 ``rotor'' can be seen around the fixed Poly 2 hub. The stacks of Poly 1,

Poly 2 and Metal on the sides represent the stators used to drive the motor electrostatically.

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CHAPTER 4 – MECHANICAL SYSTEM

Comb drive is used in mechanical system as actuator of the switch. Two main formula

of comb drive is vey important. First of stifness of beam which is formulated as;

Which become for rectangular prism beam as;

For E respresents Young Module, L represent Length of beam, W represent Width of

beam, t represent thickness of beam, and I represent innertia.

The second is Electrosatic force, which is formulated as;

For ε represents permittivity, V represents voltage between stator comb and actuated

comb, t is with of the comb and g is the distance between the actuated and stator comb. For n

comb formula becomes;

I designed the space between the actuated comb and stator comb 6um. Then From the equation

Kx=F

I found for 31 comb I should apply at least nearly 15V.

I used LASI software package to draw layout of mechanical part and ANSYS software package

to make solid model and prepare simulation.

3

3LEI

K =

3

3

4LEWt

K =

gt

VF e2

21 ε=

gt

VnF e2

21 ε=

21

MECHANICAL PROPERTIES OF POLYSILICON USED IN MUMPs PROCESS

Property Value Conditions ReferenceFrictioncoefficient

0.04 LPCVD n+type film ,at the begining & from anabrupt increase in friction during scratching,width of scratch(1.5 um) at about 17-20 mNnormal load(measured from SEM images),criticalload=9 mN.

J.Mater.Res,Vol.12,No.1,Jan1997, p.59

Frictioncoefficient

0.42 LPCVD n+type film ,at the end of scratching &from an abrupt increase in friction duringscratching, width of scratch(1.5 um) at about 17-20 mN normal load(measured from SEMimages),critical load=9 mN.


Frictioncoefficient(final)

0.42 LPCVD film,n+type( phosphorous doped),Valuesobtained during scratching,critical load=9mN,width of scratch(by SEM observations)=1.5um,slight ploughing at the tip into the film rightat the beginning.

J.Mater.Res.,Vol.12,No.1,Jan1997, p.59

Frictioncoefficient(initial)

0.04 LPCVD film,n+type( phosphorous doped),Valuesobtained during scratching,critical load=9mN,width of scratch(by SEM observations)=1.5um,slight ploughing at the tip into the film rightat the beginning.

J.Mater.Res.,Vol.12,No.1,Jan1997, p.59

Frictioncoefficient,final

0.05 LPCVD n+type film,sliding against a sphericaldiamond tip (radius=20um)at 10 mN normal load,7.0 mmstroke length,0.1 Hz frequency,and 1.0mm/sec average linear speed for a slidingdistance of 4m under an ambient temperature ofabout 22+-1 C and a relative humidity of about45+-5% RH.


Frictioncoefficient,final

0.16 LPCVD n+type film, sliding against a single-crystal sapphire ball(diameter=3mm) at 10 mNnormal load,7.0 mmstroke length,0.1 Hzfrequency,and 1.0 mm/sec average linear speedfor a sliding distance of 4m under an ambienttemperature of about 22+-1 C and a relativehumidity of about 45+-5% RH.


Frictioncoefficient,initial

0.05 LPCVD n+type film,sliding against a sphericaldiamond tip (tip radius, 20 um) at 10 mN normalload, 7.0 mm stroke length, 0.1 Hz frequency, and1.0 mm/sec average linear speed for a slidingdistance of 4 m under an ambient tempoerature of22+-1 deg C and a relative humidity of about45+-5% RH.


Frictioncoefficient,initial

0.16 LPCVD film,n+type,sliding against a single-crystal sapphire ball(diameter,3mm) at 10 mNnormal load,7.0 mmstroke length,0.1 Hzfrequency,and 1.0 mm/sec average linear speedfor a sliding distance of 4m under an ambienttemperature of about 22+-1 C and a relativehumidity of about 45+-5% RH.


Frictioncoefficient,

0.04 Scan size=500X500 nm2,using nanotribologystudies(AFM/FFM).

IEEE Micro Electro MechanicalSystems Workshop,SanDiego,

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micro California,Feb 1996, p.97Frictioncoefficient,micro

0.05 Lapped, scan size=500X500 nm2,usingnanotribology studies(AFM/FFM).

IEEE Micro Electro MechanicalSystems Workshop,SanDiego,California,Feb 1996, p.97

Hardness 11.5GPa

LPCVD,n+type(phosphorous doped),obtained bynanodentation at a load of 0.2 mN and indentationdepth of 25 nm at peak load.

J.mater.Res,Vol.12,No.1,Jan1997, p.59

Hardness 10.5GPa

LPCVD,n+type(phosphorous doped),valuesobtained by nanodentation at a load of 15 mN andindentation depth of 289 nm at peak load.


Hardness,nanoindentation(at100uN)

12.5GPa

Lapped, scan size=500X500 nm2,usingnanotribology studies(AFM/FFM).


Internalstress

-0.18GPa

LPCVD film,calculated by using Load-Deflectionof composite rectangularmembranes,thickness=0.2 um.

Sensors and Actuators,20(1989),p.138

Roughness(Rms)

1.45 nm LPCVD film,n+type(phosphorous doped), valuemeasured using AFM at a scan size of 1 um x 1um.

J. Mater. Res., Vol. 12 No. 1, Jan1997, p.60

Roughness(Rms)

1.07 Scan size=500X500 nm2,using nanotribologystudies(AFM/FFM).


Roughness(Rms)

0.16 Lapped, scan size=500X500 nm2,usingnanotribology studies(AFM/FFM).


Scratchdepth,micro(at 40uN)

18 nm Scan size=500X500 nm2,using nanotribologystudies(AFM/FFM).


Scratchdepth,micro(at 40uN)

18 nm Lapped, scan size=500X500 nm2,usingnanotribology studies(AFM/FFM).


ShearModulus

69 GPa Equivalent to rigidity modulus,MCNC MUMPSProcess,URL:http://titan.me.jhu.edu/~sharpe/ptt/ptt.html,Value deducted from the Young's modulus (169GPa) and poisson ratio (0.22) by G = E{2(1 + v)}

W.Sharpe,B.Yuan,R.Vaidyanathan,R.Edwards, Proceedings of the10th MEMSWorkshop,Nagoya,Japan,1997,p.424-429

Strain,Compressive

0.006 ..0.007

LPCVD,thickness=230nm,oxide type=3.5umPSG,unannealed, value measured locally byobserving the relaxation of a silicon overhangover an oxide underlayer.

J.Appl.Phys,Vol.54,No.8,August1983, p.4675

Strain,Compressive

0.0035..0.0045

LPCVD,thickness=230nm,oxide type=3.5umPSG, value measured locally by observing therelaxation of a silicon overhang over an oxideunderlayer,annealed in N2 for 20 min at 1100C.


Strain,Compressive

0.0035..0.0045

LPCVD,thickness=800 nm,oxide type=1.7 umPSG,unannealed, value measured locally byobserving the relaxation of a silicon overhangover an oxide underlayer.


Strain,Compressive

0.004 ..0.005

LPCVD,thickness=1.45um ,oxide type=1.1 umthermally grown, unannealed,value measuredlocally by observing the relaxation of a silicon


23

overhang over an oxide underlayer.Stress,Compressive

1.4 ..1.6 GPa

LPCVD,thickness=230nm,oxide type=3.5umPSG,unannealed, value measured locally byobserving the relaxation of a silicon overhangover an oxide underlayer.


Stress,Compressive

0.8 .. 1GPa

LPCVD,thickness=230nm,oxide type=3.5umPSG, value measured locally by observing therelaxation of a silicon overhang over an oxideunderlayer,annealed in N2 for 20 min at 1100C.


Stress,Compressive

0.8 .. 1GPa

LPCVD,thickness=800 nm,oxide type=1.7 umPSG,unannealed, value measured locally byobserving the relaxation of a silicon overhangover an oxide underlayer.


Stress,Compressive

0.9 ..1.1 GPa

LPCVD,thickness=1.45um ,oxide type=1.1 umthermally grown, unannealed,value measuredlocally by observing the relaxation of a siliconoverhang over an oxide underlayer.


Stress,residual

290MPa

Undoped,thickness=2.5um ,using wafer curvatureexperiments, as film is deposited.


Stress,residual

270MPa

Undoped,thickness=5 um ,using wafer curvatureexperiments, as film is deposited.


Stress,residual

350MPa

Undoped,thickness=2.5 um ,using wafercurvature experiments, after undergoing a wetoxidation at 1000C for 107min with the oxidelayer subsiquently stripped.


Stress,residual

190MPa

Undoped,thickness=5 um ,using wafer curvatureexperiments, after undergoing a wet oxidation at1000C for 107min with the oxide layersubsiquently stripped.

IEEE Micro Electro MechanicalSystems Workshop,SanDiego,California, Feb 1996, p.345

Tensilestress

-5.2 ..18.8MPa

Thick film,value is for thickness higher than10um,CVD film, deposited at RP(reduced press)or atm press,temperature of deposition from 870to 1000C,grown on top of a standard LPCVDpolysilicon on top of a 1um sacrificial SiO2layer,assuming biaxial stress, value obtained fromrelation between Raman shift and stress.

Sensors & Actuators,A51(1995),p.11

Weardepth,micro(at 40uN)

25 nm Lapped, scan size=500X500 nm2,usingnanotribology studies(AFM/FFM).


Young'sModulus

201GPa

LPCVD,n+type(phosphorous doped),obtained bynanodentation at a load of 0.2 mN and indentationdepth of 25 nm at peak load.


Young'sModulus

176GPa

LPCVD,n+type(phosphorous doped),valuesobtained by nanodentation at a load of 15 mN andindentation depth of 289 nm at peak load.


Young'sModulus

120 ..180GPa

In-situ B-doped ,for thickness upto 10um,obtained by lateral resonant structure method.


Young'sModulus

152 ..171

Obtained from laser induced ultrasonic surfacewave method for a thickness of 0.4-0.5

Thin solid films 290-291(1996),p.309

24

GPa um,choosing an intermediate density.Young'sModulus

160GPa

LPCVD film,calculated by using Load-Deflectionof composite rectangularmembranes,thickness=0.2 um.

Sensors and Actuators,20(1989),p.138

25

Figure 4.1 Layout of mechanical chip

26

Figure 4.2 3D model maked by ANSYS®

27

4.3. Finite Element Model of Comb Drive

28

CHAPTER 5 – ELECTRONIC SYSTEM

The mathematical model of the combdrive(Figure 5.1) is nonlinear. I tried to control it with alinear PID controller but I couldn’t achieve a good result. (Figure 5.2)

Figure 5.1 Block diagram of system.

Figure 5.2 Result of Matlab simulation

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Figure 5.3 Schematic of Op-Amp

30

Figure 5.4 Layout of Op-Amp

31

Figure 5.5 Schematic of PID Controller

32

CHAPTER 6 – CONCLUSION

As shown in the study nonlinearity of the comb drive makes it vey hard to control via

inexpensive PID controller in RF switch application. It may be more usefull to use it without a

controller, only in on/off state.

33

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34

[8] “MCNC PolyMUMPS Technotes rev(9)”, MEMSCAP

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CHAPTER 1 – ABSTRACT › ~kuzuah › BSc_Thesis.pdf · 1 CHAPTER 1 – ABSTRACT The field of micromachined sensors and actuators, offen reffered to as “MEMS”, has been growing

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