8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 E E D D C C B B A A DESCRIPTION REV DATE PAGES PAGE DESCRIPTION 2 NOTES: Title, Notes, Block Diagram, Rev. History 1 3 4 7 8 Arria V ST Bank 6, 7G 9 Arria V ST Bank 7 10 11 12 13 14 15 16 PLL and Clocks 17 JTAG 18 19 20 21 22 23 24 25 5 6 10/100/1000 Ethernet PHY (HPS) 1172 Parts, 88 Library Parts, 1330 Nets, 6643 Pins A1 All INITIAL REVISION A RELEASE Blank Page Arria V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework PCI Express Edge Connector Arria V ST Bank 4 Arria V ST Bank 3 Arria V ST Transceiver Banks 2. 100-0320807-C1 110-0320807-C1 120-0320807-C1 130-0320807-C1 140-0320807-C1 150-0320807-C1 160-0320807-C1 170-0320807-C1 180-0320807-C1 210-0320807-C1 220-0320807-C1 320-0320807-C1 On-Board USB Blaster II 26 27 28 29 PAGE DESCRIPTION 30 HPS Power Monitor Flash, EPCQ 5M2210 System Controller User I/O (LEDs, Buttons, Switches, LCD) FMC Port A Connector Dual EtherCAT PHY 31 32 33 Power 1 - DC Input, 12V, 3.3V Arria V ST Clocks Arria V ST Configuration DDR3 x40 - HPS SFP+ Port B DDR3 x32 - FPGA Port B Arria V ST Bank 8 Power 8 - 5V, 1.8V, & HPS 1.1V SFP+ Port A DDR3 x32 - FPGA Port A QSPI Flash, Reset Circuit 34 USB 2.0 OTG, Micro SD Card 35 38 37 36 39 40 41 42 44 45 Power 7 - HPS Power 3.3V Power 10 - Arria V ST Power Power 9 - Linear Regulator Decoupling Power 11 - Arria V ST GND UART Ports A & B Power 6 - HPS Power 1.5V Power 5 - HPS Power 2.5V Power 4 - FPGA Power 2.5V Power 3 - FPGA Power 1.5V Power 2 - FPGA Power 1.1V FPGA Power Monitor 2 FPGA Power Monitor 1 43 FMC Port B Connector Clock Cleaner Changes for Rev B All 02 INITIAL RELEASE TO B All B1 C1 All INITIAL RELEASE TO C Changes: Removed SPI signals from MAX device to LMK device Swapped pin locations for CLK_100M_FPGA and SPI_SDIO to remove critical warnings Added RC circuit for JTAG clocks (JTAG_MUX_TCK, JTAG_HPS_TCK) Added resistor mux for selecting clock and sync from LMK or FPGA for FMCA and FMCB Changes: Fixed connections for FPGA Power Monitor Added FMCB and LMK interface Added pull-ups for Power Monitor devices Changed QSPI device to one with reset pin Added series resistor (0-ohm) between run pin and Power Monitor device Changed LTC2978 to LTC2977 Title Size Document Number Rev Date: Sheet of C1 Arria V SoC FPGA Development Kit Board B 1 45 Thursday, December 12, 2013 150-0320807-C1 (6XX-44209R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of C1 Arria V SoC FPGA Development Kit Board B 1 45 Thursday, December 12, 2013 150-0320807-C1 (6XX-44209R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of C1 Arria V SoC FPGA Development Kit Board B 1 45 Thursday, December 12, 2013 150-0320807-C1 (6XX-44209R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
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8
8
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5
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4
3
3
2
2
1
1
E E
D D
C C
B B
A A
DESCRIPTIONREV DATE PAGES
PAGE DESCRIPTION
2
NOTES:
Title, Notes, Block Diagram, Rev. History1
3
4
7
8
Arria V ST Bank 6, 7G
9
Arria V ST Bank 7
10
11
12
13
14
15
16
PLL and Clocks
17
JTAG
18
19
20
21
22
23
24
25
5
6
10/100/1000 Ethernet PHY (HPS)
1172 Parts, 88 Library Parts, 1330 Nets, 6643 Pins
A1 All INITIAL REVISION A RELEASE
Blank Page
Arria V SoC FPGA Development Kit Board
1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
PCI Express Edge Connector
Arria V ST Bank 4
Arria V ST Bank 3
Arria V ST Transceiver Banks
2.
100-0320807-C1110-0320807-C1120-0320807-C1130-0320807-C1140-0320807-C1150-0320807-C1160-0320807-C1170-0320807-C1180-0320807-C1210-0320807-C1220-0320807-C1320-0320807-C1
On-Board USB Blaster II
26
27
28
29
PAGE DESCRIPTION
30
HPS Power Monitor
Flash, EPCQ
5M2210 System Controller
User I/O (LEDs, Buttons, Switches, LCD)
FMC Port A Connector
Dual EtherCAT PHY
31
32
33
Power 1 - DC Input, 12V, 3.3V
Arria V ST Clocks
Arria V ST Configuration
DDR3 x40 - HPS
SFP+ Port B
DDR3 x32 - FPGA Port B
Arria V ST Bank 8
Power 8 - 5V, 1.8V, & HPS 1.1V
SFP+ Port A
DDR3 x32 - FPGA Port A
QSPI Flash, Reset Circuit
34
USB 2.0 OTG, Micro SD Card
35
38
37
36
39
40
41
42
44
45
Power 7 - HPS Power 3.3V
Power 10 - Arria V ST Power
Power 9 - Linear Regulator
Decoupling
Power 11 - Arria V ST GND
UART Ports A & B
Power 6 - HPS Power 1.5V
Power 5 - HPS Power 2.5V
Power 4 - FPGA Power 2.5V
Power 3 - FPGA Power 1.5V
Power 2 - FPGA Power 1.1V
FPGA Power Monitor 2
FPGA Power Monitor 1
43
FMC Port B Connector
Clock Cleaner
Changes for Rev BAll02INITIAL RELEASE TO BAllB1
C1 All INITIAL RELEASE TO CChanges:Removed SPI signals from MAX device to LMK deviceSwapped pin locations for CLK_100M_FPGA and SPI_SDIO to remove critical warningsAdded RC circuit for JTAG clocks (JTAG_MUX_TCK, JTAG_HPS_TCK)Added resistor mux for selecting clock and sync from LMK or FPGA for FMCA and FMCB
Changes:Fixed connections for FPGA Power MonitorAdded FMCB and LMK interfaceAdded pull-ups for Power Monitor devices
Changed QSPI device to one with reset pinAdded series resistor (0-ohm) between run pin and Power Monitor device
Changed LTC2978 to LTC2977
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
1 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
1 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
1 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
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3
3
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2
1
1
E E
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
2 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
2 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
2 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PCI Express Connector
PCIE_TX_C_P0PCIE_TX_C_N0
PCIE_TX_C_N1PCIE_TX_C_P1
PCIE_TX_C_N2PCIE_TX_C_P2
PCIE_TX_C_N3PCIE_TX_C_P3
PCIE_SMBCLKPCIE_SMBDAT
3.3V
12V3.3V
3.3V_EXP 12V_EXP12V_EXP12V_EXP
3.3V_EXP
3.3V_EXP
12V_EXP 3.3V_EXP
PCIE_PERSTn 10,13
PCIE_TX_P09PCIE_TX_N09
PCIE_TX_P19PCIE_TX_N19
PCIE_TX_N29
PCIE_TX_P29
PCIE_TX_P39PCIE_TX_N39
PCIE_PRSNT2_X110
PCIE_PRSNT2_X410
PCIE_REFCLK_SYN_N 11
PCIE_REFCLK_SYN_P 11
PCIE_WAKEn13
PCIE_SMBCLK 4PCIE_SMBDAT 4
PCIE_RX_N0 9
PCIE_RX_P09
PCIE_RX_N1 9
PCIE_RX_P19
PCIE_RX_P29
PCIE_RX_N2 9
PCIE_RX_N3 9
PCIE_RX_P39
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
3 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
3 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
3 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C265
220uF16V
C245
220uF16V
C83822uF25V
R310 4.70K, 1%
C84522uF25V
C241 0.1uF
C263 0.1uF
C239 0.1uF
R324 4.7K
C228 0.1uF
KEY
X4
X1
J42
PCIE-064-02-F-D-TH
+12VB1
+12VB2
+12VB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2_N_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2_N_X4B31
GNDB32
PRSNT1_NA1
+12VA2
+12VA3
GNDA4
JTAG_TCKA5
JTAG_TDIA6
JTAG_TDOA7
JTAG_TMSA8
+3_3VA9
+3_3VA10
PERST_NA11
GNDA12
REFCLK+A13
REFCLK-A14
GNDA15
PER0PA16
PER0NA17
GNDA18
RSVD2A19
GNDA20
PER1PA21
PER1NA22
GNDA23
GNDA24
PER2PA25
PER2NA26
GNDA27
GNDA28
PER3PA29
PER3NA30
GNDA31
RSVD4A32
C264
47uF20V
C230 0.1uF
C276
47uF20V
C84622uF25V
C84422uF25V
R675
0_Ohms
C221 0.1uF
R303 4.70K, 1%
C283
47uF20V
C222 0.1uF
R680
0_Ohms
C262 0.1uF
C282
220uF16V
C277
47uF20V
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Bank 3
2.5 Volt
1.5 Volt 1.5 Volt
1.5 Volt
1.5V Signals DDR3 PORT AETHERNET FPGA
DDR3A_RZQ
DDR3A_A0DDR3A_A1DDR3A_A2DDR3A_A3DDR3A_A4DDR3A_A5DDR3A_A6DDR3A_A7DDR3A_A8DDR3A_A9DDR3A_A10DDR3A_A11DDR3A_A12DDR3A_A13DDR3A_A14
DDR3A_BA0DDR3A_BA1DDR3A_BA2
DDR3A_CLK_NDDR3A_CLK_PDDR3A_CKE
DDR3A_CSn
DDR3A_ODT
DDR3A_RASnDDR3A_CASnDDR3A_WEn
DDR3A_RESETn
DDR3A_DM0DDR3A_DQS_P0DDR3A_DQS_N0
DDR3A_DQ0DDR3A_DQ1DDR3A_DQ2DDR3A_DQ3DDR3A_DQ4DDR3A_DQ5DDR3A_DQ6DDR3A_DQ7
DDR3A_DQ8
DDR3A_DQS_P1DDR3A_DQS_N1
DDR3A_DQ9DDR3A_DQ10DDR3A_DQ11DDR3A_DQ12DDR3A_DQ13DDR3A_DQ14DDR3A_DQ15
DDR3A_DM2DDR3A_DQS_P2DDR3A_DQS_N2
DDR3A_DQ16DDR3A_DQ17DDR3A_DQ18DDR3A_DQ19DDR3A_DQ20DDR3A_DQ21DDR3A_DQ22DDR3A_DQ23
DDR3A_DM3DDR3A_DQS_P3DDR3A_DQS_N3
DDR3A_DQ24DDR3A_DQ25DDR3A_DQ26DDR3A_DQ27DDR3A_DQ28DDR3A_DQ29DDR3A_DQ30DDR3A_DQ31
DDR3A_DM1
USB_B2_DATA[7:0]
USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESETnUSB_OEnUSB_RDnUSB_WRn
USER_DIPSW_FPGA1USER_DIPSW_FPGA0
USER_DIPSW_FPGA2
USER_DIPSW_FPGA3USER_PB_FPGA0USER_PB_FPGA1USER_PB_FPGA2USER_PB_FPGA3USER_LED_FPGA0USER_LED_FPGA1USER_LED_FPGA2USER_LED_FPGA3
USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESETnUSB_OEnUSB_RDnUSB_WRn
USB_B2_DATA0USB_B2_DATA1USB_B2_DATA2
USB_B2_DATA3
USB_B2_DATA4USB_B2_DATA5USB_B2_DATA6USB_B2_DATA7
ENET1_RX_D2ENET1_RX_D3
ENET1_RX_D0ENET1_RX_D1
ENET1_TX_D0ENET1_TX_D1ENET1_TX_D2ENET1_TX_D3
ENET2_RX_D2
ENET2_RX_D0
ENET2_RX_D3
ENET2_RX_D1
ENET2_TX_D0
ENET2_TX_D2ENET2_TX_D1
ENET2_TX_D3
USER_DIPSW_FPGA[3:0]28
USER_PB_FPGA[3:0]28
USER_LED_FPGA[3:0]28
DDR3A_CASn16
DDR3A_CSn16
DDR3A_CLK_P16
DDR3A_CLK_N16
DDR3A_ODT16
DDR3A_RASn16
DDR3A_WEn16
DDR3A_A[14:0]16
DDR3A_RESETn16
DDR3A_DQS_P[3:0]16
DDR3A_DQS_N[3:0]16
DDR3A_DM[3:0]16
DDR3A_DQ[31:0]16
DDR3A_BA[2:0]16
USB_B2_DATA[7:0]30
USB_FULL30USB_EMPTY30
USB_SDA30
USB_RESETn30USB_OEn30USB_RDn30USB_WRn30
USB_SCL30
USB_B2_CLK19,30
ENET1_TX_D[3..0]21ENET1_RX_D[3..0]21ENET2_TX_D[3..0]21ENET2_RX_D[3..0]21
ENET1_TX_EN21
ENET1_RX_ERROR21ENET1_RX_DV21ENET1_RX_CLK21
ENET1_TX_CLK_FB21
ENET2_RX_CLK 21
ENET2_TX_EN 21
ENET2_TX_CLK_FB 21
P1TXERR 21
ENET2_RX_ERROR 21
P0TXERR21
ENET2_RX_DV 21
ENET_DUAL_RESETn21,26
ENET_FPGA_MDIO21
ENET_FPGA_MDC21SDI_CLK148_UP9
SDI_CLK148_DN9
PCIE_SMBDAT3 PCIE_SMBCLK 3
DDR3A_CKE16
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
4 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
4 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
4 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Bank 3C
Bank 3D
Arria V SX (SoC) Bank 3
5ASTFD5K3_F1517
U41O
HMC_DQ3_5,DIFFIO_TX_B43_PAD25
HMC_DQ4_0,DIFFIO_RX_B53_PAV24
HMC_DQ3_6,DIFFIO_RX_B40_PAC25
HMC_DQ3_4,DIFFIO_RX_B44_NAG26
HMC_DQ3_1,DIFFIO_RX_B46_NAG25
HMC_DQ3_2,DIFFIO_TX_B45_PAE26
HMC_DQ3_0,DIFFIO_RX_B46_PAH25
HMC_DQ3_3,DIFFIO_RX_B44_PAH26
HMC_DQ3_7,DIFFIO_RX_B40_NAB25
HMC_DQ3_8,DIFFIO_TX_B39_PAH27
HMC_DM4,DIFFIO_TX_B49_PAK25
HMC_DM3,DIFFIO_TX_B41_PAF27
HMC_DM5,DIFFIO_TX_B56_PAL24
HMC_DQS3,HMC_RLD2_QK#3,HMC_QDR2_CQ3/CQ#3,DIFFIO_RX_B42_PAF25
DIFFIO_TX_B58_NAG24
HMC_DQ5_2,DIFFIO_TX_B60_PAP24
HMC_DQ5_7,DIFFIO_RX_B55_NAT24HMC_DQ5_6,DIFFIO_RX_B55_PAU24
HMC_DQS#4,HMC_RLD2_QK4,DIFFIO_RX_B50_NAT26
HMC_DQ5_1,DIFFIO_RX_B61_NAT23
HMC_DQS#3,HMC_RLD2_QK3,DIFFIO_RX_B42_NAE25
HMC_DQ5_3,DIFFIO_RX_B59_PAW24
DIFFIO_TX_B60_NAN24
HMC_DQ5_5,DIFFIO_TX_B58_PAH24
HMC_DQS5,HMC_RLD2_QK#5,HMC_QDR2_CQ5/CQ#5,DIFFIO_RX_B57_PAF24
HMC_DQS#5,HMC_RLD2_QK5,DIFFIO_RX_B57_NAE24
HMC_DQ5_4,DIFFIO_RX_B59_NAW23
HMC_DQS4,HMC_RLD2_QK#4,HMC_QDR2_CQ4/CQ#4,DIFFIO_RX_B50_PAU26
HMC_DQ5_8,DIFFIO_TX_B54_PAD24
HMC_DQ4_1,DIFFIO_RX_B53_NAV25
HMC_DQ4_2AL26
HMC_DQ4_5,DIFFIO_TX_B51_PAT25
HMC_DQ4_8,DIFFIO_TX_B47_PAP26
HMC_DQ4_3,DIFFIO_RX_B52_PAW26
HMC_DQ4_6,DIFFIO_RX_B48_PAN25
HMC_DQ4_4,DIFFIO_RX_B52_NAW25
HMC_DQ5_0,DIFFIO_RX_B61_PAU23
HMC_DQ4_7,DIFFIO_RX_B48_NAM25
DIFFIO_TX_B49_NAJ25DIFFIO_TX_B47_NAN26
DIFFIO_TX_B41_NAE27
DIFFIO_TX_B45_NAD26DIFFIO_TX_B43_NAC24
DIFFIO_TX_B51_NAR25
DIFFIO_TX_B54_NAD23
DIFFIO_TX_B56_NAK24
DIFFIO_TX_B39_NAG27
DIFFIO_TX_B74_P,DQ10BAH22
DIFFIO_TX_B70_P,DQ10BAP22
DIFFIO_RX_B75_N,DQ10BAT20
DIFFIO_RX_B71_N,DQ10BAW19
DIFFIO_TX_B83_P,DQ11BAH20
DIFFIO_TX_B72_P,DQ10BAL22
DIFFIO_RX_B75_P,DQ10BAU20
DQ10BAK21
DIFFIO_RX_B71_P,DQ10BAW20
DIFFIO_RX_B67_P,DQ9BAW21
DIFFIO_RX_B69_P,DQ9BAF22
DIFFIO_TX_B81_P,DQ11BAP20
DIFFIO_TX_B66_P,DQ9BAW22
DIFFIO_RX_B69_N,DQ9BAE22
DIFFIO_TX_B62_P,DQ9BAP23
DIFFIO_TX_B64_P,DQ9BAL23
DIFFIO_TX_B68_P,DQ9BAH23
DIFFIO_TX_B77_P,DQ11BAN21
DIFFIO_TX_B77_NAM21
DIFFIO_TX_B72_NAK22
DIFFIO_RX_B65_P,DQS9BAU22
DIFFIO_TX_B83_NAG20
DIFFIO_RX_B67_N,DQ9BAV21
DIFFIO_RX_B65_N,DQSn9BAT22
DIFFIO_RX_B73_N,DQSn10BAR21
DIFFIO_TX_B66_NAV22
DIFFIO_TX_B81_NAN20
DIFFIO_TX_B74_NAG22
DIFFIO_RX_B63_N,DQ9BAD22
DIFFIO_RX_B73_P,DQS10BAT21
DIFFIO_TX_B70_NAN22
DIFFIO_TX_B68_NAG23
DIFFIO_RX_B63_P,DQ9BAE23
DIFFIO_TX_B64_NAK23 DIFFIO_TX_B62_NAN23
Bank 3A
Bank 3B
Arria V SX (SoC) Bank 3
5ASTFD5K3_F1517
U41A
HMC_A_14,DIFFIO_TX_B14_PAE29
HMC_CAS#,HMC_RLD2_REF#,HMC_QDR2_WPS#,DIFFIO_RX_B11_PAW32
HMC_DQS1,HMC_RLD2_QK#1,HMC_QDR2_CQ1/CQ#1,DIFFIO_RX_B27_PAJ28
DIFFIO_TX_B31_NAP28
DIFFIO_TX_B28_NAD28
DIFFIO_TX_B33_NAJ27
HMC_BA_1,HMC_QDR2_A_17,DIFFIO_RX_B13_NAR31
HMC_BA_2,HMC_QDR2_A_18,DIFFIO_TX_B12_PAP31
HMC_BA_0,HMC_QDR2_A_16,DIFFIO_RX_B13_PAT31
HMC_CKE_1,HMC_RLD2_A_17,DIFFIO_TX_B22_NAN30
HMC_CK,DIFFIO_RX_B23_PAP29
HMC_CKE_0,HMC_RLD2_A_16,DIFFIO_TX_B22_PAP30
HMC_CK#,DIFFIO_RX_B23_NAN29
HMC_DQS#1,HMC_RLD2_QK1,DIFFIO_RX_B27_NAH28
HMC_DQ2_7,DIFFIO_RX_B32_NAU28
HMC_DQ2_8,DIFFIO_TX_B31_PAR28
HMC_DQ2_6,DIFFIO_RX_B32_PAV28
HMC_RESET#,HMC_RLD2_A_19,DIFFIO_TX_B24_NAB29
HMC_DQ1_3,DIFFIO_RX_B29_PAB28
HMC_A_13,DIFFIO_RX_B15_NAG30
HMC_DQ1_1,DIFFIO_RX_B30_NAC27
HMC_A_11,DIFFIO_TX_B16_NAU31
HMC_A_15,DIFFIO_TX_B14_NAD29
HMC_DQ1_7,DIFFIO_RX_B25_NAF28
HMC_DQ2_4,DIFFIO_RX_B36_NAT27
HMC_DQ1_2,AM28
HMC_DQ1_8,DIFFIO_TX_B24_PAC29
HMC_A_1,DIFFIO_RX_B21_NAT29
HMC_DQ2_0,DIFFIO_RX_B38_PAW27
HMC_A_12,DIFFIO_RX_B15_PAH30
HMC_DM2,DIFFIO_TX_B33_PAK27
HMC_DQ2_3,DIFFIO_RX_B36_PAU27
HMC_DQ1_5,DIFFIO_TX_B28_PAE28 HMC_DQ1_4,DIFFIO_RX_B29_NAB27 HMC_DQ2_5,DIFFIO_TX_B35_P
AR27
HMC_DQ1_6,DIFFIO_RX_B25_PAG28
HMC_DM1,DIFFIO_TX_B26_PAL29
HMC_DQ1_0,DIFFIO_RX_B30_PAD27
RZQ_0,DIFFIO_TX_B1_NAN33
HMC_A_10,DIFFIO_TX_B16_PAV31
HMC_DQ2_2,DIFFIO_TX_B37_PAN27
HMC_A_0,DIFFIO_RX_B21_PAU29
HMC_DQ2_1,DIFFIO_RX_B38_NAV27
HMC_DQS2,HMC_RLD2_QK#2,HMC_QDR2_CQ2/CQ#2,DIFFIO_RX_B34_PAW28
HMC_DQS#2,HMC_RLD2_QK2,DIFFIO_RX_B34_NAW29
DIFFIO_TX_B35_NAP27
DIFFIO_TX_B37_NAM27
DIFFIO_TX_B26_NAK29
HMC_A_5,DIFFIO_RX_B19_NAR30
HMC_A_7,DIFFIO_TX_B18_NAK30
HMC_A_9,DIFFIO_RX_B17_NAW30
HMC_A_2,DIFFIO_TX_B20_PAV30
HMC_A_6,DIFFIO_TX_B18_PAL30
HMC_A_3,DIFFIO_TX_B20_NAU30
HMC_A_8,DIFFIO_RX_B17_PAW31
HMC_A_4,DIFFIO_RX_B19_PAT30
HMC_CS#_1,DIFFIO_TX_B8_NAN32
DIFFIO_TX_B3_P,DQ1BAL32
HMC_RAS#,HMC_RLD2_A_21,DIFFIO_TX_B12_NAN31
HMC_WE#,DIFFIO_RX_B11_NAW33
HMC_CS#_0,DIFFIO_TX_B8_PAP32
HMC_ODT_1,HMC_RLD2_A_20,DIFFIO_TX_B10_NAL31HMC_ODT_0,HMC_RLD2_A_18,DIFFIO_TX_B10_PAM31
DIFFIO_TX_B1_P,DQ1BAP33
DIFFIO_TX_B3_NAK32
DQ1BAK31
R499100, 1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Arria V ST Bank 4
1.5 Volt
1.5 Volt
1.5 Volt
2.5 Volt
DDR3B_A0DDR3B_A1DDR3B_A2DDR3B_A3DDR3B_A4DDR3B_A5DDR3B_A6DDR3B_A7DDR3B_A8DDR3B_A9DDR3B_A10
DDR3B_A11DDR3B_A12DDR3B_A13DDR3B_A14
DDR3B_BA0DDR3B_BA1DDR3B_BA2
DDR3B_CASnDDR3B_RASn
DDR3B_WEn
DDR3B_ODT
DDR3B_CSn
DDR3B_CKE
DDR3B_CLK_PDDR3B_CLK_N
DDR3B_RESETn
DDR3B_DM0DDR3B_DQS_P0DDR3B_DQS_N0
DDR3B_DQ0DDR3B_DQ1
DDR3B_DQ2
DDR3B_DQ3DDR3B_DQ4
DDR3B_DQ5
DDR3B_DQ6DDR3B_DQ7
DDR3B_DQS_P1DDR3B_DQS_N1
DDR3B_DQ8DDR3B_DQ9
DDR3B_DQ10
DDR3B_DQ11DDR3B_DQ12
DDR3B_DQ13
DDR3B_DQ14DDR3B_DQ15
DDR3B_DM1
DDR3B_DM2DDR3B_DQS_P2DDR3B_DQS_N2DDR3B_DQ16DDR3B_DQ17DDR3B_DQ18DDR3B_DQ19DDR3B_DQ20DDR3B_DQ21DDR3B_DQ22DDR3B_DQ23
DDR3B_DM3DDR3B_DQS_P3DDR3B_DQS_N3
DDR3B_DQ24DDR3B_DQ25DDR3B_DQ26
DDR3B_DQ28DDR3B_DQ29DDR3B_DQ30DDR3B_DQ31
DDR3B_DQ27
SFPB_RATESEL0SFPB_RATESEL1
SFPB_TXDISABLE
SFPA_LOSSFPA_TXFAULT
SFPA_RATESEL0SFPA_RATESEL1
SFPA_MOD2_SDASFPA_MOD1_SCLSFPA_MOD0_PRSNTn
SFPA_TXDISABLE
SFPA_RATESEL0SFPA_RATESEL1
SFPA_MOD2_SDA
SFPA_MOD1_SCLSFPA_MOD0_PRSNTn
SFPA_TXDISABLESFPA_LOSSFPA_TXFAULT
SFPB_RATESEL0SFPB_RATESEL1
SFPB_TXDISABLE
DDR3B_CASn17
DDR3B_CSn17
DDR3B_CLK_P17
DDR3B_CLK_N17
DDR3B_ODT17
DDR3B_RASn17
DDR3B_WEn17
DDR3B_A[14:0]17
DDR3B_RESETn17
DDR3B_DQS_P[3:0]17
DDR3B_DQS_N[3:0]17
DDR3B_DM[3:0]17
DDR3B_DQ[31:0]17
DDR3B_BA[2:0]17
SFPB_RATESEL023
SFPB_TXDISABLE23
SFPB_RATESEL123
SFPA_TXFAULT22SFPA_LOS22
SFPA_MOD1_SCL22
SFPA_RATESEL022
SFPA_TXDISABLE22
SFPA_MOD0_PRSNTn22
SFPA_MOD2_SDA22
SFPA_RATESEL122
DDR3B_CKE17
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
5 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
5 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
5 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Bank 4A
Arria V SX (SoC) Bank 4
Bank 4B
5ASTFD5K3_F1517
U41B
HMC_DQ5_3,DIFFIO_RX_B143_PAR10
DQ21BAH8
DIFFIO_TX_B163_NAT6
DIFFIO_TX_B167_NAN7
DIFFIO_RX_B153_N,DQ20BAT8
DIFFIO_TX_B165_NAK8
DIFFIO_RX_B153_P,DQ20BAR9
HMC_DQ5_2,DIFFIO_TX_B144_PAL11
DIFFIO_TX_B146_NAL9
DIFFIO_TX_B165_P,DQ22BAL8 DIFFIO_TX_B148_N
AV7DIFFIO_TX_B163_P,DQ22B
AU6 RZQ_1,DIFFIO_TX_B167_P,DQ22BAP7
HMC_DQ5_5,DIFFIO_TX_B142_PAE12HMC_DQ5_4,DIFFIO_RX_B143_NAP10
HMC_DQS#3,HMC_RLD2_QK3,DIFFIO_RX_B126_NAV12
HMC_DQ5_7,DIFFIO_RX_B139_NAF12
HMC_DQ5_8,DIFFIO_TX_B138_PAD11
HMC_DQ5_6,DIFFIO_RX_B139_PAG12
HMC_DQS4,HMC_RLD2_QK#4,HMC_QDR2_CQ4/CQ#4,DIFFIO_RX_B134_PAU11
HMC_DQS#5,HMC_RLD2_QK5,DIFFIO_RX_B141_NAG11
HMC_DQS3,HMC_RLD2_QK#3,HMC_QDR2_CQ3/CQ#3,DIFFIO_RX_B126_PAW12
HMC_DQS#4,HMC_RLD2_QK4,DIFFIO_RX_B134_NAT11
DIFFIO_TX_B140_NAT9
DIFFIO_TX_B144_NAK11DIFFIO_TX_B142_NAD12
HMC_DQS5,HMC_RLD2_QK#5,HMC_QDR2_CQ5/CQ#5,DIFFIO_RX_B141_PAH11
DIFFIO_TX_B131_NAH12
DIFFIO_TX_B135_NAK12DIFFIO_TX_B133_NAU10
DIFFIO_TX_B138_NAC12
DIFFIO_TX_B123_NAP13
DIFFIO_TX_B127_NAL13DIFFIO_TX_B125_NAT12
DIFFIO_TX_B129_NAN12
HMC_DQ5_0,DIFFIO_RX_B145_PAM10
HMC_DQ4_8,DIFFIO_TX_B131_PAJ12
HMC_DQ4_6,DIFFIO_RX_B132_PAG13
HMC_DQ4_4,DIFFIO_RX_B136_NAC13
HMC_DQ4_1,DIFFIO_RX_B137_NAV9
HMC_DQ3_8,DIFFIO_TX_B123_PAR13
HMC_DQ4_5,DIFFIO_TX_B135_PAL12
HMC_DQ3_7,DIFFIO_RX_B124_NAE14
HMC_DQ4_3,DIFFIO_RX_B136_PAD13
HMC_DQ3_6,DIFFIO_RX_B124_PAE13
HMC_DQ4_2,AP11
HMC_DQ4_7,DIFFIO_RX_B132_NAF13
HMC_DQ5_1,DIFFIO_RX_B145_NAL10
HMC_DQ4_0,DIFFIO_RX_B137_PAW9
HMC_DM3,DIFFIO_TX_B125_PAU12
HMC_DM4,DIFFIO_TX_B133_PAV10
HMC_DQ3_4,DIFFIO_RX_B128_NAW10
HMC_DQ3_5,DIFFIO_TX_B127_PAM13
HMC_DQ3_3,DIFFIO_RX_B128_PAW11
HMC_DM5,DIFFIO_TX_B140_PAU9
HMC_DQ3_0,DIFFIO_RX_B130_PAJ13
HMC_DQ3_1,DIFFIO_RX_B130_NAH13
HMC_DQ3_2,DIFFIO_TX_B129_PAP12
Bank 4C
Arria V SX (SoC) Bank 4
Bank 4D
5ASTFD5K3_F1517
U41P
DIFFIO_TX_B91_P,DQ12BAF19
HMC_DQ1_3,DIFFIO_RX_B113_PAW13
HMC_DQ2_6,DIFFIO_RX_B116_PAU14HMC_DQ2_8,DIFFIO_TX_B115_PAD14
HMC_DQ1_2,AH15
HMC_DQ2_7,DIFFIO_RX_B116_NAT14
HMC_DQ1_1,DIFFIO_RX_B114_NAT15
HMC_WE#,HMC_RLD2_WE#,HMC_QDR2_RPS#,DIFFIO_RX_B96_NAP18
HMC_DQ2_4,DIFFIO_RX_B120_NAN14
HMC_DQ1_0,DIFFIO_RX_B114_PAU15
HMC_DQ2_5,DIFFIO_TX_B119_PAL14
HMC_DM2,DIFFIO_TX_B117_PAU13
HMC_DM1,DIFFIO_TX_B110_PAD16
DIFFIO_TX_B87_P,DQ12BAP19
DIFFIO_TX_B89_P,DQ12BAJ18
HMC_A_10,DIFFIO_TX_B100_PAH17
DIFFIO_RX_B92_P,DQ12BAW16
DIFFIO_RX_B92_N,DQ12BAW17
DIFFIO_TX_B85_P,DQ12BAW18
HMC_A_7,DIFFIO_TX_B102_NAR16
HMC_ODT_0,HMC_RLD2_A_18,DIFFIO_TX_B95_PAD19
HMC_A_1,DIFFIO_RX_B105_NAN16
HMC_A_8,DIFFIO_RX_B101_PAP17
DIFFIO_TX_B89_NAH18
DIFFIO_TX_B85_NAV18
DIFFIO_TX_B87_NAN19
HMC_CS#_1,DIFFIO_TX_B93_NAK17
DIFFIO_RX_B94_N,DQ13BAT17
DIFFIO_RX_B88_N,DQSn12BAK19DIFFIO_RX_B88_P,DQS12BAL19
DIFFIO_TX_B91_NAE19
DIFFIO_RX_B90_P,DQ12BAT19
DIFFIO_RX_B86_P,DQ12BAH19
DIFFIO_RX_B90_N,DQ12BAU18
DIFFIO_RX_B86_N,DQ12BAG19
HMC_ODT_1,HMC_RLD2_A_20,DIFFIO_TX_B95_NAC19
HMC_CKE_1,HMC_RLD2_A_17,DIFFIO_TX_B106_NAL16
HMC_CK#,DIFFIO_RX_B107_NAE17
HMC_CAS#,HMC_RLD2_REF#,HMC_QDR2_WPS#,DIFFIO_RX_B96_PAR18
HMC_BA_0,DIFFIO_RX_B98_PAE18
HMC_A_5,DIFFIO_RX_B103_NAU16
HMC_CK,DIFFIO_RX_B107_PAF16
HMC_A_4,DIFFIO_RX_B103_PAV16
HMC_BA_2,DIFFIO_TX_B97_PAC18
HMC_A_3,DIFFIO_TX_B104_NAJ16
HMC_BA_1,DIFFIO_RX_B98_NAD18
HMC_CKE_0,HMC_RLD2_A_16,DIFFIO_TX_B106_PAM16
HMC_RAS#,HMC_RLD2_A_15,DIFFIO_TX_B97_NAD17
HMC_A_9,DIFFIO_RX_B101_NAN17
HMC_A_0,DIFFIO_RX_B105_PAP16
HMC_A_6,DIFFIO_TX_B102_PAT16
HMC_A_15,DIFFIO_RX_B94_PAU17
HMC_A_2,DIFFIO_TX_B104_PAK16
HMC_A_14AG18
HMC_CS#_0,DIFFIO_TX_B93_PAL17
HMC_A_11,DIFFIO_TX_B100_NAG17
HMC_A_12,DIFFIO_RX_B99_PAM18
HMC_A_13,DIFFIO_RX_B99_NAL18
HMC_DQ1_4,DIFFIO_RX_B113_NAV13
HMC_DQ1_7,DIFFIO_RX_B109_NAW14
HMC_DQ1_8,DIFFIO_TX_B108_PAP15
HMC_DQ1_6,DIFFIO_RX_B109_PAW15
HMC_DQ2_0,DIFFIO_RX_B122_PAE15
HMC_DQ1_5,DIFFIO_TX_B112_PAL15
HMC_DQS2,HMC_RLD2_QK#2,HMC_QDR2_CQ2/CQ#2,DIFFIO_RX_B118_PAF15
HMC_DQS#2,HMC_RLD2_QK2,DIFFIO_RX_B118_NAE16
HMC_DQS1,HMC_RLD2_QK#1,HMC_QDR2_CQ1/CQ#1,DIFFIO_RX_B111_PAH16
HMC_DQS#1,HMC_RLD2_QK1,DIFFIO_RX_B111_NAG16
HMC_RESET#,HMC_RLD2_A_19,DIFFIO_TX_B108_NAN15
DIFFIO_TX_B121_NAG14
DIFFIO_TX_B115_NAC15
DIFFIO_TX_B117_NAT13
DIFFIO_TX_B112_NAK15 DIFFIO_TX_B119_N
AK14
HMC_DQ2_1,DIFFIO_RX_B122_NAD15
HMC_DQ2_2,DIFFIO_TX_B121_PAH14
HMC_DQ2_3,DIFFIO_RX_B120_PAP14
DIFFIO_TX_B110_NAC16
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Bank 6 & 7G
1.5 Volt
1.5 Volt
Variable Voltage
Si571 VCXOFMC PORT B INTERFACE
DDR3_HPS_RZQIN
DDR3_HPS_A7
DDR3_HPS_A3
DDR3_HPS_A8
DDR3_HPS_A13
DDR3_HPS_A6
DDR3_HPS_A12
DDR3_HPS_A2
DDR3_HPS_A9
DDR3_HPS_A14
DDR3_HPS_A4
DDR3_HPS_A10
DDR3_HPS_A5
DDR3_HPS_A11
DDR3_HPS_A1DDR3_HPS_A0
DDR3_HPS_BA1DDR3_HPS_BA2
DDR3_HPS_BA0
DDR3_HPS_CLK_P
DDR3_HPS_CKEDDR3_HPS_CLK_N
DDR3_HPS_CSn
DDR3_HPS_ODT
DDR3_HPS_CASnDDR3_HPS_WEn
DDR3_HPS_RASn
DDR3_HPS_DQS_P0DDR3_HPS_DQS_N0
DDR3_HPS_DM0
DDR3_HPS_DQ7
DDR3_HPS_DQ0
DDR3_HPS_DQ2
DDR3_HPS_DQ4DDR3_HPS_DQ3
DDR3_HPS_DQ1
DDR3_HPS_DQ6DDR3_HPS_DQ5
DDR3_HPS_DQS_P1DDR3_HPS_DQS_N1
DDR3_HPS_DM1
DDR3_HPS_DQ13DDR3_HPS_DQ14
DDR3_HPS_DQ8
DDR3_HPS_DQ10
DDR3_HPS_DQ15
DDR3_HPS_DQ9
DDR3_HPS_DQ12DDR3_HPS_DQ11
DDR3_HPS_DQS_P2DDR3_HPS_DQS_N2
DDR3_HPS_DM2
DDR3_HPS_DQ23
DDR3_HPS_DQ16
DDR3_HPS_DQ18
DDR3_HPS_DQ20DDR3_HPS_DQ19
DDR3_HPS_DQ17
DDR3_HPS_DQ22DDR3_HPS_DQ21
DDR3_HPS_DQS_P3DDR3_HPS_DQS_N3
DDR3_HPS_DM3
DDR3_HPS_DQ29DDR3_HPS_DQ30
DDR3_HPS_DQ24
DDR3_HPS_DQ26DDR3_HPS_DQ25
DDR3_HPS_DQ28DDR3_HPS_DQ27
DDR3_HPS_DQ31
DDR3_HPS_DQS_P4DDR3_HPS_DQS_N4
DDR3_HPS_DM4
DDR3_HPS_DQ32
DDR3_HPS_DQ39
DDR3_HPS_DQ34DDR3_HPS_DQ35DDR3_HPS_DQ36DDR3_HPS_DQ37DDR3_HPS_DQ38
DDR3_HPS_DQ33
DDR3_HPS_RESETn
FMCB_PRSNTn FMCB_SDAFMCB_SCL
FMCB_GPIO2FMCB_GPIO3
FMCB_GPIO4FMCB_GPIO5FMCB_GPIO6FMCB_GPIO7
DDR3_HPS_CASn15
DDR3_HPS_CSn15
DDR3_HPS_CLK_P15
DDR3_HPS_CLK_N15
DDR3_HPS_ODT15
DDR3_HPS_RASn15
DDR3_HPS_WEn15
DDR3_HPS_A[14:0]15
DDR3_HPS_RESETn15
DDR3_HPS_DQS_P[4:0]15
DDR3_HPS_DQS_N[4:0]15
DDR3_HPS_DM[4:0]15
DDR3_HPS_DQ[39:0]15
DDR3_HPS_BA[2:0]15
SDI_CLK148_DN 4,9DDR3_HPS_CKE
15
FMCB_SDA25
FMCB_SCL25
FMCB_PRSNTn25,28
FMCB_GPIO[7:0]25
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
6 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
6 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
6 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Arria V SX (SoC) Bank 7GBank 7G
5ASTFD5K3_F1517
U41E
DIFFIO_TX_T18_PL19
ION19
DIFFIO_RX_T16_NT19 DIFFIO_RX_T16_PR19
DIFFIO_RX_T21_NM20
DIFFIO_RX_T17_NU20 DIFFIO_RX_T17_PU19
DIFFIO_RX_T21_PL20DIFFIO_RX_T19_NR20DIFFIO_RX_T19_PP20
DIFFIO_TX_T20_PM19
R576100, 1%
Arria V SX (SoC) Bank 6Bank 6A
Bank 6B
5ASTFD5K3_F1517
U41C
HPS_DM_0C6
HPS_CS#_1J9
HPS_A_0N9
HPS_A_7A9
HPS_A_9C10
HPS_BA_0L7
HPS_BA_2D8 HPS_BA_1C9
HPS_CAS#G9
HPS_CKA11
HPS_CK#B10
HPS_A_5B7
HPS_A_1M9
HPS_DM_1E4
HPS_A_10K7
HPS_A_12F9
HPS_DQ_0D7
HPS_A_11J7
HPS_DQ_10N8
HPS_A_13E9
HPS_DQ_1C7
HPS_A_14D11
HPS_DQ_11G5
HPS_A_2N10
HPS_DQ_12A4
HPS_A_15D10
HPS_DQ_14R9
HPS_A_3M10
HPS_DQ_13A5
HPS_A_4A8
HPS_DQ_15F4
HPS_A_6B9
HPS_A_8D9
HPS_CS#_0H9
HPS_CKE_0R8
HPS_CKE_1F5
HPS_DQ_4A6
HPS_DQ_9G6
HPS_DQ_2R10
HPS_DQ_5A7
HPS_DQ_8H6
HPS_DQ_3G7
HPS_DQS#_0E7
HPS_DQ_6L6
HPS_DQS#_1E6
HPS_DQ_7D6
HPS_DQS_0F7
HPS_GPI1M7
HPS_ODT_0H7
HPS_WE#J8
HPS_RZQ_0K9
HPS_ODT_1K6
HPS_RAS#G8
HPS_GPI3C4
HPS_GPI0B6
HPS_GPI2B4
HPS_DQS_1D5
HPS_RESET#E3
HPS_DQS_2G4
HPS_DQS_3C2
HPS_DQ_39R6HPS_DQ_38N1
HPS_DQS#_2H4 HPS_DQS#_4
H1
HPS_DQS#_3D2
HPS_DQ_37M1
HPS_DQS_4J1
HPS_GPI12R7
HPS_GPI5L4HPS_GPI4M6
HPS_GPI13K1
HPS_GPI11J2HPS_GPI10K2
HPS_GPI6K4
HPS_GPI7K3
HPS_GPI9B1HPS_GPI8N6
HPS_DM_3D1
HPS_DQ_21J4
HPS_DQ_17K5
HPS_DQ_22M5
HPS_DM_4T7
HPS_DQ_18N7
HPS_DQ_16J5
HPS_DQ_19F3
HPS_DQ_20H3
HPS_DM_2D3
HPS_DQ_25A3
HPS_DQ_31E1
HPS_DQ_36M2
HPS_DQ_34P6
HPS_DQ_27C1
HPS_DQ_23C3
HPS_DQ_32G1
HPS_DQ_35L1
HPS_DQ_30M3 HPS_DQ_29F2 HPS_DQ_28G2
HPS_DQ_24A2
HPS_DQ_33F1
HPS_DQ_26P7
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Bank 7
ETHERNET INTERFACE
Micro SD / USB INTERFACE
BOOTSEL0
BOOTSEL1
BOOTSEL2
CLKSEL0
CLKSEL1
Logic 0 = pin 6 <--> pin 7 (Bypass)Logic 1 = pin 6 <--> pin 4 (Enable)
Logic 0 = pin 10 <--> pin 9 (TRST from JTAG)Logic 1 = pin 10 <--> pin 2 (TRST from MICTOR)
3.3 Volt
3.3 Volt
3.3 Volt
3.3 Volt
3.3 Volt
ENET_HPS_TX_ENENET_HPS_GTX_CLK
ENET_HPS_MDIO
ENET_HPS_MDC
ENET_HPS_RX_DV
ENET_HPS_TXD[3..0]
ENET_HPS_RX_CLK
ENET_HPS_RXD[3..0]
ENET_HPS_RESETn
ENET_HPS_INTn
USB_DATA[7..0]
MICTOR_PWR2
TRACE_CLK_MIC
MICTOR_PWR1
JTAG_MICTOR_TCKJTAG_MICTOR_TMS
JTAG_HPS_TRST
BOOTSEL2
QSPI_SS0
BOOTSEL0
CLKSEL1
UARTA_TX
MICTOR_TRST
MICTOR_RSTn
JTAG_MICTOR_TMSJTAG_MICTOR_TDI
HPS_RESETn
USER_LED_HPS[3:0]
MICTR_TRST
MICTOR_TRST
JTAG_MIC_SEL
TRACE_DATA7TRACE_DATA6TRACE_DATA5TRACE_DATA4TRACE_DATA3TRACE_DATA2TRACE_DATA1
TRACE_DATA0
MIC_34MIC_36
JTAG_HPS_TRST
JTAG_MICTOR_TDI
JTAG_MICTOR_TDO
MIC_36MIC_34
JTAG_MIC_SEL
MICTOR_RSTnHPS_RESETn
TRACE_DATA0
TRACE_DATA2TRACE_DATA1
TRACE_CLK_MIC
TRACE_DATA3TRACE_DATA4TRACE_DATA5
TRACE_DATA7TRACE_DATA6
USER_DIPSW_HPS[3:0]
USER_DIPSW_HPS0
USER_DIPSW_HPS1
USER_DIPSW_HPS2USER_DIPSW_HPS3
USER_LED_HPS2USER_LED_HPS3USER_PB_HPS[3:0]
USER_PB_HPS0
SD_CD_DAT3 SD_CLK
SD_CMD
SD_DAT0SD_DAT1SD_DAT2
USB_STPUSB_DIRUSB_NXT
USB_CLK
USB_DATA6USB_DATA5USB_DATA7
USB_DATA4 USB_DATA0USB_DATA1USB_DATA2USB_DATA3
USER_LED_HPS0
ENET_HPS_RXD3ENET_HPS_RXD2
ENET_HPS_TXD2ENET_HPS_TXD3
ENET_HPS_MDCENET_HPS_MDIOENET_HPS_RX_CLKENET_HPS_RX_DV
CLKSEL1
BOOTSEL0
BOOTSEL2
ENET_HPS_GTX_CLK
ENET_HPS_TXD0ENET_HPS_TXD1
ENET_HPS_RXD0ENET_HPS_RXD1
ENET_HPS_TX_EN
USER_LED_HPS1
ENET_HPS_INTn
USER_PB_HPS2USER_PB_HPS3
USER_PB_HPS1JTAG_HPS_TCK
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
2.5V_REG_HPS 3.3V
2.5V_HPS
2.5V_REG_HPS
3.3V
ENET_HPS_RESETn20,26ENET_HPS_MDC20
ENET_HPS_GTX_CLK20
ENET_HPS_MDIO20
ENET_HPS_TX_EN20
ENET_HPS_RXD[3..0]20
ENET_HPS_RX_DV20ENET_HPS_RX_CLK20
ENET_HPS_TXD[3..0]20
ENET_HPS_INTn20
USB_DATA[7..0]27
JTAG_MICTOR_TCK 14JTAG_MICTOR_TMS 14
HPS_RESETn19,26
MICTOR_RSTn 14,19,26
USER_LED_HPS[3:0]28
JTAG_TRST 14,19
JTAG_MICTOR_TDO 14
JTAG_MICTOR_TDI 14
JTAG_HPS_TCK14
JTAG_HPS_TMS14
JTAG_HPS_TDI14JTAG_HPS_TDO14
CLK_OSC111CLK_OSC211
I2C_SDA_HPS 20,28,33
I2C_SCL_HPS 20,28,33
UARTA_RX 29
UARTA_TX 29
UARTB_RX 29
UARTB_TX 29
QSPI_CLK 26
QSPI_SS0 26
QSPI_IO3 26
QSPI_IO2 26
QSPI_IO1 26
QSPI_IO0 26
USER_DIPSW_HPS[3:0]28
USER_PB_HPS[3:0]28
SD_CD_DAT3 27 SD_CLK27
SD_CMD 27
SD_DAT0 27SD_DAT1 27SD_DAT2 27
USB_STP 27USB_DIR 27
USB_NXT 27
USB_CLK 27
USB_DATA6 27USB_DATA5 27USB_DATA7 27
USB_DATA4 27 USB_DATA027USB_DATA127USB_DATA227USB_DATA327
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
7 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
7 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
7 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R429 10K
R541 22R53822
R259 1.00K
Arria V SX (SoC) Bank 7Bank 7A
Bank 7B
Bank 7C
Bank 7D
Bank 7E
5ASTFD5K3_F1517
U41D
SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57P12
UART0_TX,CLKSEL1,SPIM1_SS1,HPS_GPIO62A15
SPIM0_MISO,UART1_CTS,HPS_GPIO59N12
SPIM0_SS0,SPIM0_SS0,HPS_GPIO66P13
TRACE_CLK,HPS_GPIO48J11
SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58A14
SPIS1_MOSI,SPIM1_MOSI,HPS_GPIO68E13HPS_CLK1
N11 SPIS1_SS0,SPIM1_SS0,HPS_GPIO70D13
SPIS1_MISO,SPIM1_MISO,HPS_GPIO69F13
SPIM0_SS0,BOOTSEL0,UART1_RTS,HPS_GPIO60B15
SPIS0_CLK,SPIM0_SS1,HPS_GPIO67H13
SPIS1_CLK,SPIM1_CLK,HPS_GPIO67L12
SPIS0_MOSI,HPS_GPIO68C14
SPIS0_SS0,HPS_GPIO70D14
SPIS0_MISO,HPS_GPIO69J13
HPS_CLK2D12
HPS_nPORK10
HPS_TCKG10
HPS_nRSTR11
HPS_TDIH10
HPS_PORSELC12
UART1_TX,SPIM0_CLK,HPS_GPIO63N13
TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49K12
HPS_TDOT11
UART0_TX*,CLKSEL0,UART0_TX,SPIM1_SS0,HPS_GPIO66M13
UART0_RX,SPIM0_SS1,HPS_GPIO61B14
HPS_TMSF10
UART0_RX*,UART0_RX,SPIM1_MISO,HPS_GPIO65M12
TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56A13
TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50K11
HPS_TRSTF11
I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63C13
TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51J12
I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64L13
TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55F12
I2C1_SCL,SPIM0_MISO,HPS_GPIO65M14
TRACE_D4,SPIS1_CLK,HPS_GPIO53E12
TRACE_D5,SPIS1_MOSI,HPS_GPIO54G11
I2C1_SDA,SPIM0_MOSI,HPS_GPIO64R13
TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52H12
UART1_RX,SPIM1_SS1,HPS_GPIO62G13
NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17R15
QSPI_IO2,USB1_DIR,HPS_GPIO31M15
QSPI_IO3,USB1_NXT,HPS_GPIO32H15
NAND_WE,BOOTSEL2,QSPI_SS1,HPS_GPIO28L14
NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14A16
NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27C15
NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18C16
NAND_DQ7,RGMII1_RXD2,HPS_GPIO26K14
QSPI_SS1,HPS_GPIO35E15
QSPI_SS0,BOOTSEL1,HPS_GPIO33N15
QSPI_IO0,USB1_CLK,HPS_GPIO29D15
QSPI_IO1,USB1_STP,HPS_GPIO30G15
QSPI_CLK,HPS_GPIO34F15
NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16A17
NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23P14
NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25R14 NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24K15
NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15P15
NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22L15
NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20B17 NAND_DQ0,RGMII1_RXD0,HPS_GPIO19G14
NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21H14
SDMMC_CCLK_OUT,USB0_STP,HPS_GPIO45L16
SDMMC_CMD,USB0_D0,HPS_GPIO36D16
SDMMC_FB_CLK_IN,USB0_CLK,HPS_GPIO44K16
SDMMC_PWREN,USB0_D1,HPS_GPIO37P16
SDMMC_D0,USB0_D2,HPS_GPIO38C17
SDMMC_D1,USB0_D3,HPS_GPIO39N16
SDMMC_D2,USB0_DIR,HPS_GPIO46J16
SDMMC_D3,USB0_NXT,HPS_GPIO47M16
SDMMC_D4,USB0_D4,HPS_GPIO40F16
SDMMC_D5,USB0_D5,HPS_GPIO41G16
SDMMC_D6,USB0_D6,HPS_GPIO42E16
SDMMC_D7,USB0_D7,HPS_GPIO43H16
RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7K17
RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6D18
RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10C18 RGMII0_RX_CTL,USB1_D7,HPS_GPIO8B19
RGMII0_RXD0,USB1_D4,HPS_GPIO5J17
RGMII0_RXD1,USB1_STP,HPS_GPIO11A19
RGMII0_RXD2,USB1_DIR,HPS_GPIO12C19
RGMII0_RXD3,USB1_NXT,HPS_GPIO13G18
RGMII0_TX_CLK,HPS_GPIO0R17
RGMII0_TX_CTL,HPS_GPIO9A18
RGMII0_TXD0,USB1_D0,HPS_GPIO1F17
RGMII0_TXD1,USB1_D1,HPS_GPIO2P17
RGMII0_TXD2,USB1_D2,HPS_GPIO3F18
RGMII0_TXD3,USB1_D3,HPS_GPIO4E18
RGMII1_RXD0,HPS_GPIO52E19
RGMII1_RXD1,HPS_GPIO53M17
RGMII1_TX_CLK,HPS_GPIO48D19
RGMII1_TX_CTL,HPS_GPIO51N18
RGMII1_TXD0,HPS_GPIO49H18
RGMII1_TXD1,HPS_GPIO50F19
RGMII1_MDC,SPIM0_MOSI,SPIS0_MOSI,HPS_GPIO55L18
RGMII1_MDIO,SPIM0_CLK,SPIS0_CLK,HPS_GPIO54J18
RGMII1_RX_CLK,SPIS1_CLK,SPIM1_CLK,HPS_GPIO58G21
RGMII1_RX_CTL,SPIS1_MOSI,SPIM1_MOSI,HPS_GPIO59H19
RGMII1_RXD2,SPIS1_MISO,SPIM1_MISO,HPS_GPIO60G20
RGMII1_RXD3,SPIS1_SS0,SPIM1_SS0,HPS_GPIO61G19
RGMII1_TXD2,SPIM0_MISO,SPIS0_MISO,HPS_GPIO56K18
RGMII1_TXD3,SPIM0_SS0,SPIS0_SS0,HPS_GPIO57M18
R54622
R261 1.00K
R428 10K
R2551.00K
R55722J38
HEADER, 1x3-PIN
123
J28
CON2
12
R260 10.0K
R25410.0K
R564 0
XJ9
881545-2
R1010_Ohms
R262 10.0K
R551
4.70K, 1%
XJ11
881545-2
R426 10K
R263 1.00K
R76 4.70K, 1%
R563 22
R4001
37.4
R25610.0K
C72
0.001uf
R425 10K
R100DNI
C320 0.1uF
R427 DNI
J41
HEADER, 1x3-PIN
123
C242
2.2uF
R54722
R75 4.70K, 1%
R550 4.70K, 1%
C73
0.1uF
J17
Mictor38P
5VDC1
SCL2
GND3
SDA4
CLKE5
CLKO6
D15E7
D15O8
D14E9
D14O10
D13E11
D13O12
D12E13
D12O14
D11E15
D11O16
D10E17
D10O18
D9E19
D9O20
D8E21
D8O22
D7E23
D7O24
D6E25
D6O26
D5E27
D5O28
D4E29
D4O30
D3E31
D3O32
D2E33
D2O34
D1E35
D1O36
D0E37
D0O38
GND139
GND240
GND341
GND442
GND543
C243
0.1uF
R558 22
XJ8
881545-2
R2571.00K
J37HEADER, 1x3-PIN
123
R54022
XJ4
881545-2U67
TS5A23157
IN11
NO12
GND3
NO24
IN25
COM26
NC27
V+8
NC19
COM110
R1504.70K, 1%
R397 10.0K
R258 10.0KJ39HEADER, 1x3-PIN
123
XJ10
881545-2
R4060
R436 10.0K
J40
HEADER, 1x3-PIN
123
XJ12
881545-2
C849
39pF
R430 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Bank 8
Variable Voltage
FMC PORT A INTERFACE
Variable Voltage
Variable Voltage
Variable Voltage
FMC PORT B INTERFACEUSB FPGA INTERFACE
FMC_LA_RX_P0
FMC_LA_TX_P2
FMC_LA_TX_P3
FMC_LA_TX_P4
FMC_LA_TX_P5
FMC_LA_TX_N0FMC_LA_TX_N2
FMC_LA_TX_N3
FMC_LA_TX_N4
FMC_LA_TX_N5
FMC_LA_TX_P6
FMC_LA_TX_N6
FMC_LA_TX_P7
FMC_LA_TX_P9
FMC_LA_TX_P10
FMC_LA_TX_P12
FMC_LA_TX_P13
FMC_LA_TX_P14
FMC_LA_TX_P15
FMC_LA_TX_N7
FMC_LA_TX_N9FMC_LA_TX_N10
FMC_LA_TX_N12
FMC_LA_TX_N13
FMC_LA_TX_N14FMC_LA_TX_N15
FMC_LA_TX_CLK_P
FMC_LA_TX_CLK_N
FMC_LA_RX_P1
FMC_LA_TX_P0
FMC_LA_RX_P2
FMC_LA_RX_P3
FMC_LA_RX_P4
FMC_LA_RX_P5
FMC_LA_RX_P6
FMC_LA_RX_P8
FMC_LA_RX_P9
FMC_LA_RX_P10
FMC_LA_RX_P11
FMC_LA_RX_P12
FMC_LA_RX_P13
FMC_LA_RX_P14
FMC_LA_RX_P15
FMC_LA_RX_N0
FMC_LA_RX_N1
FMC_LA_RX_N2
FMC_LA_RX_N3
FMC_LA_RX_N4
FMC_LA_RX_N5
FMC_LA_RX_N6
FMC_LA_RX_N8
FMC_LA_RX_N9
FMC_LA_RX_N10
FMC_LA_RX_N11
FMC_LA_RX_N12
FMC_LA_RX_N13
FMC_LA_RX_N14
FMC_LA_RX_N15
FMC_LA_TX_P1
FMC_LA_TX_N1
FMC_GA0FMC_SDA
FMC_SCLFMC_LA_TX_P16
FMC_LA_TX_N16
FMC_PRSNTn
FMC_LA_TX_P17
FMC_LA_TX_N17
FMC_GPIO0FMC_GPIO1
FMC_GPIO2
FMC_GPIO3
FMC_GA1
FMC_GPIO4
FMC_GPIO5
FMC_GPIO6FMC_GPIO7
FMCB_LA_RX_N0FMCB_LA_RX_P0
FMCB_LA_RX_P1FMCB_LA_RX_N1
FMCB_LA_RX_P2FMCB_LA_RX_N2
FMCB_LA_RX_P3FMCB_LA_RX_N3
FMCB_LA_RX_N4FMCB_LA_RX_P4
FMCB_LA_RX_N5FMCB_LA_RX_P5
FMCB_LA_RX_N6FMCB_LA_RX_P6
FMCB_LA_RX_N8FMCB_LA_RX_P8
FMCB_LA_RX_N9FMCB_LA_RX_P9
FMCB_LA_RX_N10FMCB_LA_RX_P10
FMCB_LA_RX_N11FMCB_LA_RX_P11
FMCB_LA_RX_N12FMCB_LA_RX_P12
FMCB_LA_RX_N14FMCB_LA_RX_P14
FMCB_LA_RX_N15FMCB_LA_RX_P15
FMCB_LA_TX_N0FMCB_LA_TX_P0
FMCB_LA_TX_P1FMCB_LA_TX_N1
FMCB_LA_TX_N2FMCB_LA_TX_P2
FMCB_LA_TX_N3FMCB_LA_TX_P3
FMCB_LA_TX_P13
FMCB_LA_TX_N13FMCB_LA_TX_N14
FMCB_LA_TX_N15
FMCB_LA_TX_P14
FMCB_LA_TX_P15
FMCB_LA_TX_P4
FMCB_LA_TX_N4
FMCB_LA_TX_P5FMCB_LA_TX_N5
FMCB_LA_TX_P6FMCB_LA_TX_N6
FMCB_LA_TX_P7FMCB_LA_TX_N7
FMCB_LA_TX_N9
FMCB_LA_TX_P9
FMCB_LA_TX_P10
FMCB_LA_TX_N10
FMCB_LA_TX_P12
FMCB_LA_TX_N12
FMCB_LA_TX_P16
FMCB_LA_TX_N16
FMCB_GA0
FMCB_GA1
FMCB_LA_TX_CLK_P
FMCB_LA_TX_CLK_N
FMCB_GPIO0
FMCB_GPIO1
USB_FPGA_DATA0
USB_FPGA_DATA1
USB_FPGA_DATA2
USB_FPGA_DATA3
USB_FPGA_TXEn
USB_FPGA_RDnUSB_FPGA_WR
FMC_GA[1:0]24
FMC_LA_RX_P[15:0]10,24
FMC_LA_RX_N[15:0]10,24
FMC_LA_TX_P[17:0]24
FMC_LA_TX_N[17:0]24
FMC_LA_TX_CLK_N24
FMC_LA_TX_CLK_P24
FMC_PRSNTn24,28
FMC_SDA24
FMC_SCL24
FMC_GPIO[7:0]24
FMCB_GA[1:0]25
FMCB_LA_RX_P[15:0]10,25
FMCB_LA_RX_N[15:0]10,25
FMCB_LA_TX_P[17:0]10,25
FMCB_LA_TX_N[17:0]10,25
FMCB_LA_TX_CLK_N25
FMCB_LA_TX_CLK_P25
FMCB_GPIO[7:0]6,25
USB_FPGA_DATA[7..0]10,27
USB_FPGA_WR27
USB_FPGA_RDn27
USB_FPGA_TXEn27
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
8 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
8 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
8 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Bank 8C
Arria V SX (SoC) Bank 8
Bank 8D
U41Q
5ASTFD5K3_F1517
HMC_DM3,DIFFIO_TX_T74_PK27
HMC_DM4,DIFFIO_TX_T66_PJ26
HMC_DM5,DIFFIO_TX_T59_PK24
HMC_DQ3_0,DIFFIO_RX_T69_PP27
HMC_DQ3_1,DIFFIO_RX_T69_NR27
HMC_DQ3_2,DIFFIO_TX_T70_PH27
HMC_DQ3_3,DIFFIO_RX_T71_PB27
HMC_DQ3_4,DIFFIO_RX_T71_NC27
HMC_DQ3_5,DIFFIO_TX_T72_PE27
HMC_DQ3_6,DIFFIO_RX_T75_PM27
HMC_DQ3_7,DIFFIO_RX_T75_NN27
HMC_DQ3_8,DIFFIO_TX_T76_PN28
HMC_DQ4_0,DIFFIO_RX_T62_PC26
HMC_DQ4_1,DIFFIO_RX_T62_ND26
HMC_DQ4_2K25
HMC_DQ4_3,DIFFIO_RX_T63_PR26
HMC_DQ4_4,DIFFIO_RX_T63_NT27
HMC_DQ4_5,DIFFIO_TX_T64_PA26
HMC_DQ4_6,DIFFIO_RX_T67_PF26
HMC_DQ4_7,DIFFIO_RX_T67_NG26
HMC_DQ4_8,DIFFIO_TX_T68_PM25
HMC_DQ5_0,DIFFIO_RX_T54_PT26
HMC_DQ5_1,DIFFIO_RX_T54_NT25
HMC_DQ5_2,DIFFIO_TX_T55_PG25
HMC_DQ5_3,DIFFIO_RX_T56_PN24
HMC_DQ5_4,DIFFIO_RX_T56_NP24
HMC_DQ5_5,DIFFIO_TX_T57_PR24
HMC_DQ5_6,DIFFIO_RX_T60_PD25
HMC_DQ5_7,DIFFIO_RX_T60_NE25
HMC_DQ5_8,DIFFIO_TX_T61_PP25
HMC_DQS#3,HMC_RLD2_QK3,DIFFIO_RX_T73_NT28
HMC_DQS#4,HMC_RLD2_QK4,DIFFIO_RX_T65_NN26
HMC_DQS#5,HMC_RLD2_QK5,DIFFIO_RX_T58_NB25
HMC_DQS3,HMC_RLD2_QK#3,HMC_QDR2_CQ3/CQ#3,DIFFIO_RX_T73_PR28
HMC_DQS4,HMC_RLD2_QK#4,HMC_QDR2_CQ4/CQ#4,DIFFIO_RX_T65_PM26
HMC_DQS5,HMC_RLD2_QK#5,HMC_QDR2_CQ5/CQ#5,DIFFIO_RX_T58_PA25
DIFFIO_TX_T76_NP28DIFFIO_TX_T74_NL27DIFFIO_TX_T72_NF27DIFFIO_TX_T70_NJ27DIFFIO_TX_T68_NN25DIFFIO_TX_T66_NK26DIFFIO_TX_T64_NA27DIFFIO_TX_T61_NR25DIFFIO_TX_T59_NL24DIFFIO_TX_T57_NT24DIFFIO_TX_T55_NH25
DIFFIO_TX_T38_P,DQ1TR21 DIFFIO_TX_T34_P,DQ1TD21 DIFFIO_TX_T32_P,DQ1TN21
DIFFIO_TX_T45_P,DQ2TR22
DIFFIO_TX_T43_P,DQ2TL22 DIFFIO_TX_T41_P,DQ2TA23
DIFFIO_RX_T44_P,DQ2TN22
DIFFIO_RX_T44_N,DQ2TP22
DIFFIO_RX_T40_P,DQ2TE22
DIFFIO_RX_T40_N,DQ2TF22
DQ2TJ22
DIFFIO_TX_T53_P,DQ3TH24
DIFFIO_TX_T51_P,DQ3TJ23DIFFIO_TX_T49_P,DQ3TM23
DIFFIO_TX_T47_P,DQ3TR23
DIFFIO_RX_T52_P,DQ3TF24
DIFFIO_RX_T52_N,DQ3TG24
DIFFIO_RX_T48_P,DQ3TB24
DIFFIO_RX_T48_N,DQ3TC24
DIFFIO_RX_T46_P,DQ3TF23
DIFFIO_RX_T46_N,DQ3TG23DIFFIO_RX_T42_P,DQS2T
C23
DIFFIO_RX_T50_P,DQS3TD24
DIFFIO_RX_T42_N,DQSn2TD23
DIFFIO_RX_T50_N,DQSn3TE24
DIFFIO_TX_T53_NJ24DIFFIO_TX_T51_NK23DIFFIO_TX_T49_NN23DIFFIO_TX_T47_NT23
DIFFIO_TX_T45_NT22 DIFFIO_TX_T43_NM22 DIFFIO_TX_T41_NA24 DIFFIO_TX_T38_NT21 DIFFIO_TX_T34_NE21 DIFFIO_TX_T32_NP21
Arria V SX (SoC) Bank 8Bank 8A
Bank 8B
5ASTFD5K3_F1517
U41F
DIFFIO_TX_T112_NG32
HMC_DQ2_4,DIFFIO_RX_T79_ND28
HMC_DQ2_6,DIFFIO_RX_T83_PM29HMC_DQ2_5,DIFFIO_TX_T80_PF28
HMC_DM2,DIFFIO_TX_T82_PJ29
HMC_DQ2_7,DIFFIO_RX_T83_NN29
HMC_DQ2_8,DIFFIO_TX_T84_PF29
HMC_DQ1_0,DIFFIO_RX_T85_PB28 HMC_DQS#2,HMC_RLD2_QK2,DIFFIO_RX_T81_N
T29
HMC_DQ1_1,DIFFIO_RX_T85_NC29
HMC_DQS#1,HMC_RLD2_QK1,DIFFIO_RX_T88_NP30
HMC_DQ1_3,DIFFIO_RX_T86_PA29
HMC_DQS1,HMC_RLD2_QK#1,HMC_QDR2_CQ1/CQ#1,DIFFIO_RX_T88_PN30
HMC_DQ1_2R30
HMC_DQS2,HMC_RLD2_QK#2,HMC_QDR2_CQ2/CQ#2,DIFFIO_RX_T81_PR29
HMC_DQ1_4,DIFFIO_RX_T86_NA28
DIFFIO_TX_T89_NK30
HMC_DQ1_5,DIFFIO_TX_T87_PL30
HMC_RESET#,HMC_RLD2_A_19,DIFFIO_TX_T91_NG30
HMC_DQ1_7,DIFFIO_RX_T90_ND29
DIFFIO_TX_T87_NM30
HMC_DQ1_6,DIFFIO_RX_T90_PD30
DIFFIO_TX_T84_NG29
HMC_DQ1_8,DIFFIO_TX_T91_PF30
DIFFIO_TX_T80_NG28
HMC_DQ2_0,DIFFIO_RX_T77_PL28
DIFFIO_TX_T82_NK29
HMC_DQ2_2,DIFFIO_TX_T78_PH28
DIFFIO_TX_T78_NJ28
HMC_DQ2_1,DIFFIO_RX_T77_NM28
HMC_DQ2_3,DIFFIO_RX_T79_PC28
RZQ_6,DIFFIO_TX_T114_NF33
HMC_A_0,DIFFIO_RX_T94_PB31
HMC_A_1,DIFFIO_RX_T94_NA30
HMC_BA_0,DIFFIO_RX_T102_PM32
HMC_A_10,DIFFIO_TX_T99_PC32
HMC_BA_2,DIFFIO_TX_T103_PJ34
HMC_A_11,DIFFIO_TX_T99_ND32
HMC_BA_1,DIFFIO_RX_T102_NN32
HMC_A_13,DIFFIO_RX_T100_NP31
HMC_CAS#,HMC_RLD2_REF#,HMC_QDR2_WPS#,DIFFIO_RX_T104_PL33
HMC_CK#,DIFFIO_RX_T92_NC30
HMC_CKE_0,HMC_RLD2_A_16,DIFFIO_TX_T93_PE31
HMC_A_12,DIFFIO_RX_T100_PN31
HMC_CK,DIFFIO_RX_T92_PB30
HMC_A_14,DIFFIO_TX_T101_PJ32
HMC_CKE_1,HMC_RLD2_A_17,DIFFIO_TX_T93_NF31
HMC_A_15,DIFFIO_TX_T101_NK32
HMC_CS#_0,DIFFIO_TX_T107_PL34
HMC_A_3,DIFFIO_TX_T95_NA32
HMC_ODT_0,HMC_RLD2_A_18,DIFFIO_TX_T105_PL31
HMC_A_2,DIFFIO_TX_T95_PA31
HMC_CS#_1,DIFFIO_TX_T107_NM34
HMC_A_4,DIFFIO_RX_T96_PA33
HMC_ODT_1,HMC_RLD2_A_20,DIFFIO_TX_T105_NM31
HMC_A_5,DIFFIO_RX_T96_NB33
HMC_RAS#,HMC_RLD2_A_21,DIFFIO_TX_T103_NK34
HMC_A_6,DIFFIO_TX_T97_PH31
DIFFIO_TX_T114_P,DQ11TE33
HMC_A_7,DIFFIO_TX_T97_NJ31
HMC_WE#,HMC_RLD2_WE#,HMC_QDR2_RPS#,DIFFIO_RX_T104_NM33
HMC_A_9,DIFFIO_RX_T98_ND31
DIFFIO_TX_T112_P,DQ11TF32
HMC_A_8,DIFFIO_RX_T98_PC31
DQ11TJ33
HMC_DM1,DIFFIO_TX_T89_PJ30
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Transceivers
LVDS
From MAXV
SDI Reference Clocks
From FPGA
SMA ConnectorInterface
SMA Connector Interface
CAD Note:Place resistor near RREF_TL pins.Route away frm aggressor
CMU PLL (PCIe)
CAD Note:Place resistor near RREF_TL pins.Route away frm aggressor
RX
TX
Si571 Programmable OscillatorUse Clock Control GUI(Default 148.5MHz)I2C Address 55 HEX
CLK_148_CP
CLK_148_CN
SI571_VCONTROL
CLK_148_P
CLK_148_N
SMA_XCVR_RX_C_PSMA_XCVR_RX_C_NSMA_XCVR_RX_N
SMA_XCVR_RX_P
FMCB_DP_M2C_P2
FMCB_DP_M2C_P3
FMC_DP_M2C_P0
FMCB_DP_M2C_N2
FMCB_DP_M2C_N3
FMC_DP_M2C_N0FMC_DP_C2M_P0FMC_DP_C2M_N0
XCVR_RREF_BR
XCVR_RREF_TL
SMA_XCVR_RX_PSMA_XCVR_RX_N
SMA_XCVR_TX_PSMA_XCVR_TX_N
FMCB_DP_M2C_P0FMCB_DP_M2C_N0
FMCB_DP_M2C_N1FMCB_DP_M2C_P1
FMC_DP_M2C_P1FMC_DP_M2C_N1FMC_DP_M2C_P2FMC_DP_M2C_N2
FMC_DP_M2C_P3FMC_DP_M2C_N3
FMC_DP_M2C_P4FMC_DP_M2C_N4
FMC_DP_M2C_N5FMC_DP_M2C_P5
FMC_DP_M2C_N6FMC_DP_M2C_P6
FMC_DP_M2C_N7FMC_DP_M2C_P7
FMC_DP_C2M_P1FMC_DP_C2M_N1FMC_DP_C2M_P2FMC_DP_C2M_N2
FMC_DP_C2M_P3FMC_DP_C2M_N3
FMC_DP_C2M_P4FMC_DP_C2M_N4
FMC_DP_C2M_P5FMC_DP_C2M_N5FMC_DP_C2M_P6FMC_DP_C2M_N6
FMC_DP_C2M_P7FMC_DP_C2M_N7
FMCB_DP_C2M_P0FMCB_DP_C2M_N0
FMCB_DP_C2M_N1FMCB_DP_C2M_P1
FMCB_DP_C2M_N2FMCB_DP_C2M_P2
FMCB_DP_C2M_N3FMCB_DP_C2M_P3
CLK_148_PCLK_148_N
2.5V_REG_HPS
SI571_EN19
SDI_CLK148_UP4
SDI_CLK148_DN4
I2C_SDA_MAX11,19
I2C_SCL_MAX11,19
FMC_DP_M2C_P[7:0]24
FMC_DP_C2M_P[7:0]24
FMC_DP_C2M_N[7:0]24
FMC_DP_M2C_N[7:0]24
PCIE_TX_N0 3
PCIE_TX_P0 3
PCIE_TX_N1 3
PCIE_TX_P1 3
PCIE_TX_N2 3
PCIE_TX_P2 3
SFPA_TX_N 22
SFPA_TX_P 22
PCIE_RX_N03
PCIE_RX_N13
PCIE_RX_P13
PCIE_RX_N23
PCIE_RX_P23
PCIE_RX_P03
PCIE_REFCLK_QR0_P11PCIE_REFCLK_QR0_N11
SFPA_RX_N22
SFPA_RX_P22
REFCLK_QR2_P11REFCLK_QR2_N11
FMC_GBTCLK_M2C_P024FMC_GBTCLK_M2C_N024
FMC_GBTCLK_M2C_N124
FMC_GBTCLK_M2C_P124
SFPB_RX_P23SFPB_RX_N23
SFPB_TX_P 23SFPB_TX_N 23
PCIE_TX_N3 3
PCIE_TX_P3 3PCIE_RX_N33
PCIE_RX_P33
FMCB_GBTCLK_M2C_P025FMCB_GBTCLK_M2C_N025
FMCB_GBTCLK_M2C_N125
FMCB_GBTCLK_M2C_P125
FMCB_DP_M2C_P[3:0]25
FMCB_DP_C2M_P[3:0]25
FMCB_DP_C2M_N[3:0]25
FMCB_DP_M2C_N[3:0]25
LMK_SFPCLK_P12LMK_SFPCLK_N12
LMK_FMCCLK_P12LMK_FMCCLK_N12
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
9 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
9 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
9 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R575
2.00K
1%
C116 0.1uF
J311
2 3 4 5
C104 0.1uF
J321
2 3 4 5
C117
10uF
C114
0.1uF
R505
2.00K
1%
X3
Si571
OE2
VC1
GND3
CLK+4
CLK-5
VDD6
SDA7
SCL8
R126 180K
R593 10.0K
R129 4.99K
J251
2 3 4 5
Arria V SX (SoC) Transceiver - RightGXB_R0
GXB_R1
5ASTFD5K3_F1517
U41R
GXB_RX_R0p,GXB_REFCLK_R0pAU1
GXB_RX_R0n,GXB_REFCLK_R0nAU2
GXB_TX_R3nAK4GXB_TX_R3pAK3
GXB_TX_R4pAH3
GXB_TX_R4nAH4
GXB_TX_R2nAM4GXB_TX_R2pAM3
GXB_TX_R5pAF3
GXB_TX_R5nAF4
GXB_RX_R2n,GXB_REFCLK_R2nAN2 GXB_RX_R2p,GXB_REFCLK_R2pAN1
REFCLK0RpAF8
REFCLK0RnAF7
GXB_RX_R8n,GXB_REFCLK_R8nAA2 GXB_RX_R8p,GXB_REFCLK_R8pAA1
GXB_TX_R6pAD3
GXB_TX_R6nAD4
GXB_TX_R7nAB4GXB_TX_R7pAB3
GXB_RX_R10p,GXB_REFCLK_R10pU1
GXB_RX_R10n,GXB_REFCLK_R10nU2
GXB_TX_R8nY4GXB_TX_R8pY3
GXB_RX_R9n,GXB_REFCLK_R9nW2 GXB_RX_R9p,GXB_REFCLK_R9pW1
REFCLK2RpAB9
REFCLK2RnAB8
RREF_BRAW2
GXB_RX_R1p,GXB_REFCLK_R1pAR1
GXB_RX_R1n,GXB_REFCLK_R1nAR2
REFCLK1RnAD8 REFCLK1RpAD9
GXB_TX_R0pAT3
GXB_TX_R1nAP4
GXB_TX_R0nAT4
GXB_TX_R1pAP3
GXB_RX_R4p,GXB_REFCLK_R4pAJ1
GXB_RX_R5p,GXB_REFCLK_R5pAG1 GXB_RX_R4n,GXB_REFCLK_R4nAJ2
GXB_RX_R3p,GXB_REFCLK_R3pAL1
GXB_RX_R3n,GXB_REFCLK_R3nAL2
GXB_RX_R5n,GXB_REFCLK_R5nAG2
GXB_RX_R6n,GXB_REFCLK_R6nAE2
GXB_RX_R11n,GXB_REFCLK_R11nR2 GXB_RX_R11p,GXB_REFCLK_R11pR1
GXB_RX_R7p,GXB_REFCLK_R7pAC1
GXB_RX_R6p,GXB_REFCLK_R6pAE1
GXB_RX_R7n,GXB_REFCLK_R7nAC2
REFCLK3RpY9
REFCLK3RnY8
GXB_TX_R11pP3
GXB_TX_R11nP4
GXB_TX_R9pV3
GXB_TX_R10pT3GXB_TX_R9nV4
GXB_TX_R10nT4
C150 0.1uFC151 0.1uF
R127 4.99K
J241
2 3 4 5
C115 0.1uF
R120 10.0K
C112 1000pF
Arria V SX (SoC) Transceiver - LeftGXB_L0
GXB_L1
GXB_L2
5ASTFD5K3_F1517
U41M
GXB_RX_L0n,GXB_REFCLK_L0nAW36 GXB_RX_L0p,GXB_REFCLK_L0pAW37
GXB_TX_L1pAR37
GXB_TX_L1nAR36
GXB_TX_L2nAN36GXB_TX_L2pAN37
GXB_TX_L0pAU37
GXB_TX_L0nAU36
GXB_TX_L3nAL36GXB_TX_L3pAL37
GXB_RX_L2p,GXB_REFCLK_L2pAP39
GXB_RX_L2n,GXB_REFCLK_L2nAP38
GXB_TX_L4nAJ36GXB_TX_L4pAJ37
GXB_RX_L10p,GXB_REFCLK_L10pV39
GXB_RX_L10n,GXB_REFCLK_L10nV38
GXB_TX_L6nAE36GXB_TX_L6pAE37
GXB_TX_L7pAC37
GXB_TX_L7nAC36
GXB_RX_L6n,GXB_REFCLK_L6nAF38 GXB_RX_L6p,GXB_REFCLK_L6pAF39
GXB_TX_L8pAA37
GXB_TX_L8nAA36
GXB_TX_L12nN36GXB_TX_L12pN37
GXB_RX_L12n,GXB_REFCLK_L12nP38 GXB_RX_L12p,GXB_REFCLK_L12pP39
GXB_TX_L14pJ37
GXB_TX_L14nJ36
GXB_TX_L15pG37
GXB_TX_L15nG36
GXB_RX_L14n,GXB_REFCLK_L14nK38 GXB_RX_L14p,GXB_REFCLK_L14pK39
GXB_TX_L16pE37
GXB_TX_L16nE36
GXB_RX_L11p,GXB_REFCLK_L11pT39
GXB_RX_L11n,GXB_REFCLK_L11nT38
GXB_TX_L10nU36GXB_TX_L10pU37
GXB_RX_L13n,GXB_REFCLK_L13nM38 GXB_RX_L13p,GXB_REFCLK_L13pM39
RREF_TLB39
GXB_RX_L1n,GXB_REFCLK_L1nAT38 GXB_RX_L1p,GXB_REFCLK_L1pAT39
GXB_TX_L5pAG37
GXB_TX_L5nAG36
REFCLK0LnAG33
REFCLK1LpAE31
REFCLK0LpAG32
REFCLK1LnAE32
GXB_RX_L4n,GXB_REFCLK_L4nAK38
GXB_RX_L5n,GXB_REFCLK_L5nAH38
GXB_RX_L4p,GXB_REFCLK_L4pAK39 GXB_RX_L3n,GXB_REFCLK_L3nAM38 GXB_RX_L3p,GXB_REFCLK_L3pAM39
GXB_RX_L5p,GXB_REFCLK_L5pAH39
GXB_RX_L8p,GXB_REFCLK_L8pAB39
GXB_RX_L7p,GXB_REFCLK_L7pAD39
GXB_RX_L7n,GXB_REFCLK_L7nAD38
GXB_RX_L9n,GXB_REFCLK_L9nY38
GXB_RX_L8n,GXB_REFCLK_L8nAB38
GXB_RX_L9p,GXB_REFCLK_L9pY39
GXB_TX_L11nR36GXB_TX_L11pR37
REFCLK3LnAA32 REFCLK3LpAA31
GXB_TX_L9nW36
REFCLK2LnAC32
GXB_TX_L9pW37
REFCLK2LpAC31
GXB_TX_L13nL36GXB_TX_L13pL37
GXB_RX_L17p,GXB_REFCLK_L17pD39
GXB_RX_L15n,GXB_REFCLK_L15nH38
GXB_RX_L16p,GXB_REFCLK_L16pF39
GXB_RX_L15p,GXB_REFCLK_L15pH39
GXB_RX_L16n,GXB_REFCLK_L16nF38
GXB_RX_L17n,GXB_REFCLK_L17nD38 GXB_TX_L17p
C37
REFCLK5LnU32 REFCLK5LpU31
REFCLK4LpW31
GXB_TX_L17nC36
REFCLK4LnW32
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Clocks
1.5 Volt
2.5 Volt
2.5 Volt
Variable Voltage
Variable Voltage
Alt. DEVCLK
DEVCLKB
DEVCLKB
Alt. DEVCLK
FMC PORT B
FMCPORT A
CLK_ENET_FPGA_NCLK_ENET_FPGA_P
CLK_50M_FPGA
CLK_ENET_FPGA_PHY
CLK_BOT1
I2C_SDA_FPGAI2C_SCL_FPGA
FMC_CLK_M2C_P0FMC_CLK_M2C_N0
FMC_CLK_M2C_P1FMC_CLK_M2C_N1
CLK_TOP1
FMCB_CLK_M2C_P0FMCB_CLK_M2C_N0
FMCB_CLK_M2C_P1FMCB_CLK_M2C_N1
FMC_CLK_M2C_N1FMC_CLK_M2C_P1
FMC_CLK_M2C_P0 FMC_CLK_M2C_N0
FMC_LA_RX_CLK_NFMC_LA_RX_CLK_P
FMC_LA_RX_N7FMC_LA_RX_P7
FMCB_CLK_M2C_N1FMCB_CLK_M2C_P1
FMCB_CLK_M2C_P0 FMCB_CLK_M2C_N0
FMCB_LA_RX_CLK_NFMCB_LA_RX_CLK_P
FMCB_LA_RX_N7FMCB_LA_RX_P7
RCLOCK_OUT_NRCLOCK_OUT_P
SFPB_MOD1_SCLSFPB_MOD0_PRSNTn
USB_FPGA_DATA[7..0]
USB_FPGA_DATA4USB_FPGA_DATA5
USB_FPGA_DATA6USB_FPGA_DATA7
SMA_CLKIN
FMCB_LA_RX_P13FMCB_LA_RX_N13
CLK_100M_FPGA
FMC_LA_RX_CLK_N24
FMC_LA_RX_CLK_P24
FMC_LA_RX_N724
FMC_LA_RX_P724
CLK_ENET_FPGA_N 11
CLK_ENET_FPGA_P 11
CLK_50M_FPGA 11
CLK_ENET_FPGA_PHY11
PCIE_PRSNT2_X1 3PCIE_PRSNT2_X4 3
PCIE_PERSTn 3,13
I2C_SDA19,31,32
I2C_SCL19,31,32
CLK_BOT1 11
FMCB_CLK_M2C_P[1:0]25
FMCB_CLK_M2C_N[1:0]25
FMCB_LA_RX_N725
FMCB_LA_RX_P725
FMCB_LA_TX_P17 25FMCB_LA_TX_N17 25
FMCB_LA_RX_CLK_N25
FMCB_LA_RX_CLK_P25
CLK_TOP1 11
FMC_CLK_M2C_P[1:0]24
FMC_CLK_M2C_N[1:0]24
SPI_CLK19SPI_CSn19
SFPB_MOD2_SDA23
LMK_RESET19
LMK_CLEAN_CLK_P12LMK_CLEAN_CLK_N12 SFPB_LOS 23
LMK_SYSREF_P12LMK_SYSREF_N12
RCLOCK_OUT_N12
RCLOCK_OUT_P12
SFPB_MOD1_SCL23
SFPB_MOD0_PRSNTn23
USB_FPGA_DATA[7..0] 8,27
SFPB_TXFAULT23
FMCB_LA_RX_N1325
FMCB_LA_RX_P1325
SPI_SDIO19
CLK_100M_FPGA 11
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
10 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
10 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
10 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R35349.9
R533 100, 1%
R5910
R517 100, 1%
R513 100, 1%
Arria V SX (SoC) Clocks
Bank 3A
Bank 3D
Bank 4A
Bank 8A
Bank 8D
5ASTFD5K3_F1517
U41N
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUT_N,DIFFIO_TX_B5_NAL34FPLL_BL_CLKOUT0,FPLL_BL_CLKOUT_P,FPLL_BL_FB0,DIFFIO_TX_B5_P,DQ1BAM34
FPLL_BC_CLKOUT3,FPLL_BC_FBn,DIFFIO_RX_B80_N,DQSn11BAG21FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1,DIFFIO_RX_B80_P,DQS11BAH21
CLK7_P,DIFFIO_RX_B84_P,DQ11BAL20
FPLL_BC_CLKOUT1,FPLL_BC_CLKOUT_N,DIFFIO_TX_B79_NAD21FPLL_BC_CLKOUT0,FPLL_BC_CLKOUT_P,FPLL_BC_FB0,DIFFIO_TX_B79_P,DQ11BAC22
CLK6_P,DIFFIO_RX_B82_P,DQ11BAD20
CLK6_N,DIFFIO_RX_B82_N,DQ11BAC21
CLK9_P,DIFFIO_RX_B166_P,DQ22BAW4
CLK9_N,DIFFIO_RX_B166_N,DQ22BAV4
FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1,DIFFIO_RX_B6_P,DQ1BAK33
FPLL_BL_CLKOUT3,FPLL_BL_FBn,DIFFIO_RX_B6_N,DQ1BAJ33
CLK0_P,DIFFIO_RX_B2_P,DQ1BAP34
CLK0_N,DIFFIO_RX_B2_N,DQ1BAN34
CLK7_N,DIFFIO_RX_B84_N,DQ11BAK20
CLK8_P,DIFFIO_RX_B168_P,DQ22BAR6
CLK8_N,DIFFIO_RX_B168_N,DQ22BAP6
CLK2_N,DIFFIO_RX_B7_N,DQ1BAL33
CLK3_P,DIFFIO_RX_B9_P,DQ2BAU32
CLK3_N,DIFFIO_RX_B9_N,DQ2BAT32
CLK2_P,DIFFIO_RX_B7_P,DQ1BAM33
CLK1_N,DIFFIO_RX_B4_N,DQSn1BAJ34 CLK1_P,DIFFIO_RX_B4_P,DQS1BAK34
CLK5_P,DIFFIO_RX_B78_P,DQ11BAF21
CLK4_N,DIFFIO_RX_B76_N,DQ10BAU19 CLK4_P,DIFFIO_RX_B76_P,DQ10BAV19
CLK5_N,DIFFIO_RX_B78_N,DQ11BAE21
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUT_N,DIFFIO_TX_B161_NAL7
FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1,DIFFIO_RX_B162_P,DQ22BAP8
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUT_P,FPLL_BR_FB0,DIFFIO_TX_B161_P,DQ22BAM7
FPLL_BR_CLKOUT3,FPLL_BR_FBn,DIFFIO_RX_B162_N,DQ22BAN8
CLK10_P,DIFFIO_RX_B164_P,DQS22BAT7
CLK11_N,DIFFIO_RX_B160_N,DQ21BAJ7
CLK10_N,DIFFIO_RX_B164_N,DQSn22BAR7
CLK11_P,DIFFIO_RX_B160_P,DQ21BAK7
CLK22_P,DIFFIO_RX_T108_P,DQ11TE34
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUT_P,FPLL_TL_FB0,DIFFIO_TX_T110_P,DQ11TC33
CLK23_N,DIFFIO_RX_T106_N,DQ10TN33 FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1,DIFFIO_RX_T109_P,DQ11T
B34
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUT_N,DIFFIO_TX_T110_ND33
CLK22_N,DIFFIO_RX_T108_N,DQ11TF34
FPLL_TL_CLKOUT3,FPLL_TL_FBn,DIFFIO_RX_T109_N,DQ11TA35CLK23_P,DIFFIO_RX_T106_P,DQ10T
N34
CLK21_P,DIFFIO_RX_T111_P,DQS11TG34
CLK21_N,DIFFIO_RX_T111_N,DQSn11TH34
CLK20_N,DIFFIO_RX_T113_N,DQ11TD34 CLK20_P,DIFFIO_RX_T113_P,DQ11TC34
CLK18_P,DIFFIO_RX_T33_P,DQ1TH21
FPLL_TC_CLKOUT0,FPLL_TC_CLKOUT_P,FPLL_TC_FB0,DIFFIO_TX_T36_P,DQ1TK21
FPLL_TC_CLKOUT1,FPLL_TC_CLKOUT_N,DIFFIO_TX_T36_NL21
FPLL_TC_CLKOUT3,FPLL_TC_FBn,DIFFIO_RX_T35_N,DQSn1TB21
CLK18_N,DIFFIO_RX_T33_N,DQ1TJ21
CLK19_P,DIFFIO_RX_T31_P,DQ1TC20
CLK19_N,DIFFIO_RX_T31_N,DQ1TD20 FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1,DIFFIO_RX_T35_P,DQS1T
A20
CLK16_P,DIFFIO_RX_T39_P,DQ2TB22
CLK17_N,DIFFIO_RX_T37_N,DQ1TA21 CLK17_P,DIFFIO_RX_T37_P,DQ1TA22
CLK16_N,DIFFIO_RX_T39_N,DQ2TC22
R514 100, 1%
R537 100, 1%
R532 100, 1%
J151
2345
R5920
R536 100, 1%
R512 100, 1%
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Si570 Programmable OscillatorUse Clock Control GUI(Default 100MHz)I2C Address 66 HEX
PLL
OSC1_CLK_SEL = HIGH selects (OSC1_CLK_SMA) SMA inputOSC1_CLK_SEL = LOW selects (OSC1_CLK_SYN) Si5356A input
CMOS
Si5358 Programmable Oscillator Use Clock Control GUI (Defaults 156.25MHz,156.25MHz,25MHz,25MHz, 25MHz, 25MHz,100MHz, 100MHz)I2C Address 70 HEX
25Mhz
25Mhz
100MHz
156.25MHz
25Mhz
25Mhz
100Mhz
100Mhz
I2C_SDA_MAXI2C_SCL_MAX
REFCLK_QR2_C_N
REFCLK_QR2_C_P
SI570_EN
OSC2_CLK_SYN
OSC2_CLK_SMA
2.5V_CLK_MUX
CLKIN_50
CLK125A_EN
CLK125A_EN
OSC2_CLK_SEL0
CLK_DIFF1_N
CLK_DIFF1_P
CLK_DIFF2_N
CLK_DIFF2_P
PCIE_REFCLK_SYN_N
PCIE_REFCLK_SYN_P
PCIE_REFCLK_QR0_N
PCIE_REFCLK_QR0_P
OSC2_CLK_SEL0OSC2_CLK_SEL1
OSC2_CLK_SEL1
OSC2_HPS_CLK
OSC2_HPS_CLK
3.3V_VCXO
3.3V
2.5V_REG_HPS
1V81V8
1V8
1V8
2.5V_PLL1
2.5V_PLL1
2.5V_PLL12.5V_PLL1
2.5V_REG_HPS
2.5V_REG_HPS
1V8
1V8
1V8
1V8_PLL
1V8_PLL
2.5V_REG_HPS2.5V_REG_HPS
1V8
2.5V_REG_HPS
2.5V_REG_HPS
1V8 2.5V_REG_HPS
2.5V_REG_HPS
2.5V_PLL1
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
3.3V
SI570_EN14,19
REFCLK_QR2_N 9
REFCLK_QR2_P 9
CLK_BOT1 10
CLK_TOP1 10
CLK_OSC1 7
CLK50_EN19
CLK_50M_FPGA 10
CLK_50M_MAX 19
CLK_ENET_FPGA_P 10
CLK_ENET_FPGA_N 10
I2C_SDA_MAX9,11,19
I2C_SCL_MAX9,11,19
CLK125A_EN 14,19
PCIE_REFCLK_SYN_N 3
PCIE_REFCLK_SYN_P 3
PCIE_REFCLK_QR0_P 9
PCIE_REFCLK_QR0_N 9
I2C_SCL_MAX9,11,19
I2C_SDA_MAX9,11,19
CLK_DUAL_ENET_PHY 21
CLK_ENET_FPGA_PHY 10
CLK_100M_FPGA 10
CLK_100M_MAX 19
CLK_OSC2 7
CP112
VCXO 12
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
11 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
11 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
11 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R2850
C375
0.1uF
PLL
U59
Si52112
VSS25
DIFF16
DIFF28
DIFF29
XIN/CLKIN3
XOUT2
VDD1
VSS4
DIFF17
VDD210
R84 1.00K
C143
0.1uF
C423
0.1uF
R2890
R78 DNI
R86 100, 1%
U62
ICS83054I
CLK110
SEL17
Q1
NC26
NC311
VD
DQ
16
CLK28
CLK34
NC12
GN
D5
VD
D12
NC515
CLK014
OE3
SEL09
NC413
C834
0.1uF
R130 22
C63 0.1uF
C161
0.1uF
C310
2.2uF
L35
742792780
C56
0.1uF
C448
0.1uF
C383
0.1uF
R131 10.0K
C166
0.1uF
C145
0.1uF
L30
3A, 30 Ohm FB
Y6
OSC_33MHZ
EN1
VDD4
OUT3
GND2
R147 DNI
J46
CON2
12
C133
0.1uF
C127 DNI
C390
0.1uF
C424
0.1uF
TP8
C2610.01uF
L41
742792780
R146DNI
X4
50MHz
VCC4
GND2
OUT3
EN1
C130
0.1uF
R149 1.00K
C160
0.1uF
C144
0.1uF
Y5
25.00MHz
13
24
R2931.00K
J45
CON2
12
R311DNI
U42
Si5335
XA_CLKIN1
XB_CLKINB2
P33
GND4
P55
P66
VDD7VDD24
VDDO311VDDO215VDDO116VDDO020
LOS8
CLK3B9CLK3A10
P112
CLK2B13CLK2A14
CLK1B17CLK1A18
P219
CLK0B21CLK0A22
RSVD_GND23
EPAD25
C162
0.1uF
C244
0.1uF
C315
0.1uF
C156
0.1uF
Y4
25.00MHz
13
24
R2921.00K
L14
742792780
C374
2.2uF
R132 22
R284
DNI
C167
0.1uF
R503 1.00K
Y3
25.00MHz
13
24
C64 0.1uF
R148 DNI
C152 DNI
C238 DNI
C840
0.1uF
R681 22
C124
0.1uF
X2
SI570
OE2
NC1
GND3
CLK+4
CLK-5
VCC6
SDA7
SCL8
R2900
C237 DNIR2830
R85 DNI
C55
2.2uF
C388
10uF
C240
2.2uF
C153 DNI
C123
0.1uF
R286DNI
Y2
122.88 MHz
VC1
GND2
VDD4
OUT3
C449
0.1uF
X5
125.0MHz
EN1
NC2
GND3
OUT4
OUTn5
VCC6
C132 DNI
C382
0.1uF
U35
Si5338A-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
J49
SMA1
2345
U30
SL18860DC
CLKIN3 CLKOUT1
8
CLKOUT29
GND1
CLKOUT310
VDD2
OE16
OE_OSC4
OE27
OE35
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FROM FPGA RX_CLK
CMOS INPUT -> LVPECL OUTPUT
3.3V_VCC1_5_6
3.3V_VCC7
3.3V_VCC9
3.3V_VCC3
3.3V_VCC8_10
3.3V_VCC4
3.3V_VCC113.3V_VCC12
3.3V_VCC2
CLK_CLN_IN_C_PCLK_CLN_IN_C_N
SPI_CSn
LMK_RESET
SPI_SDIO
OSC_IN_POSC_IN_N
MUX_OSC_IN_P
MUX_OSC_IN_N
LMK_SYNC_IN
CP2
3.3V_MUX
LO_SMA
LMK_OSC_SEL
LMK_CLK_P
LMK_CLK_N
LMK_SDCLK_N
LMK_SDCLK_P
SPI_CLK
LMK_CLK_IN_NLMK_CLK_IN_P
MUX_OSC_IN_NMUX_OSC_IN_P
LMK_OSC_SEL
OSC_IN_C_P
OSC_IN_C_N
LMKR_CLK_FMC_PLMKR_CLK_FMC_N
LMKR_SYSREF_FMC_PLMKR_SYSREF_FMC_N
LMKR_CLK_FMCB_PLMKR_CLK_FMCB_N
LMKR_SYSREF_FMCB_PLMKR_SYSREF_FMCB_N
SMA_LMK_CLK_IN
LMK_SFPCLK_C_PLMK_SFPCLK_C_N
2.0V_VTD
LMK_FMCCLK_C_NLMK_FMCCLK_C_P
3.3V
3.3V
2.5V_REG_HPS
3.3V
SPI_CSn19
RCLOCK_OUT_P10
RCLOCK_OUT_N10
SPI_CLK19SPI_SDIO19
LMK_RESET19
LMK_SYSREF_FMC_P 24LMK_SYSREF_FMC_N 24
LMK_SYSREF_FMCB_P 25LMK_SYSREF_FMCB_N 25
LMK_CLK_FMC_P 24LMK_CLK_FMC_N 24
LMK_CLK_FMCB_P 25LMK_CLK_FMCB_N 25
CP1 11
VCXO11
LMK_SFPCLK_P 9LMK_SFPCLK_N 9
LMK_SYSREF_N 10
LMK_SYSREF_P 10
LMK_CLEAN_CLK_N 10
LMK_CLEAN_CLK_P 10
LMK_FMCCLK_P 9LMK_FMCCLK_N 9
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
12 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
12 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
12 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R48 0
U5LMK04828
CLKIN0p37
CLKIN0n38
CLKIN1p/FBCLKINp/FINp34
CLKIN1n/FBCLKINn/FINn35
OSCINp43
OSCINn44
SDIO20 SCK19
RESET5
CLKin_SEL058
CLKin_SEL159
SYNC6
VCC1_VCO10
VCC2_GC117
DAP65
CS18
VCC3_SYSREF21
VCC4_CG226
VCC5_DIG33
VCC6_PLL136
VCC7_OSCout39
VCC8_OSCin42
VCC9_CP245
VCC10_PLL247
VCC11_CG353
VCC12_CG064
DCLKOUT0p1
DCLKOUT0n2
SDCLKOUT1p3
SDCLKOUT1n4
DCLKOUT2p15
DCLKOUT2n16
SDCLKOUT3p13
SDCLKOUT3n14
DCLKOUT4p24
DCLKOUT4n25
SDCLKOUT5p22
SDCLKOUT5n23
DCLKOUT6p27
DCLKOUT6n28
STATUS_LD131
STATUS_LD248
OSCOUTp40
OSCOUTn41
SDCLKOUT7n30
DCLKOUT8p51
DCLKOUT8n52
SDCLKOUT9p49
SDCLKOUT9n50
DCLKOUT10p54
DCLKOUT10n55
SDCLKOUT7p29
SDCLKOUT11p56
SDCLKOUT11n57
CPOUT132
CPOUT246
LDObyp111
LDObyp212
DCLKOUT12p62
DCLKOUT12n63
SDCLKOUT13p60
SDCLKOUT13n61
C28
1uF
C30
0.1uF
C34
0.1uF
R338 820,1%
L1
742792780
C295
0.01uF
R36 0
C1447pF
R1549.9
C21 0.1uF
L8
3A, 30 Ohm FB
L6
3A, 30 Ohm FB
R357
DNI
C3 0.1uF
R35 0
U3
NB6L72MNG
SEL18
VCC13
D0n3 D0p2
GND16
VTD04
Q0p15
Q0n14
D1p6
D1n7
VTD15
GND_PAD17SEL0
1
Q1n10Q1p11
VCC12
GND9
C31
0.01uF
D4 Green_LED
J7
CON2
12
R1649.9
C46
0.1uF
J161
2 3 4 5
R59 1K
C296
0.01uF
C4 0.1uF
L4
3A, 30 Ohm FB
R356
DNI
R337 820,1%
R30 0
L5
3A, 30 Ohm FB
R355
DNI
C293
0.01uF
R111.00K
R29 0
D1 Green_LED
L2
3A, 30 Ohm FB
R13 100, 1%
C153900pF
C313
0.01uF
C17 0.1uF
R12620
C314
0.01uF
C16 0.1uF
J12
1
2 3 4 5
C47
10uF 25V
J21
2345
J91
2 3 4 5
J81
2345
R66 1K
L3
3A, 30 Ohm FB
C309
0.01uF
C120.1uF
R6
240
R14 100, 1%
R2839K
XJ13
881545-2
C25
0.1uF
R354
DNI
J10
1
2 3 4 5
C41 0.1uF
R7
240
R340 820,1%
R58 10K
L28
3A, 30 Ohm FB
C42 0.1uF
C27 0.1uF
J111
2 3 4 5
C5
0.1uF
D2 Green_LED
R47 0
C23
0.01uF
L29
3A, 30 Ohm FB
R23 1.96K
R61 10K
C19 0.1uF
C33 0.1uF
C6
0.1uF
C20 0.1uF
R34 0
C13
0.1uF
R339 820,1%
C24
0.01uF
R24 3.01K
C18 0.1uF
C45
1uF
R49 0
C350.68uF
C294
0.01uF
D3 Green_LED
C8
0.01uF
C26
0.1uF
C29
0.1uF
L7
3A, 30 Ohm FB
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria V ST Configuration
1.5 Volt
2.5 Volt
1.5 Volt
Logic 0 = pin 10 <--> pin 9 (MAX II Bypass)Logic 1 = pin 10 <--> pin 2 (MAX II Enable)
1 0
1 0
Logic 0 = pin 6 <--> pin 7 (FMC Bypass)Logic 1 = pin 6 <--> pin 4 (FMC Enable)
Logic 0 = pin 10 <--> pin 9 (FMC Bypass)Logic 1 = pin 10 <--> pin 2 (FMC Enable)
MSEL0MSEL1MSEL2MSEL3MSEL4
FPGA_DCLK
FPGA_nCONFIG
JTAG_FPGA_TDI
FPGA_nSTATUS
FPGA_CONF_DONE
MAX_FPGA_MOSI
FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14FPGA_CONFIG_D15
FPGA_CONFIG_D7
FPGA_CONFIG_D0FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5FPGA_CONFIG_D6
MAX_FPGA_SCKMAX_FPGA_SSEL
MAX_FPGA_MISO
FMCB_JTAG_EN
FMCB_JTAG_EN
BP_FMCB_TMS
MAX
FMCB_JTAG_EN
JTAG_MUX_TMS
FMCB_JTAG_TDOFMCB_JTAG_TDI
BP_FMCB_TMSFMCB_JTAG_TMSFMCB_JTAG_TMS
MAXMAX
2.5V_REG_FPGA
2.5V_REG_FPGA
2.5V_REG_FPGA
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
FPGA_PR_REQUEST 19
FPGA_PR_DONE 19
FPGA_PR_READY 19FPGA_PR_ERROR 19
FPGA_CvP_CONFDONE 19
JTAG_MUX_TCK14,19,24,25JTAG_FPGA_TDI14
JTAG_FPGA_TDO14
JTAG_FPGA_TMS14
FPGA_DCLK18,19
FPGA_nCONFIG19
FPGA_CONF_DONE19
FPGA_nSTATUS19
MAX_FPGA_MOSI 19
FPGA_CONFIG_D[15:0]18,19
MSEL0 19MSEL1 19MSEL2 19MSEL3 19MSEL4 19
PCIE_PERSTn 3,10
PCIE_WAKEn 3
MAX_FPGA_SSEL19
MAX_FPGA_SCK19MAX_FPGA_MISO 19
CPU_RESETn19,28
JTAG_MAX_TDI 14,19
FMCB_JTAG_TDO25
FMCB_JTAG_TMS 25
JTAG_MUX_TMS14
FMCB_JTAG_TDI14,25
USB_FPGA_RXFn27
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
13 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
13 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
13 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R4
91
10K
R4
89
10K
R171.00K
R30
R4
92
10K
C389 DNI
R497
DNI
R511 10K
R518 10K
R8 DNI
R515 10K
U1
TS5A23157
IN11
NO12
GND3
NO24
IN25
COM26
NC27
V+8
NC19
COM110
C291 0.1uF R1 DNI
OPEN
SW3
TDA06H0SB1
123456 7
89101112
R418 1.00KR419 1.00K
J3
CON2
12
R415 1.00K
R498 DNI
R10 1.00K
R416 1.00K
R4
90
10K
XJ14
881545-2
R507 10K
R9 DNI
Arria V SX (SoC) Configuration
Bank 3A
Bank 4A
Bank 8A
5ASTFD5K3_F1517
U41G
PR_REQUEST,DIFFIO_RX_B155_P,DQ21BAE11
DATA6,DIFFIO_TX_B148_P,DQ20BAV6
CRC_ERROR,DIFFIO_RX_B157_P,DQS21BAJ6
PR_ERROR,DIFFIO_TX_B154_NAH10
nPERSTR0,DIFFIO_TX_B156_NAK6
AS_DATA3,DATA3AU34
TDOAT34
DEV_CLRn,DIFFIO_TX_B158_P,DQ21BAJ9
AS_DATA0,ASDO,DATA0AV33
TMSAM35
AS_DATA1,DATA1AU33
MSEL2D35
MSEL0H35
INIT_DONE,DIFFIO_RX_B159_N,DQ21BAM6
nCONFIGA36
DATA9,DIFFIO_TX_B152_NAN9
DATA5,DIFFIO_RX_B147_P,DQ20BAW8
DATA7,DIFFIO_TX_B150_NAK9
DATA8,DIFFIO_TX_B150_P,DQ20BAK10
nCSO,DATA4AR34
DEV_OE,DIFFIO_TX_B158_NAH9
nCEM35
nCEO,DIFFIO_RX_B159_P,DQ21BAN6
MSEL4P34CONF_DONE
K35
CvP_CONFDONE,DIFFIO_RX_B157_N,DQSn21BAH6
nPERSTL0,DIFFIO_TX_B156_P,DQ21BAL6
MSEL3A37
PR_DONE,DIFFIO_RX_B155_N,DQ21BAF10
TDIAT33
AS_DATA2,DATA2AR33
TCKAV34
DCLKAW34
DATA10,DIFFIO_TX_B146_P,DQ20BAM9
DATA11,DIFFIO_RX_B147_N,DQ20BAW7
DATA12,DIFFIO_RX_B149_N,DQSn20BAW6
DATA13,DIFFIO_RX_B149_P,DQS20BAW5
DATA14,DIFFIO_RX_B151_N,DQ20BAU7
DATA15,DIFFIO_RX_B151_P,DQ20BAU8
CLKUSR,DIFFIO_TX_B152_P,DQ20BAP9
PR_READY,DIFFIO_TX_B154_P,DQ21BAJ10
nSTATUSF35 MSEL1
A34
R2 DNI
R417 1.00K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
JTAG(uses JTAG mode only)
USB Blaster Programming Header
JTAG Chain Control
ON = not-in-chainOFF = in-chain
TS5A23157 Switch FunctionsWhen Pins 1 & 5 are:LOW --> NC to/from COM = ON and NO to/from COM = OFFHIGH --> NC to/from COM = OFF and NO to/from COM = ON
Logic 0 = pin 10 <--> pin 9 (HPS Bypass)Logic 1 = pin 10 <--> pin 2 (HPS Enable)
Logic 0 = pin 6 <--> pin 7 (HPS Bypass)Logic 1 = pin 6 <--> pin 4 (HPS Enable)
Logic 0 = pin 10 <--> pin 9 (FMC Bypass)Logic 1 = pin 10 <--> pin 2 (FMC Enable)
Logic 0 = pin 6 <--> pin 7 (FMC Bypass)Logic 1 = pin 6 <--> pin 4 (FMC Enable)
Logic 0 = pin 10 <--> pin 9 (FPGA Bypass)Logic 1 = pin 10 <--> pin 2 (FPGA Enable)
Logic 0 = pin 6 <--> pin 7 (FPGA Bypass)Logic 1 = pin 6 <--> pin 4 (FPGA Enable)
Populate R183 if you would like toMaster the JTAG chain throughFMC
Logic 0 = pin 6 <--> pin 7 (HSMBBypass)Logic 1 = pin 6 <--> pin 4 (HSMB Enable)
Logic 0 = pin 10 <--> pin 9 (MAX II Bypass)Logic 1 = pin 10 <--> pin 2 (MAX II Enable)
1 0
1 0
1 0
1 0
1 0
1 0
JTAG_BLASTER_TDI
FMC_JTAG_EN
HPS_JTAG_ENFPGA_JTAG_EN
MAX_JTAG_EN
FMC_JTAG_TDI
BP_FPGA_TMS
BP_HPS_TMS
BP_FMC_TMS
JTAG_BLASTER_TDO JTAG_BLASTER_TDI
SI570_ENFACTORY_LOAD
CLK125A_EN
SECURITY_MODE
JTAG_SELJTAG_MICTOR_TDO
JTAG_MICTOR_TDI
FMC_JTAG_EN
HPS_JTAG_EN
FPGA_JTAG_EN
MAX_JTAG_EN
HPS_JTAG_EN
FPGA_JTAG_EN
FMC_JTAG_EN
BP_MAX_TMS
MAX_JTAG_EN
JTAG_MUX_TMS
JTAG_MUX_TMS
JTAG_MUX_TMS
JTAG_MUX_TMS
JTAG_MUX_TDO
JTAG_MUX_TCK
JTAG_HPS_SEL
JTAG_MUX_TMS
JTAG_FPGA_TDI
JTAG_MUX_HPS_TDI
JTAG_BLASTER_TDO
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_TCK
JTAG_MICTOR_TCK
JTAG_MICTOR_TMS
JTAG_MUX_TDO
JTAG_MUX_TDI
JTAG_MUX_TMS
JTAG_MUX_TCK
JTAG_MICTOR_TCK
JTAG_MICTOR_TMS
JTAG_MICTOR_TDO
JTAG_MICTOR_TDI
JTAG_MUX_TCKJTAG_MICTOR_TCK
JTAG_HPS_TCKJTAG_HPS_TCK
JTAG_MUX_TMSJTAG_MICTOR_TMS
JTAG_HPS_TMSJTAG_HPS_TMS
JTAG_MUX_HPS_TDIJTAG_MICTOR_TDO
JTAG_HPS_TDIJTAG_HPS_TDI
JTAG_FPGA_TDIJTAG_MICTOR_TDI
JTAG_HPS_TDOJTAG_HPS_TDO
JTAG_MICTOR_TDO
JTAG_MICTOR_TDI
JTAG_BLASTER_TDO
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_TCKJTAG_MICTOR_TCK
JTAG_MICTOR_TMS
JTAG_MUX_TCKJTAG_MUX_TCK
JTAG_MUX_TMSJTAG_MUX_TMS
JTAG_MUX_TDIJTAG_MUX_TDI
JTAG_MUX_TDOJTAG_MUX_TDO
JTAG_MAX_TDO
JTAG_MUX_TMS
JTAG_MUX_TMS
FMC_JTAG_TDO
JTAG_MUX_TMS
JTAG_FPGA_TDOJTAG_FPGA_TDI
FMC_JTAG_TDI
JTAG_MAX_TDI
BP_MAX_TMS
BP_FMC_TMS
BP_FPGA_TMS
BP_HPS_TMS
JTAG_MUX_TDOJTAG_MUX_TDO
JTAG_HPS_TMS
JTAG_FPGA_TMSJTAG_FPGA_TMS
FMC_JTAG_TMSFMC_JTAG_TMS
JTAG_MAX_TMSJTAG_MAX_TMS
JTAG_MUX_HPS_TDI HPS FPGA
FMC
FMCB
MUX
FPGA
FMC
FMCBHPS
MUXFMC
FMCB
MUX
FACTORY_LOADSECURITY_MODE
CLK125A_ENSI570_EN
JTAG_SEL
JTAG_HPS_SEL
JTAG_HPS_SEL
JTAG_SEL
1V8
3.3V
3.3V
2.5V_REG_HPS2.5V_REG_HPS 2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
2.5V_REG_HPS
3.3V
3.3V
3.3V
3.3V
JTAG_TCK 14,30
JTAG_TMS 14,30
JTAG_BLASTER_TDO 14,30
FMC_JTAG_TDO24
FMC_JTAG_TMS 24
JTAG_FPGA_TMS 13
JTAG_FPGA_TDO13
JTAG_HPS_TMS 7,14
USB_DISABLEn30
JTAG_MICTOR_TDO 7,14
JTAG_MICTOR_TDI 7,14
JTAG_MAX_TDO19
JTAG_MAX_TMS 19
JTAG_MUX_TCK13,14,19,24,25
JTAG_HPS_TDO 7
JTAG_HPS_TDI 7
JTAG_MUX_TMS 14
JTAG_TCK 14,30
JTAG_MICTOR_TCK 7,14
JTAG_TMS 14,30
JTAG_MICTOR_TMS 7,14
JTAG_BLASTER_TDI 30
JTAG_BLASTER_TDO 14,30
JTAG_MUX_TDI14
JTAG_MUX_TMS14
JTAG_MUX_TCK13,14,19,24,25
JTAG_HPS_TCK 7
JTAG_HPS_TMS 7,14
JTAG_FPGA_TDI 13,14
JTAG_MICTOR_TCK 7,14
JTAG_MICTOR_TMS 7,14
JTAG_MICTOR_TDO 7,14
JTAG_MICTOR_TDI 7,14
JTAG_FPGA_TDI 13,14
JTAG_FPGA_TDI 13,14
FMC_JTAG_TDI 24
FMCB_JTAG_TDI 19
JTAG_MUX_TDI 14
MICTOR_RSTn 7,19,26
JTAG_TRST 7,19
FACTORY_LOAD 19SECURITY_MODE 19
CLK125A_EN 11,19SI570_EN 11,19
JTAG_MAX_TDI 13,19
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
14 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
14 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
14 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
J35
JTAG_SMD
2468
10
13579
C333 0.1uF
R473 DNI
R960
U18
TS5A23157
IN11
NO12
GND3
NO24
IN25
COM26
NC27
V+8
NC19
COM110
R450 DNI
R465 DNI
R644 1.00K
J19
CON2
12
R445 DNI
R920
R421 1.00K
R668 1.00K
R447 DNI
XJ5
881545-2
R440 DNI
R463 DNI
R99 1.00K
R422 1.00K
OPEN
SW4
TDA04H0SB1
1234 5
678
J21
CON2
12
R405 10.0K
R459 DNI
R464 DNI
XJ6
881545-2
R474 DNI
R413 10.0K
R439 DNI
R655 1.00K
C335 0.1uF
U24
IDTQS3VH257
I0A2
I0B5
I1A3
I0C11
I1B6
I1C10
I0D14
I1D13
YA4
YB7
YC9
YD12
S1
E15
GND8
VCC16
U23
IDTQS3VH257
I0A2
I0B5
I1A3
I0C11
I1B6
I1C10
I0D14
I1D13
YA4
YB7
YC9
YD12
S1
E15
GND8
VCC16
C334 0.1uF
R1110
R95 1.00K
R453 DNI
R93 1.00K
R458 DNI
U17
TS5A23157
IN11
NO12
GND3
NO24
IN25
COM26
NC27
V+8
NC19
COM110
R444 DNI
R471 DNI
R396 10.0K
R446 DNI
C93
0.1uF
R97 1.00K
U15
TS5A23157
IN11
NO12
GND3
NO24
IN25
COM26
NC27
V+8
NC19
COM110
R476 DNI
R6540
R423 1.00K
R449 DNI
R451 DNI
R472 DNI
R470 DNI
OPEN
SW2
TDA04H0SB1
12345
678
U16
TS5A23157
IN11
NO12
GND3
NO24
IN25
COM26
NC27
V+8
NC19
COM110
R448 DNI
C92
2.2uF
R940
R667 DNI
R404 10.0K
R437 DNI
R443 DNI
C332 0.1uF
R114 1.00K
R980
R452 DNI
R462 DNI
R469 DNI
C91
0.1uF
R460 DNI
R420 1.00K
R475 DNI
C90
2.2uF
R113 1.00K
R461 DNI
R438 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1024MB DDR3 (x32 + ECC) - HPS
DDR3 ECC TEST
Place at end of branchPlace at end of branch
DDR3_HPS_CLK_P DDR3_HPS_CLK_N
DDR3_HPS_DQS_P4DDR3_HPS_DQS_N4
DDR3_HPS_DM4
DDR3_HPS_ZQ1
DDR3_HPS_CLK_P
DDR3_HPS_CSnDDR3_HPS_WEnDDR3_HPS_RASnDDR3_HPS_CASn
DDR3_HPS_RESETnDDR3_HPS_ODT
DDR3_HPS_BA2
DDR3_HPS_CKE
DDR3_HPS_BA1
DDR3_HPS_CLK_N
DDR3_HPS_BA0
DDR3_HPS_A13
DDR3_HPS_A5
DDR3_HPS_A1
DDR3_HPS_A6
DDR3_HPS_A11
DDR3_HPS_A0
DDR3_HPS_A7
DDR3_HPS_A12
DDR3_HPS_A2
DDR3_HPS_A8
DDR3_HPS_A3
DDR3_HPS_A9
DDR3_HPS_A4
DDR3_HPS_A10
DDR3_HPS_A14
DDR3_HPS_DQS_P2
DDR3_HPS_DQS_P3DDR3_HPS_DQS_N3
DDR3_HPS_DQS_N2
DDR3_HPS_DM3DDR3_HPS_DM2
DDR3_HPS_CLK_P
DDR3_HPS_ZQ2
DDR3_HPS_CASnDDR3_HPS_RASnDDR3_HPS_WEnDDR3_HPS_CSn
DDR3_HPS_BA2
DDR3_HPS_ODTDDR3_HPS_RESETn
DDR3_HPS_BA1
DDR3_HPS_CKE
DDR3_HPS_BA0
DDR3_HPS_CLK_N DDR3_HPS_DQS_P0
DDR3_HPS_DQS_P1DDR3_HPS_DQS_N1
DDR3_HPS_DQS_N0
DDR3_HPS_DM1DDR3_HPS_DM0
DDR3_HPS_CLK_P
DDR3_HPS_ZQ
DDR3_HPS_CASnDDR3_HPS_RASnDDR3_HPS_WEnDDR3_HPS_CSn
DDR3_HPS_BA2
DDR3_HPS_ODTDDR3_HPS_RESETn
DDR3_HPS_BA1
DDR3_HPS_CKE
DDR3_HPS_BA0
DDR3_HPS_CLK_N
DDR3_HPS_RESETn
DDR3_HPS_A14
DDR3_HPS_A12
DDR3_HPS_A7
DDR3_HPS_A2
DDR3_HPS_A6
DDR3_HPS_A3
DDR3_HPS_A13
DDR3_HPS_A8
DDR3_HPS_A1
DDR3_HPS_A11
DDR3_HPS_A5
DDR3_HPS_A10
DDR3_HPS_A4
DDR3_HPS_A9
DDR3_HPS_A0
DDR3_HPS_A7
DDR3_HPS_A3
DDR3_HPS_A8
DDR3_HPS_A13
DDR3_HPS_A6
DDR3_HPS_A12
DDR3_HPS_A2
DDR3_HPS_A9
DDR3_HPS_A14
DDR3_HPS_A4
DDR3_HPS_A10
DDR3_HPS_A5
DDR3_HPS_A11
DDR3_HPS_A1DDR3_HPS_A0
DDR3_HPS_DQ15
DDR3_HPS_DQ14
DDR3_HPS_DQ3DDR3_HPS_DQ21DDR3_HPS_DQ32
DDR3_HPS_CKE
DDR3_HPS_A0
DDR3_HPS_A1
DDR3_HPS_A7
DDR3_HPS_A2
DDR3_HPS_A3
DDR3_HPS_A4
DDR3_HPS_A5
DDR3_HPS_A6DDR3_HPS_A8
DDR3_HPS_RASn
DDR3_HPS_A9
DDR3_HPS_ODT
DDR3_HPS_WEn
DDR3_HPS_A13
DDR3_HPS_BA2
DDR3_HPS_CSn
DDR3_HPS_A10
DDR3_HPS_CASn
DDR3_HPS_BA0
DDR3_HPS_A11DDR3_HPS_A14
DDR3_HPS_A12 DDR3_HPS_BA1
DDR3_HPS_DQ0DDR3_HPS_DQ2DDR3_HPS_DQ1DDR3_HPS_DQ5DDR3_HPS_DQ4DDR3_HPS_DQ6DDR3_HPS_DQ7DDR3_HPS_DQ11DDR3_HPS_DQ8DDR3_HPS_DQ15DDR3_HPS_DQ14DDR3_HPS_DQ12DDR3_HPS_DQ10DDR3_HPS_DQ13DDR3_HPS_DQ9
DDR3_HPS_DQ23DDR3_HPS_DQ16DDR3_HPS_DQ19DDR3_HPS_DQ17DDR3_HPS_DQ22DDR3_HPS_DQ18DDR3_HPS_DQ20DDR3_HPS_DQ31DDR3_HPS_DQ25DDR3_HPS_DQ26DDR3_HPS_DQ28DDR3_HPS_DQ27DDR3_HPS_DQ29DDR3_HPS_DQ30DDR3_HPS_DQ24
DDR3_HPS_DQ36DDR3_HPS_DQ34DDR3_HPS_DQ35DDR3_HPS_DQ39DDR3_HPS_DQ37DDR3_HPS_DQ33DDR3_HPS_DQ38
DDR3_HPS_CLK_P DDR3_HPS_CLK_N
VTT_HPS_DDR3
VTT_HPS_DDR3
VTT_HPS_DDR3
VTT_HPS_DDR3VTT_HPS_DDR3
VTT_HPS_DDR3
VREF_HPS_DDR3 VREF_HPS_DDR3 VREF_HPS_DDR3
1.5V_REG_HPS 1.5V_REG_HPS 1.5V_REG_HPS
1.5V_REG_HPS
1.5V_REG_HPS
1.5V_REG_HPS
1.5V_REG_HPS
1.5V_REG_HPS
DDR3_HPS_DM[4:0]6
DDR3_HPS_BA[2:0]6
DDR3_HPS_DQS_P[4:0]6
DDR3_HPS_DQS_N[4:0]6
DDR3_HPS_A[14:0]6
DDR3_HPS_DQ[39:0]6
DDR3_HPS_CLK_P 6
DDR3_HPS_CLK_N 6
DDR3_HPS_CKE 6
DDR3_HPS_BA0 6
DDR3_HPS_BA1 6
DDR3_HPS_BA2 6
DDR3_HPS_RASn 6
DDR3_HPS_CASn 6
DDR3_HPS_WEn 6DDR3_HPS_CSn 6
DDR3_HPS_ODT 6DDR3_HPS_RESETn 6
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
15 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
15 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
15 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C750
2.2nF
C777
0.47uF
C490
0.1uF
RN4D 514 13
R560
240
C800
2.2nF
C488
4.7nF
CN6
0.1uF
1234 5
678
C612
0.1uF
DDR3 DeviceU38
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
RN8E 515 12
C686
2.2nF
C526
0.1uF
C683
0.47uF
R595
240
C548
2.2nF
R586 240
RN4G 517 10
C653
2.2nF
R568 10.0K
C487
0.47uF
CN8
0.1uF
1234 5
678
C769
2.2nF
C682
0.1uF
R527
240
RN8B 512 15
C551
0.47uF
RN4E 515 12
C611
0.1uF
C684
0.1uF
R622 10.0K
RN4C 513 14
RN8H 518 9
C492
2.2nF
C778
3300pF
RN8F 516 11
C588
2.2nF
TP5
C586
0.01uF
RN8D 514 13
R526
10.0K
C634
2.2nF
RN6C 513 14
R567 10.0K
C798
0.47uF
RN8C 513 14
C552
0.01uF
DDR3 DeviceU51
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
RN6H 518 9
C584
0.47uF
C491
0.01uF
RN4F 516 11
RN6F 516 11
TP7
C779
0.1uF
C486
2.2nF
RN4H 518 9
C685
0.01uF
R620 10.0K
C549
2.2nF
RN8A 511 16
C718
0.47uF
RN4A 511 16
C651
0.47uF
C797
0.1uF
R587100, 1%
RN6A 511 16
C799
0.01uF
TP4
RN8G 517 10
R566 10.0K
R5422.00K
C780
0.1uF
C652
3300pF
RN6D 514 13
TP6
C489
0.01uF
C587
0.01uF
R585 240
CN4
0.1uF
1234 5
678
RN6B 512 15
R528100, 1%
C720
0.1uF
R525
10.0K
C585
4.7nF
C509
2.2nF
RN6G 517 10
R559 4.70K, 1%
C749
2.2nF
R621 10.0K
C719
0.01uF
DDR3 DeviceU44
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
C654
2.2nF
R623 10.0K
RN4B 512 15
R565 10.0K
C550
0.1uF
C527
0.1uF
C717
2.2nF
C610
2.2nF
RN6E 515 12
C721
0.01uF
R594 240
C553
2.2nF
C748
4.7nF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1024MB DDR3 (x32) - FPGA PORT ADDR3A_CLK_P DDR3A_CLK_N
DDR3A_DQ17
DDR3A_DQS_P2
DDR3A_DQS_P3DDR3A_DQS_N3
DDR3A_DQS_N2
DDR3A_DM3DDR3A_DM2
DDR3A_CLK_P
DDR3A_ZQ1
DDR3A_CASnDDR3A_RASnDDR3A_WEnDDR3A_CSn
DDR3A_BA2
DDR3A_ODTDDR3A_RESETn
DDR3A_BA1
DDR3A_CKE
DDR3A_BA0
DDR3A_CLK_N
DDR3A_DQ6
DDR3A_DQS_P0
DDR3A_DQS_P1DDR3A_DQS_N1
DDR3A_DQS_N0
DDR3A_DM1DDR3A_DM0
DDR3A_CLK_P
DDR3A__ZQ
DDR3A_CASnDDR3A_RASnDDR3A_WEnDDR3A_CSn
DDR3A_BA2
DDR3A_ODTDDR3A_RESETn
DDR3A_BA1
DDR3A_CKE
DDR3A_BA0
DDR3A_CLK_N
DDR3A_RESETn
DDR3A_A0 DDR3A_A0
DDR3A_CKE
DDR3A_CSn DDR3A_BA0DDR3A_A3 DDR3A_A0
DDR3A_A5 DDR3A_A2
DDR3A_A7DDR3A_A9 DDR3A_A13 DDR3A_WEnDDR3A_ODT DDR3A_CASn DDR3A_RASnDDR3A_A14
DDR3A_A11 DDR3A_A8DDR3A_A1 DDR3A_A4 DDR3A_A12DDR3A_BA1 DDR3A_A10
DDR3A_BA2
DDR3A_A6
DDR3A_DQ5DDR3A_A1
DDR3A_DQ7DDR3A_A2
DDR3A_DQ1DDR3A_A3
DDR3A_DQ0DDR3A_A4
DDR3A_DQ3DDR3A_A5
DDR3A_DQ2DDR3A_A6
DDR3A_DQ4DDR3A_A7
DDR3A_DQ10DDR3A_A8
DDR3A_DQ15DDR3A_A9
DDR3A_DQ12DDR3A_A10
DDR3A_DQ8DDR3A_A11
DDR3A_DQ11DDR3A_A12
DDR3A_DQ9DDR3A_A13
DDR3A_DQ13DDR3A_A14
DDR3A_DQ14
DDR3A_A1DDR3A_A2DDR3A_A3DDR3A_A4DDR3A_A5DDR3A_A6DDR3A_A7DDR3A_A8DDR3A_A9DDR3A_A10DDR3A_A11DDR3A_A12DDR3A_A13DDR3A_A14
DDR3A_DQ16DDR3A_DQ21DDR3A_DQ18DDR3A_DQ23DDR3A_DQ19DDR3A_DQ22DDR3A_DQ20DDR3A_DQ28DDR3A_DQ25DDR3A_DQ26DDR3A_DQ24DDR3A_DQ30DDR3A_DQ29DDR3A_DQ31DDR3A_DQ27
VTT_FPGA_DDR3A
VTT_FPGA_DDR3A
VTT_FPGA_DDR3A
VTT_FPGA_DDR3AVTT_FPGA_DDR3A
VTT_FPGA_DDR3A
VREF_FPGA_DDR3A VREF_FPGA_DDR3A
1.5V_REG_FPGA
1.5V_REG_FPGA
1.5V_REG_FPGA
1.5V_REG_FPGA
1.5V_REG_FPGA
DDR3A_DM[3:0]4
DDR3A_BA[2:0]4
DDR3A_DQS_P[3:0]4
DDR3A_DQS_N[3:0]4
DDR3A_A[14:0]4
DDR3A_DQ[31:0]4
DDR3A_CKE4
DDR3A_CLK_P4
DDR3A_CLK_N4
DDR3A_DM24
DDR3A_DM34
DDR3A_CSn4
DDR3A_WEn4
DDR3A_RASn4
DDR3A_CASn4
DDR3A_BA04
DDR3A_BA14
DDR3A_BA24
DDR3A_RESETn4
DDR3A_ODT4
DDR3A_DM04
DDR3A_DM14
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
16 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
16 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
16 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
RN3B 512 15
C362
3300pF
RN3D 514 13
C454
0.01uF
DDR3 DeviceU29
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
R504
240
C376
2.2nF
V12
C369
0.47uF
V30
RN2E 515 12
CN1
0.1uF
1234 5
678
V24
V9
V31
C377
0.01uF
RN3E 515 12
R479
240
V17
C380
0.1uF
C453
2.2nF
C372
0.47uF
RN2B 512 15
C364
2.2nF
V27
RN2C 513 14
RN3F 516 11
V8
C403
4.7nF
V25 RN2G 517 10
RN1A 511 16
RN3A 511 16
V14
V21
C378
2.2nF
V22
C401
0.01uF
RN1C 513 14
C404
0.1uF
RN1D 514 13
V29R487 4.70K, 1%
C458
0.1uF
C360
3300pF
RN1H 518 9
C456
0.1uF
V23
RN1F 516 11RN1G 517 10
R488100, 1%
R5022.00K
V11
V16
V7
V15
C381
4.7nF
CN3
0.1uF
1234 5
678
RN3C 513 14
C418
0.47uF
RN3H 518 9
RN1E 515 12
C457
0.47uF
RN1B 512 15
V26
C361
0.1uF
C431
2.2nF
RN2F 516 11RN2H 518 9
C455
2.2nF
C402
2.2nF
C363
4.7nF
V28 V18
V13RN2D 514 13
C373
2.2nF
C405
2.2nF
RN2A 511 16CN2
0.1uF
1234 5
678
RN3G 517 10 V20
V10
DDR3 DeviceU37
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
C379
0.1uF
V19
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1024MB DDR3 (x32) - FPGA PORT BDDR3B_CLK_P DDR3B_CLK_N
DDR3B_DQ18
DDR3B_DQS_P2
DDR3B_DQS_P3DDR3B_DQS_N3
DDR3B_DQS_N2
DDR3B_DM3DDR3B_DM2
DDR3B_CLK_P
DDR3B_ZQ1
DDR3B_CASnDDR3B_RASnDDR3B_WEnDDR3B_CSn
DDR3B_BA2
DDR3B_ODTDDR3B_RESETn
DDR3B_BA1
DDR3B_CKE
DDR3B_BA0
DDR3B_CLK_N
DDR3B_DQ7
DDR3B_DQS_P0
DDR3B_DQS_P1DDR3B_DQS_N1
DDR3B_DQS_N0
DDR3B_RESETn
DDR3B_A0 DDR3B_A0
DDR3B_CKE
DDR3B_CSn DDR3B_BA0DDR3B_A3 DDR3B_A0
DDR3B_A5 DDR3B_A2
DDR3B_A7DDR3B_A9 DDR3B_A13 DDR3B_WEnDDR3B_ODT DDR3B_CASn DDR3B_RASnDDR3B_A14
DDR3B_A11 DDR3B_A8DDR3B_A1 DDR3B_A4 DDR3B_A12DDR3B_BA1 DDR3B_A10
DDR3B_BA2
DDR3B_A6
DDR3B_DQ20 DDR3B_DQ6DDR3B_A1 DDR3B_A1
DDR3B_DQ17 DDR3B_DQ5DDR3B_A2 DDR3B_A2
DDR3B_DQ19 DDR3B_DQ1DDR3B_A3 DDR3B_A3
DDR3B_DQ16 DDR3B_DQ2DDR3B_A4 DDR3B_A4
DDR3B_DQ21 DDR3B_DQ0DDR3B_A5 DDR3B_A5
DDR3B_DQ22 DDR3B_DQ4DDR3B_A6 DDR3B_A6
DDR3B_DQ23 DDR3B_DQ3DDR3B_A7 DDR3B_A7
DDR3B_DQ29 DDR3B_DQ13DDR3B_A8 DDR3B_A8
DDR3B_DQ30 DDR3B_DQ12DDR3B_A9 DDR3B_A9
DDR3B_DQ24 DDR3B_DQ9DDR3B_A10 DDR3B_A10
DDR3B_DQ27 DDR3B_DQ15DDR3B_A11 DDR3B_A11
DDR3B_DQ26 DDR3B_DQ10DDR3B_A12 DDR3B_A12
DDR3B_DQ28 DDR3B_DQ14DDR3B_A13 DDR3B_A13
DDR3B_DQ25 DDR3B_DQ8DDR3B_A14 DDR3B_A14
DDR3B_DQ11DDR3B_DQ31
DDR3B_DM1DDR3B_DM0
DDR3B_CLK_P
DDR3B_ZQ
DDR3B_CASnDDR3B_RASnDDR3B_WEnDDR3B_CSn
DDR3B_BA2
DDR3B_ODTDDR3B_RESETn
DDR3B_BA1
DDR3B_CKE
DDR3B_BA0
DDR3B_CLK_N
VTT_FPGA_DDR3B
VTT_FPGA_DDR3B
VTT_FPGA_DDR3B
VTT_FPGA_DDR3BVTT_FPGA_DDR3B
VTT_FPGA_DDR3B
VREF_FPGA_DDR3B VREF_FPGA_DDR3B
1.5V_REG_FPGA
1.5V_REG_FPGA
1.5V_REG_FPGA
1.5V_REG_FPGA
1.5V_REG_FPGA
DDR3B_DM[3:0]5
DDR3B_BA[2:0]5
DDR3B_DQS_P[3:0]5
DDR3B_DQS_N[3:0]5
DDR3B_A[14:0]5
DDR3B_DQ[31:0]5
DDR3B_CKE 5
DDR3B_CLK_P 5
DDR3B_CLK_N 5
DDR3B_DM2 5
DDR3B_DM3 5
DDR3B_CSn 5
DDR3B_WEn 5
DDR3B_RASn 5
DDR3B_CASn 5
DDR3B_BA0 5
DDR3B_BA1 5
DDR3B_BA2 5
DDR3B_RESETn 5
DDR3B_ODT 5
DDR3B_DM0 5
DDR3B_DM1 5
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
17 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
17 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
17 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.C761
0.47uF
V41
V39
C595
4.7nF
DDR3 DeviceU43
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
C531
3300pF
C690
0.01uF
V63
V57
C760
0.1uF
RN5H 518 9V52
V51RN9H 518 9
RN7G 517 10
C529
3300pF
V50
C730
2.2nF
V54
C560
0.47uF
RN5F 516 11
R531
240
V42
RN9F 516 11
RN5A 511 16
RN9D 514 13
V38
V59
RN5B 512 15
C592
2.2nF
RN9A 511 16RN7E 515 12
C694
2.2nF
V60
C533
2.2nF
RN5E 515 12
C590
2.2nF
C593
0.1uF
C762
0.1uF
RN9B 512 15
V55R539 4.70K, 1%
C594
0.1uF
V61
CN5
0.1uF
1234 5
678
C757
2.2nF
V53
RN5C 513 14
C759
2.2nF
C572
2.2nF
V48RN7B 512 15
C591
0.01uF
RN7H 518 9
C758
0.01uF
V40
V58
R545100, 1%
V66
C691
2.2nF
RN5G 517 10RN7C 513 14
R562
240
RN9G 517 10
C692
4.7nF
V62RN7F 516 11
V56
RN9E 515 12
RN7A 511 16RN7D 514 13
DDR3 DeviceU49
MT41K256M16HA-125:E
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4L9
A10/APL7
A11R7
A12/BCnN7
RESETnT2
VSSQB1
VSSQB9
VSSQD1
A9R3 A8T8 A7R2 A6R8
NC5M7
NC1J1
NC3L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2J9
RASJ3
CK_PJ7
CSL2
BA0M2
BA1N8
BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2
VDDD9
VDDG7
VDDK2
VSSA9
VSSB3
VSSE1
VSSG8
DQ0E3
LDQS_PF3
DQ1F7
DQ2F2
DQ3F8
DQ4H3
DQ5H8
DQ6G2
DQ7H7
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQS_PC7LDQS_NG3
UDQS_NB7
VSSQD8
VSSQE2
VSSQE8
VSSQF9
VDDQH9
VDDK8
VDDN1
VDDN9
VDDR1
VDDR9
VREFDQH1
VREFCAM8
VSSQG1
VSSQG9
VDDQA1
VDDQA8
VDDQC1
VDDQC9
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VSSJ2
VSSJ8
VSSM1
VSSM9
VSSP1
VSSP9
VSST1
VSST9
V47
CN7
0.1uF
1234 5
678
R5562.00K
C532
4.7nF
C571
0.47uF
RN9C 513 14
RN5D 514 13
C530
0.1uF
V65
C710
0.47uF
V49CN9
0.1uF
1234 5
678
C693
0.1uF
V64
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FM BUS
FLASH, EPCQ
FLASH 512Mb (32M X 16)
- When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software.
NOR PARALLEL FLASH
EPCQFM_A1
FM_D0
FLASH_RESETn
FLASH_WEnFLASH_RDYBSYn
FLASH_WPn
FM_D1FM_D2FM_D3FM_D4FM_D5FM_D6FM_D7
FM_D8FM_D9FM_D10FM_D11FM_D12FM_D13FM_D14FM_D15
FM_A2FM_A3FM_A4FM_A5FM_A6FM_A7FM_A8FM_A9FM_A10FM_A11FM_A12FM_A13FM_A14FM_A15FM_A16FM_A17FM_A18FM_A19FM_A20FM_A21FM_A22FM_A23FM_A24FM_A25
FLASH_WPn
FM_A26
FPGA_CONFIG_D0FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3FPGA_CONFIG_D4
FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3
FPGA_nCSO
LT1761_CSENSE
FPGA_nCSO
FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3
1V8
1V8
1V8
1V81V8
3.3V
5.0V
VPP
1V8VPP
VPP
9V_VPP
12V9V_VPP
3.3V
FM_A[26:1]19
FLASH_RDYBSYn 19
FM_D[15:0]19
FLASH_CLK19
FLASH_RESETn19FLASH_CEn019FLASH_OEn19FLASH_WEn19FLASH_ADVn19
FPGA_CONFIG_D113,19FPGA_CONFIG_D213,19FPGA_CONFIG_D313,19FPGA_CONFIG_D413,19
MAX_AS_CONF19
FPGA_CONFIG_D013,19
FPGA_DCLK 13,19
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
18 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
18 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
18 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C349
0.1uFU21
IDTQS3861
NC1
A02
A13
A24
A35
A46
A57
A68
A79
A810
A911
GND12
BE23
VCC24
B022
B121
B220
B319
B418
B517
B616
B715
B814
B913
R434 10K
R454 10K
R424 10K
R107
10.0K
U12
LT1761
VIN1
GND2
VOUT5
ADJ/BYPASS4
SHDN3
R4325.62k
C350
0.1uF
R4334.7KC62
4.7uF
J18
CON2
12
R455 10K
XJ1
881545-2
C323
0.1uF
C80
0.1uF
C65
4.7uF
U28
EPCQ256
VC
C2
NC013
NC024
NC035
NC046
nCS7
DATA18
DCLK16
DATA015
NC0511
NC0612
NC0713
NC0814
GN
D10
DATA29
DATA31
C328
0.1uF
C81
0.1uF
C325
0.1uF
C337
0.1uF
C322
0.1uF
C336
0.1uF
PC28FxxxP30B85FLASH
U13
PC28F512P30BF
A1A1
A2B1
A3C1
A4D1
A5D2
A6A2
A7C2
A8A3
A9B3
A10C3
A11D3
A12C4
A13A5
A14B5
A15C5
A16D7
A17D8
A18A7
A19B7
A20C7
A21C8
A22A8
NC(64M)/A23G1
CE#B4
OE#F8
WE#G8
WP#C6
VCCA6
RESET#D4
VCCH3
D0F2
D1E2
D2G3
D3E4
D4E5
D5G5
D6G6
D7H7
D8E1
D9E3
D10F3
D11F4
D12F5
D13H5
D14G7
D15E7
WAITF7
GNDB2
GNDH4GNDH2
CLKE6
ADV#F6
NC/A26(1G)B8
RFU3E8RFU2F1RFU1G2RFU0H1
NC(64M,128M)/A24H8
NC/A25(512M)B6
VPPA4
VCCQD6VCCQD5
VCCQG4
GNDH6
D19
CMDSH-3
R431 36K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
LED INTERFACE
PUSH BUTTON INTERFACE
MAXV DIPSWITCH
5M2210 System Controller
VCCINT 2.5V VCCIO
ON-BOARD USB BLASTER II
1.5V VCCIO
FPGA_DCLKFPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3
FPGA_CONFIG_D5FPGA_CONFIG_D6
FPGA_CONFIG_D4
FPGA_nSTATUSFPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_CONFIG_D7
PGM_LED[2:0]
MAX_ERROR
MAX_CONF_DONEMAX_LOAD
PGM_CONFIGMAX_RESETn
PGM_SEL
MSEL1MSEL2
MSEL0
MSEL3MSEL4
FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14FPGA_CONFIG_D15
CLK_100M_MAX
CLK_50M_MAX
FM_A21FM_A22
FPGA_CvP_CONFDONEFPGA_PR_ERROR
CLK50_EN
Si570_EN
CLK125A_EN
PGM_SEL
MAX_CONF_DONE
FPGA_nCONFIG
PGM_LED0PGM_CONFIG
CPU_RESETn
MAX_ERRORMAX_LOAD
SI571_EN
FM_D14FM_D15
FM_D10FM_D11FM_D12FM_D13
FM_D8FM_D9
FM_A1FM_A2FM_A3
FM_A0
FM_A4FM_A5FM_A6FM_A7
FM_A14
FM_A8FM_A9
FM_A15
FM_A10FM_A11FM_A12FM_A13
FM_A19FM_A20
FM_A18
FM_A16FM_A17
FM_D1FM_D2FM_D3
FM_D0
FM_D4FM_D5FM_D6FM_D7
FPGA_PR_READYFPGA_PR_REQUESTFPGA_PR_DONE
PGM_LED1PGM_LED2
FACTORY_LOAD
MAX_RESETn
FACTORY_STATUS
SECURITY_MODEM570_CLOCK
FACTORY_REQUEST
USB_CFG[11:0]
USB_CFG0
USB_CFG1
USB_CFG2USB_CFG3USB_CFG4USB_CFG5USB_CFG6USB_CFG7USB_CFG8USB_CFG9
USB_CFG10
USB_CFG11
USB_B2_CLK
EXTRA_SIG[2:0]
EXTRA_SIG1
EXTRA_SIG2
I2C_SDA_MAX
I2C_SCL_MAX
I2C_SDA_MAXI2C_SCL_MAX
I2C_SDA_MAXI2C_SCL_MAX MAX_FPGA_MOSI
MAX_FPGA_MISO
MAX_FPGA_MISOMAX_FPGA_MOSI
MAX_AS_CONF
FLASH_OEn
FLASH_ADVn
FLASH_CEn0
FLASH_CLKFLASH_RESETn
FLASH_WEn
FLASH_RDYBSYn
M570_PCIE_JTAG_EN
FM_A23
FM_A24FM_A25FM_A26
MAX_FPGA_SCKMAX_FPGA_SSEL
MAX_FPGA_SCKMAX_FPGA_SSEL
EXTRA_SIG0
USB_FPGA_RESET
1V8
2.5V_REG_HPS
1V8
1.5V_REG_HPS
1.5V_REG_HPS2.5V_REG_HPS
2.5V_REG_HPS
1V8
1V8
CPU_RESETn 13,28
FLASH_RDYBSYn 18
FPGA_nCONFIG13
FM_A[26:0]18
FM_D[15:0]18
FPGA_DCLK 13,18
FPGA_CONF_DONE 13
FPGA_nSTATUS 13
FLASH_CEn0 18
FLASH_ADVn 18
FLASH_WEn18
FLASH_OEn 18
FLASH_RESETn 18FLASH_CLK 18
CLK125A_EN 11,14
Si570_EN 11,14
CLK50_EN 11
FPGA_CONFIG_D[15:0]13,18
FACTORY_LOAD 14SECURITY_MODE 14
PGM_SEL28PGM_CONFIG28MAX_RESETn28
PGM_LED[2:0]28
MAX_ERROR28
MAX_LOAD28
MAX_CONF_DONE28
FPGA_PR_DONE 13FPGA_PR_REQUEST 13FPGA_PR_READY 13FPGA_PR_ERROR 13FPGA_CvP_CONFDONE 13
MSEL0 13MSEL1 13MSEL2 13MSEL3 13MSEL4 13
SI571_EN 9
M570_CLOCK 30FACTORY_STATUS 30FACTORY_REQUEST 30
M570_PCIE_JTAG_EN 30
USB_CFG[11:0]30
USB_B2_CLK4,30
EXTRA_SIG[2:0]30
JTAG_MAX_TDI 14JTAG_MAX_TDO 14JTAG_MAX_TMS 14
JTAG_MUX_TCK13,14,24,25
OVERTEMP 31
HPS_RESETn 7,26
USB_RESET 27
I2C_SDA 10,31,32
I2C_SCL 10,31,32
I2C_SDA_MAX 9,11
I2C_SCL_MAX 9,11 MAX_FPGA_MOSI13
MAX_FPGA_MISO13
MAX_AS_CONF 18,19
MAX_AS_CONF 18,19
JTAG_TRST 7,14MICTOR_RSTn 7,14,26
TRST 30RST 30
MAX_FPGA_SCK13MAX_FPGA_SSEL13
FMC_C2M_PG24
CLK_50M_MAX 11CLK_100M_MAX 11
FMCB_C2M_PG25
MAX_QSPI_RSTn 26
USB_FPGA_RESET27
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
19 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
19 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
19 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C365
0.1uF
C341
0.1uF
C385
0.1uF
C346
0.1uF
C384
0.1uF
C344
0.1uF
C355
0.1uF
C352
0.1uF
MAX VBANK2
U27B
5M2210ZF256
DIFFIO_T9PB8
DIFFIO_T9NA8
DIFFIO_T8PD8
DIFFIO_T8NA7
DIFFIO_T7PC8
DIFFIO_T7NB7
DIFFIO_T6PB6
DIFFIO_T6NE7
DIFFIO_T5PA5
DIFFIO_T5ND7
DIFFIO_T4PE6
DIFFIO_T4NB5
DIFFIO_T3PB4
DIFFIO_T3ND6
DIFFIO_T2PC5
DIFFIO_T2NC4
DIFFIO_T1PD4
DIFFIO_T1NB1
DIFFIO_T18PC13
DIFFIO_T18NB16
DIFFIO_T17PD12
DIFFIO_T17NB14
DIFFIO_T16PC11
DIFFIO_T16NB13
DIFFIO_T15PE11
DIFFIO_T15NB12
DIFFIO_T14PB11
DIFFIO_T14NA12
DIFFIO_T13PE10
DIFFIO_T13NA11
DIFFIO_T12PA10
DIFFIO_T12NC9
DIFFIO_T11PB9
DIFFIO_T11ND9
DIFFIO_T10PA9
DIFFIO_T10NE9
IOB2_6A13
IOB2_7A15
IOB2_8A2
IOB2_9A4
IOB2_10A6
IOB2_11B10
IOB2_12B3
IOB2_13C10
IOB2_14C12
IOB2_15C6
IOB2_16C7
IOB2_17D10
IOB2_18D11
IOB2_19D5
IOB2_20E8
R6740
C366
0.1uF
C356
0.1uF
MAX VBANK1
U27A
5M2210ZF256
DIFFIO_L19PN1
IOB1/CLK0H5
IOB1/CLK1J5
DIFFIO_L9PG1
DIFFIO_L9NG4
DIFFIO_L8PG2
DIFFIO_L8NG3
DIFFIO_L7PF1
DIFFIO_L7NF6
DIFFIO_L6PF4
DIFFIO_L6NF2
DIFFIO_L5PF3
DIFFIO_L5NE1
DIFFIO_L4PD1
DIFFIO_L4NE5
DIFFIO_L3PD2
DIFFIO_L3NE4
DIFFIO_L2PC3
DIFFIO_L2NE3
DIFFIO_L21PN3
DIFFIO_L21NP2
DIFFIO_L20PN2
DIFFIO_L20NM3
DIFFIO_L1PD3
DIFFIO_L1NC2
DIFFIO_L19NM4
DIFFIO_L18PL4
DIFFIO_L18NL3
DIFFIO_L17PM1
DIFFIO_L17NM2
DIFFIO_L16PL2
DIFFIO_L16NK3
DIFFIO_L15PK5
DIFFIO_L15NL1
DIFFIO_L14PJ3
DIFFIO_L14NK2
DIFFIO_L13PJ4
DIFFIO_L13NK1
DIFFIO_L12PH4
DIFFIO_L12NJ2
DIFFIO_L11PH3
DIFFIO_L11NJ1
DIFFIO_L10PH2
DIFFIO_L10NG5
IOB1_1E2
IOB1_2F5
IOB1_3H1
IOB1_4K4
IOB1_5L5
TMSN4TDOM5TDIL6TCKP3
R4860
MAX VPower
U27E
5M2210ZF256
GNDINTF7
GNDINTG6
GNDINTH7
GNDINTH9
GNDIOA1
GNDIOA16
GNDIOB15
GNDIOB2
GNDIOG10
GNDIOG7
GNDIOG8
GNDIOG9
GNDIOK10
GNDIOK7
GNDIOK8
GNDIOK9
GNDIOR15
GNDIOR2
GNDIOT1
GNDIOT16
VCCINTH8VCCINTH10VCCINTG11VCCINTF10
VCCIO1C1
VCCIO1H6
VCCIO1J6
VCCIO1P1
VCCIO2A14
VCCIO2A3
VCCIO2F8
VCCIO2F9
VCCIO3C16
VCCIO3H11
VCCIO3J11
VCCIO3P16
VCCIO4L8
VCCIO4L9
VCCIO4T14
VCCIO4T3
GNDINTJ10
VCCINTJ7
VCCINTL7
GNDINTJ8
GNDINTK11
VCCINTK6VCCINTJ9
GNDINTL10
GNDIOT6
R484 10KR483 10K
MAX VBANK3
U27C
5M2210ZF256
IOB3/CLK2J12
IOB3/CLK3H12
DIFFIO_R9PG12
DIFFIO_R9NG16
DIFFIO_R8PG13
DIFFIO_R8NG15
DIFFIO_R7PG14
DIFFIO_R7NF16
DIFFIO_R6PE16
DIFFIO_R6NF15
DIFFIO_R5PF13
DIFFIO_R5NE15
DIFFIO_R4PF14
DIFFIO_R4ND16
DIFFIO_R3PE12
DIFFIO_R3ND15
DIFFIO_R2PC15
DIFFIO_R2NE13
DIFFIO_R22PP15
DIFFIO_R22NP14
DIFFIO_R21PN15
DIFFIO_R21NN14
DIFFIO_R20PN16
DIFFIO_R20NM13
DIFFIO_R1PE14
DIFFIO_R1NC14
DIFFIO_R19PM15
DIFFIO_R19NL14
DIFFIO_R18PM16
DIFFIO_R18NL13
DIFFIO_R17PL15
DIFFIO_R17NL12
DIFFIO_R16PL16
DIFFIO_R16NL11
DIFFIO_R15PK15
DIFFIO_R15NK14
DIFFIO_R14PK16
DIFFIO_R14NK13
DIFFIO_R13PJ14
DIFFIO_R13NJ15
DIFFIO_R12PJ13
DIFFIO_R12NJ16
DIFFIO_R11PH13
DIFFIO_R11NH16
DIFFIO_R10PH14
DIFFIO_R10NH15
IOB3_21D13
IOB3_22D14
IOB3_23F11
IOB3_24F12
IOB3_25K12
IOB3_26M14
IOB3_27N13
R4850
MAX VBANK4
U27D
5M2210ZF256
DIFFIO_B13N/DEV_CLRnM9
DIFFIO_B13P/DEV_OEM8
DIFFIO_B9PP8
DIFFIO_B9NT7
DIFFIO_B8PM7
DIFFIO_B8NR7
DIFFIO_B7PR6
DIFFIO_B7NN7
DIFFIO_B6PT5
DIFFIO_B6NP7
DIFFIO_B5PR5
DIFFIO_B5NM6
DIFFIO_B4PP6
DIFFIO_B4NN6
DIFFIO_B3PR3
DIFFIO_B3NN5
DIFFIO_B2PT2
DIFFIO_B2NP5
DIFFIO_B22PR16
DIFFIO_B22NP13
DIFFIO_B21PP12
DIFFIO_B21NT15
DIFFIO_B20PN12
DIFFIO_B20NR14
DIFFIO_B1PR1
DIFFIO_B1NP4
DIFFIO_B19PT13
DIFFIO_B19NR13
DIFFIO_B18PR12
DIFFIO_B18NP11
DIFFIO_B17PT12
DIFFIO_B17NN11
DIFFIO_B16PP10
DIFFIO_B16NR11
DIFFIO_B15PN10
DIFFIO_B15NT11
DIFFIO_B14PM10
DIFFIO_B14NR10
DIFFIO_B12PR9
DIFFIO_B12NP9
DIFFIO_B11PT8
DIFFIO_B11NT9
DIFFIO_B10PN8
DIFFIO_B10NR8 IOB4_28
M11
IOB4_29M12
IOB4_30N9
IOB4_31R4
IOB4_32T10
IOB4_33T4
C386
0.1uF
C345
0.1uF
C354
0.1uF
C342
0.1uF
C370
0.1uF
C343
0.1uF
C353
0.1uF
C351
0.1uF
C357
0.1uF
R6780
C371
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet - HPS
Place near KSZ9021RN PHY
ETHERNET INTERFACE
BOOT-STRAPS
1.2V AVDLL_PLL
MDI_HPS_P1MDI_HPS_N1MDI_HPS_P2MDI_HPS_N2
CT3
MDI_HPS_P3
CT1
CT0
CT2
MDI_HPS_N3
MDI_HPS_N0MDI_HPS_P0
ENET_HPS_TX_ENENET_HPS_GTX_CLK
ENET_HPS_MDIO
ENET_HPS_MDC
ENET_HPS_RX_DV
ENET_HPS_TXD[3..0]
ENET_HPS_RX_CLK
ENET_HPS_RXD[3..0]
ENET_HPS_RESETn
ENET_HPS_INTn
ENET_HPS_RXD2
ENET_HPS_RXD0
ENET_HPS_RXD3
ENET_HPS_RXD1
ENET_HPS_RX_CLK
ENET_HPS_RX_DV
ENET_HPS_GTX_CLK
ENET_HPS_TX_EN
ENET_HPS_MDCENET_HPS_MDIO
ENET_HPS_LED2_LINKENET_HPS_LED1_LINK
ENET_HPS_INTn
ENET_HPS_RSET
ENET_HPS_RESETnENET_HPS_LED2_LINK
ENET_HPS_LED1_LINK
ENET_HPS_LED2_LINKENET_HPS_LED1_LINK
ENET_HPS_RXD2ENET_HPS_RXD3
ENET_HPS_RXD1ENET_HPS_RXD0ENET_HPS_RX_DV
CLK125_NDO_LED_MODE
CLK125_NDO_LED_MODE
ENET_HPS_TXD2
ENET_HPS_TXD0
ENET_HPS_TXD3
ENET_HPS_TXD1
CT0
CT1
CT2
CT3
ENET_HPS_RX_CLK
3.3V_REG_HPS
3.3V_REG_HPS
3.3V_REG_HPS1.2V_AVDLL_PLL
3.3V_AVDDH
3.3V_DVDDH 1.2V_AVDDL
1.2V_AVDLL_PLL
1.2V_AVDDL
1.2V_DVDDL 1.2V_DVDDL3.3V_DVDDH
3.3V_REG_HPS
3.3V_REG_HPS
3.3V_REG_HPS
3.3V_AVDDH
3.3V
2.5V_REG_HPS2.5V_REG_HPS
5.0V2.5V_REG_HPS
2.5V_REG_HPS
1.2V_AVDLL_PLL
ENET_HPS_RESETn20,26ENET_HPS_MDC7,20
ENET_HPS_GTX_CLK7
ENET_HPS_MDIO7,20
ENET_HPS_TX_EN7
ENET_HPS_RXD[3..0]7
ENET_HPS_RX_DV7ENET_HPS_RX_CLK7
ENET_HPS_TXD[3..0]7
ENET_HPS_INTn7,20
ENET_HPS_MDIO7,20
ENET_HPS_RESETn 20,26
ENET_HPS_MDC7,20
I2C_SCL_HPS 7,28,33I2C_SDA_HPS 7,28,33
ENET_HPS_INTn 7,20
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
20 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
20 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
20 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R343 DNI
R359 DNI
R125 2.00K
R368 DNI
C10722uF
C109
0.1uF
R360 4.70K, 1%
R50 4.70K, 1%R364 DNI
R124
1.00K
C9522uF
R39 4.70K, 1%
R367 1.00K
C77
0.1uF
R351 DNI
C98
2.2uF
R31
220
R352 4.70K, 1%
C11022uF
R344 4.70K, 1%
R379 DNI
C1062.2uF
R116 10.0K
C9722uF
C1132.2uF
L33
3A, 30 Ohm FB
L10
3A, 30 Ohm FB
R350 DNI
R74 220
C33122uF
C108
0.1uF
C3292.2uF
U7B
KSZ9021RN
DVDDL39
DVDDH40
LDO_O43AVDDL_PLL44
AVDDH47
P_GND49
VSS29 VSS_PS13
AVDDL9
AVDDL4AVDDH
1 AVDDH12
DVDDL30
DVDDL26
DVDDL23
DVDDL14DVDDH
16DVDDL
18
DVDDH34
L12
3A, 30 Ohm FB
R40 4.70K, 1%
C36 0.01uF
R349 4.70K, 1%
C111
0.1uF
C682.2uF
R366 4.70K, 1%
Y1
25.00MHz
13
24
R363 DNI
Yellow
Green
Orange
J13
ENET_L829-1J1T-43
TD0_P11
TD0_N10
TD1_P4
TD1_N5
TD2_P3
TD2_N2
TD3_P8
TD3_N9
CT012
GND_TAB19 GND_TAB18
OK15
GOA16
YA14
YK13
GK17
CT16
CT21
CT37
C37 0.01uF
C99 1uF
C7422uF
C40 DNIC51
10uF
C338
0.1uF
C38 DNI
C54 0.01uF
C52
10uF
R358 DNI
MDI INTERFACE
U7A
KSZ9021RN
TXRXP_A2
LED1_PHYAD017
TXRXP_D10
TXRXP_C7
TXRXM_C8
TXRXP_B5
TXRXM_B6
TXRXM_A3
TXRXM_D11
LED2_PHYAD115
TXD120
TXD019
GTX_CLK24
RXD0_MODE032
RX_DV_CLK125_EN33
TXD322
RXD2_MODE228
TX_EN25
RXD3_MODE327
RXD1_MODE131
TXD221
RX_CLK_PHYAD235
MDC36
MDIO37
INT_N38
XO45 XI46
ISET48
RESET_N42
CLK125_NDO_LED_MODE41
U26
LTC3026
IN11
IN22
GN
D3
SW4
BST5
SHDN6
PG7ADJ8
OUT19OUT210
GN
D11
U34
24LC32A
A01
A12
A23
GND4
VCC8
WP7
SCL6
SDA5
R361 4.70K, 1%
L13
3A, 30 Ohm FB
C53 0.01uF
R38 4.70K, 1%
R365 4.70K, 1%
R378 1.00K
R37 4.99K
C103
10uF
C962.2uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100M Ethernet - FPGA
Place near uPD60620 PHY
PLACE NEAR LEVEL TRANSLATORS
Place near uPD60620 PHY
BOOT-STRAPS
ENET1_TX_D0ENET1_TX_D1ENET1_TX_D2ENET1_TX_D3
ENET2_TX_D0
ENET2_TX_D2ENET2_TX_D1
ENET2_TX_D3
ENET2_RX_D2
ENET2_RX_D0
ENET2_RX_D3
ENET2_RX_D1
ENET1_RX_D2ENET1_RX_D3
ENET1_RX_D0ENET1_RX_D1
ENET1_TX_EN
ENET2_TX_EN
ENET1_RX_DV
ENET2_RX_DV
ENET1_RX_CLK
ENET2_RX_CLK
ENET1_RX_ERROR
ENET2_RX_ERROR
ENET1_TX_CLK_FB
ENET2_TX_CLK_FB
ENET1_TX_D0ENET1_TX_D1ENET1_TX_D2ENET1_TX_D3
ENET1_RX_D2ENET1_RX_D3
ENET1_RX_D0ENET1_RX_D1
ENET2_TX_D0
ENET2_TX_D2ENET2_TX_D1
ENET2_TX_D3
ENET2_RX_D2
ENET2_RX_D0
ENET2_RX_D3
ENET2_RX_D1
ENET1_LINK_LED
ENET1_RX_DVENET2_RX_DVENET1_RX_D0ENET1_RX_D1
ENET2_RX_D0ENET2_RX_D1ENET2_RX_CLKENET1_RX_ERRORENET2_RX_ERRORENET1_RX_CLK
ENET2_LINK_LED
ENET1_MDI_TX_PENET1_MDI_TX_N
ENET1_MDI_RX_PENET1_MDI_RX_N
ENET1_LINK_LED
ENET2_LINK_LED
ENET2_MDI_TX_PENET2_MDI_TX_N
ENET2_MDI_RX_PENET2_MDI_RX_N
ENET1_ACT_LED
ENET2_ACT_LED
ENET2_ACT_LED
ENET1_ACT_LED
REG_FB
ENET_DUAL_RESETn
REG_FB
P0TXERR_PHY
P1TXERR_PHY
P1TXERR_PHYP0TXERR_PHY
ENET2_TX_CLK_FB
1.5V_REG_HPS
3.3V
3.3V
1.5V_REG_HPS
1V5_ECAT2
3.3V3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
1V5_ECAT
3.3V
1V5_ECAT2
ENET1_TX_D[3..0]4
ENET1_RX_D[3..0]4
ENET2_RX_D[3..0]4
ENET2_TX_D[3..0]4
ENET1_RX_ERROR4ENET1_RX_DV4ENET1_RX_CLK4ENET1_TX_CLK_FB4
ENET2_RX_ERROR4
ENET2_RX_CLK4
ENET2_RX_DV4
ENET2_TX_CLK_FB4
ENET1_TX_EN4
ENET2_TX_EN4
ENET_FPGA_MDC4
ENET_FPGA_MDIO4
ENET_DUAL_RESETn4,26
P0TXERR4,21
P1TXERR4,21
P0TXERR4,21
CLK_DUAL_ENET_PHY11
P1TXERR4,21
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
21 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
21 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
21 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C821
0.1uF
R616 DNI
R642
0
Green
Yellow
J47
EN
ET
-74
99
01
11
21
A
TD+1
TD-3
RD+4
RD-6
GND8
GND_TAB13
GND_TAB14
GK
12
GA
11
YA
9
YK
10
TCT2
RCT5
GN
D_T
AB
115
GN
D_T
AB
216
NC
7
C248
12pF
C255
12pF
C812
0.1uF
R609 DNI
C819
0.1uF
R608 DNI
R656 4.70K, 1%
R649 DNI
C247
12pF
C254
12pF
C822
0.1uF
R615 4.70K, 1%
R619 DNI
R611 4.70K, 1%
Green
Yellow
J48
EN
ET
-74
99
01
11
21
A
TD+1
TD-3
RD+4
RD-6
GND8
GND_TAB13
GND_TAB14
GK
12
GA
11
YA
9
YK
10
TCT2
RCT5
GN
D_T
AB
115
GN
D_T
AB
216
NC
7
C260
0.01uF
C257
0.01uF
R658 4.70K, 1%
C820
0.1uF
R614 4.70K, 1%
R637 DNI
R238
0_Ohms
D32
40V
R328 220
R617 DNI
C256
0.01uF
R607 4.70K, 1%
C817
0.1uF
R26710
C814
0.1uF
C80422uF25V
R601 DNI
R663 4.70K, 1%
R599 4.70K, 1%
R2520
R329 220
R643 4.70K, 1%
R610 DNI
C813
0.1uF
R27810
R330 220
C253
0.01uF
R603 4.70K, 1%
R618 DNI
R27749.9
C811
0.1uF
R26810
C823
0.1uF
R600 DNI
C142
4.7uF
R27110
R598 DNI
R331 220
R647 DNI
C141
0.1uF
R604 4.70K, 1%
R237DNI
R27049.9
C249
0.01uF
C818
0.1uF
R631 4.70K, 1%
C140
0.1uF
R613
0
R242 DNI
C259
12pF
C80522uF25V
R26949.9
C250
0.01uF
R602 4.70K, 1%
R27649.9
R612 DNI
R630 4.70K, 1%
C139
0.1uF
R26649.9
R27349.9
R606 4.70K, 1%
R636 DNI
R646 4.70K, 1%
R657 12.4K
C138
0.1uF
R27510
R27410
C252
12pFR628 DNI
C815
0.1uF
R26549.9
R629 DNI
R648 DNI
R251
DNI
L2610uH
12
C816
0.1uF
U55
uPD60621
P0TXD043
P0TXD144
P0TXD245
P0TXD346
P1TXD023
P1TXD124
P1TXD225
P1TXD326
P0TXERR47
P0TXEN48
P0TXCLK49
P0RXD053
P0RXD154
P0RXD255
P0RXD356
P0RXDV57 P0RXERR58
P0RXCLK59
P0CRS60
P0TXP15
P0TXN16
P0RXP17
P0RXN18
P1RXD136
P1TXEN28
P1RXD237
P1TXERR27
P1RXCLK41 P1RXDV39
P1CRS42
P1RXERR40
P1RXD035
P1RXD338
P1TXCLK29
REGBVDD170
REGBVDD271
REGAVDD77
VCC33ESD20
VDDIO132
VDDIO366VDDIO250
REGLX172
REGLX273
VDDACB10
VDD15_130
VDD15_252
VDDAPLL11
P1TXN6P1TXP7
P1RXP5
P1RXN4
REGBGND174
REGBGND275
P0AGND14
P1AGND8
GNDIO31
GND1551
VSSAPLL9
P0VDDMEDIA19
P1VDDMEDIA3
REGFB78
XCLK033
XCLK134
REGOFF80
RESETB1
TEST2 ATP
13
P0COL21
P1COL22
EXTRES12
DR79
MDC62 MDIO63
P0100BTLED64
P1100BTLED61
P0ACTLED68
P1ACTLED65
P0LINKED69
P1LINKED67
REGAGND76
C251
12pF
C258
12pF
R27249.9
R627 4.70K, 1%
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Optical (SFP) Transceiver Cage & Connector 1
Optical (SFP+) Transceiver Cage & Connector 0
Small Form Factor Pluggable Plus (SFP+) Port A
SFPA_RX_PSFPA_RX_N
SFPA_RX_N
SFPA_TX_P
SFPA_LOS
SFPA_TXDISABLE
SFPA_RX_PSFPA_TXFAULT
SFPB_VCCR
SFPA_RATESEL0
SFPA_TX_N
SFPB_VCCT
SFPA_RATESEL0
SFPA_TX_PSFPA_TX_N
SFPA_RATESEL1SFPA_LOSSFPA_TXFAULT
SFPA_RATESEL0
SFPA_RATESEL1
SFPA_LOSSFPA_TXFAULT
SFPA_MOD2_SDASFPA_MOD1_SCLSFPA_MOD0_PRSNTn
SFPA_MOD2_SDASFPA_MOD1_SCLSFPA_MOD0_PRSNTn
SFPA_RATESEL1
SFPA_MOD2_SDASFPA_MOD1_SCLSFPA_MOD0_PRSNTn
SFPA_TXDISABLE
SFPA_VCCT
SFPA_VCCR
3.3V
2.5V_REG_FPGA
GND_CAGE
SFPA_VCCTSFPA_VCCR
GND_CAGE
SFPA_TXFAULT5SFPA_LOS5
SFPA_MOD1_SCL5
SFPA_TX_P9SFPA_TX_N9
SFPA_RATESEL05
SFPA_TXDISABLE5
SFPA_RX_P9SFPA_RX_N9
SFPA_MOD0_PRSNTn5
SFPA_MOD2_SDA5
SFPA_RATESEL15
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
22 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
22 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
22 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C792
10uF
R281 4.7K
R239 4.7K
C801
10uF
R253 4.7K
C810
0.1uF
R243 4.7K
J44
SFP+_AND_CAGE
CAGE_GND21
CAGE_GND22
CAGE_GND23
CAGE_GND24
CAGE_GND25
CAGE_GND26
CAGE_GND27
CAGE_GND28
CAGE_GND29
CAGE_GND30
CAGE_GND31
CAGE_GND32
CAGE_GND33
CAGE_GND34
VEET1
VEET17
VEET20
RS19
VEER10
VEER11
VEER14
TD_P18
TD_N19
RX_LOS8
TX_FAULT2
VCCT16
VCCR15
RD_P13
RD_N12
TX_DISABLE3
RS07
MOD_ABS6
SCL5
SDA4
CAGE_GND35
CAGE_GND36
CAGE_GND37
CAGE_GND38
CAGE_GND39
CAGE_GND40
MH141
MH242
R244 4.7K
B5
SFP+_CAGE
L40 1.0uH
C802
0.1uF
R231 4.7K
L37 1.0uHC791
0.1uF
R282 4.7K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Optical (SFP) Transceiver Cage & Connector 1
Optical (SFP+) Transceiver Cage & Connector 0
Small Form Factor Pluggable Plus (SFP+) Port B
SFPB_RX_PSFPB_RX_N
SFPB_RX_N
SFPB_TX_P
SFPB_LOS
SFPB_TXDISABLE
SFPB_RX_PSFPB_TXFAULT
SFPB_VCCR
SFPB_RATESEL0
SFPB_TX_N
SFPB_VCCT
SFPB_RATESEL0
SFPB_TX_PSFPB_TX_N
SFPB_RATESEL1SFPB_LOSSFPB_TXFAULT
SFPB_RATESEL0
SFPB_RATESEL1
SFPB_LOSSFPB_TXFAULT
SFPB_MOD2_SDASFPB_MOD1_SCLSFPB_MOD0_PRSNTn
SFPB_MOD2_SDASFPB_MOD1_SCLSFPB_MOD0_PRSNTn
SFPB_RATESEL1
SFPB_MOD2_SDASFPB_MOD1_SCLSFPB_MOD0_PRSNTn
SFPB_TXDISABLE
SFPB_VCCT
SFPB_VCCR
3.3V
2.5V_REG_FPGA
GND_CAGE
SFPB_VCCTSFPB_VCCR
GND_CAGE
SFPB_TXFAULT10SFPB_LOS10
SFPB_MOD1_SCL10
SFPB_TX_P9SFPB_TX_N9
SFPB_RATESEL05
SFPB_TXDISABLE5
SFPB_RX_P9SFPB_RX_N9
SFPB_MOD0_PRSNTn10
SFPB_MOD2_SDA10
SFPB_RATESEL15
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
23 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
23 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
23 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
L39 1.0uHC795
0.1uF
R288 4.7K
C796
10uF
R279 4.7K
R305 4.7K
C793
10uF
R287 4.7K
C774
0.1uF
R304 4.7K
J43
SFP+_AND_CAGE
CAGE_GND21
CAGE_GND22
CAGE_GND23
CAGE_GND24
CAGE_GND25
CAGE_GND26
CAGE_GND27
CAGE_GND28
CAGE_GND29
CAGE_GND30
CAGE_GND31
CAGE_GND32
CAGE_GND33
CAGE_GND34
VEET1
VEET17
VEET20
RS19
VEER10
VEER11
VEER14
TD_P18
TD_N19
RX_LOS8
TX_FAULT2
VCCT16
VCCR15
RD_P13
RD_N12
TX_DISABLE3
RS07
MOD_ABS6
SCL5
SDA4
CAGE_GND35
CAGE_GND36
CAGE_GND37
CAGE_GND38
CAGE_GND39
CAGE_GND40
MH141
MH242
R291 4.7K
B6
SFP+_CAGE
L38 1.0uH
C794
0.1uF
R280 4.7K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FMC PORT A
FMC INTERFACE
CLK2_BIDIR, CLK3_BIDIR,and CLK_DIR only on HighPincount versions.
PG_M2C only on HighPincount versions.
SYNC (C->M)
Alt. DEVCLKB
Alt. DEVCLK
SYSREF (M->C)
SYSREF (C->M)
DEVCLK
DEVCLKB
Alt. SYSREF (M->C)
Alt. SYSREF (C->M)
Blue means change from current Altera FMC spec
Alt. SYNC (C->M)
SYNC (M->C)
Alt. SYNC(M->C)
TRANSLATORFMC_DP_C2M_N0FMC_DP_C2M_P0
FMC_DP_C2M_N3FMC_DP_C2M_P3FMC_DP_C2M_N2FMC_DP_C2M_P2FMC_DP_C2M_N1FMC_DP_C2M_P1
FMC_C2M_PG
FMC_DP_C2M_N4FMC_DP_C2M_P4
FMC_DP_C2M_P6FMC_DP_C2M_N5FMC_DP_C2M_P5
FMC_DP_C2M_P7FMC_DP_C2M_N6
FMC_GA0FMC_GA1
FMC_DP_C2M_N7
FMC_DP_M2C_N0FMC_DP_M2C_P0
FMC_DP_M2C_N4FMC_DP_M2C_P4FMC_DP_M2C_N3FMC_DP_M2C_P3FMC_DP_M2C_N2FMC_DP_M2C_P2FMC_DP_M2C_N1FMC_DP_M2C_P1
FMC_DP_M2C_N7FMC_DP_M2C_P7FMC_DP_M2C_N6FMC_DP_M2C_P6FMC_DP_M2C_N5FMC_DP_M2C_P5
FMC_CLK_M2C_N1
FMC_CLK_M2C_P0
FMC_CLK_M2C_P1FMC_CLK_M2C_N0
FMC_M2C_PG
FMC_LA_RX_P0FMC_LA_RX_N0
FMC_LA_TX_P0FMC_LA_TX_N0
FMC_LA_RX_N1FMC_LA_RX_P1
FMC_LA_TX_N1FMC_LA_TX_P1
FMC_SYSREF_NFMC_SYSREF_P
FMC_LA_TX_N3
FMC_LA_RX_N3FMC_LA_RX_P3
FMC_LA_TX_P3
FMC_LA_TX_N4
FMC_LA_RX_N4FMC_LA_RX_P4
FMC_LA_TX_P4
FMC_LA_TX_N5
FMC_LA_RX_N5FMC_LA_RX_P5
FMC_LA_TX_P5
FMC_LA_TX_N6
FMC_LA_RX_N6FMC_LA_RX_P6
FMC_LA_TX_P6
FMC_LA_TX_N7FMC_LA_TX_P7
FMC_LA_RX_N7
FMC_LA_RX_N8FMC_LA_RX_P8
FMC_LA_RX_P7
FMC_LA_TX_N9
FMC_LA_RX_N9FMC_LA_RX_P9
FMC_LA_TX_P9
FMC_LA_TX_N10
FMC_LA_RX_N10FMC_LA_RX_P10
FMC_LA_TX_P10
FMC_LA_RX_N11FMC_LA_RX_P11
FMC_LA_TX_N12
FMC_LA_RX_N12FMC_LA_RX_P12
FMC_LA_TX_P12
FMC_LA_TX_N13
FMC_LA_RX_N13FMC_LA_RX_P13
FMC_LA_TX_P13
FMC_LA_RX_P14FMC_LA_RX_N14
FMC_LA_RX_CLK_NFMC_LA_RX_CLK_P
FMC_LA_TX_N14FMC_LA_TX_P14
FMC_LA_TX_N15FMC_LA_TX_P15
FMC_DEVCLK_PFMC_DEVCLK_N
FMC_JTAG_RST
FMC_LA_RX_N2FMC_LA_RX_P2
FMC_LA_RX_N15FMC_LA_RX_P15
FMC_LA_TX_N16FMC_LA_TX_P16
FMC_LA_TX_N17FMC_LA_TX_P17
FMC_GPIO0FMC_GPIO1FMC_GPIO2FMC_GPIO3FMC_GPIO4FMC_GPIO5FMC_GPIO6FMC_GPIO7
FMC_DEVCLK_PFMC_DEVCLK_N
FMC_LA_TX_CLK_PFMC_LA_TX_CLK_N
FMC_LA_TX_P2FMC_LA_TX_N2FMC_SYSREF_N
FMC_SYSREF_P
VREF_FMC
3.3V
12V
VAR_VCCIOP
3.3V 3.3V
VREF_FMC
VAR_VCCIOP
FMC_DP_C2M_P[7:0]9
FMC_DP_C2M_N[7:0]9
FMC_JTAG_TDI 14
FMC_DP_M2C_N[7:0]9
FMC_DP_M2C_P[7:0]9
FMC_GA[1:0]8
FMC_JTAG_TMS 14
JTAG_MUX_TCK 13,14,19,25
FMC_JTAG_TDO 14
FMC_GBTCLK_M2C_P0 9FMC_GBTCLK_M2C_N0 9FMC_GBTCLK_M2C_P1 9FMC_GBTCLK_M2C_N1 9
FMC_CLK_M2C_P[1:0]10
FMC_CLK_M2C_N[1:0]10
FMC_PRSNTn8,28
FMC_C2M_PG 19
FMC_LA_TX_P[17:0]8
FMC_LA_TX_N[17:0]8
FMC_LA_RX_P[15:0]8,10
FMC_LA_RX_N[15:0]8,10
FMC_SCL8
FMC_SDA8
FMC_LA_RX_CLK_N10
FMC_LA_RX_CLK_P10
FMC_LA_TX_CLK_N8
FMC_LA_TX_CLK_P8
FMC_GPIO[7:0]8
LMK_SYSREF_FMC_N12
LMK_SYSREF_FMC_P12
LMK_CLK_FMC_N12
LMK_CLK_FMC_P12
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
24 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
24 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
24 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R87
DNI
R90 10.0K
J26E
ASP-134486-01
CLK_DIRB1
CLK0_M2C_NH5CLK0_M2C_PH4
CLK1_M2C_NG3CLK1_M2C_PG2
CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34
GA1D35
PG_C2MD1
PG_M2CF1
PRSNT_M2C_LH2
RES0B40
SCLC30 SDAC31
TCKD29TDID30TDOD31TMSD33TRSTD34
3P3VAUXD32
3P3VD40
3P3VC39
3P3VD36
3P3VD38
12P0VC35
12P0VC37
VADJE39
VADJF40
VADJG39
VADJH40
VIO_B_M2CK40
VIO_B_M2CJ39
VREF_B_M2CK1
VREF_A_M2CH1
R88
DNI
J26A
ASP-134486-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16G19
LA_N17D21
LA_N18_CCC23
LA_N19H23
LA_N2H8
LA_N20G22
LA_N21H26
LA_N22G25
LA_N23D24
LA_N24H29
LA_N25G28
LA_N26D27
LA_N27C27
LA_N28H32
LA_N29G31
LA_N3G10
LA_N30H35
LA_N31G34
LA_N32H38
LA_N33G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16G18
LA_P17D20
LA_P18_CCC22
LA_P19H22
LA_P2H7
LA_P20G21
LA_P21H25
LA_P22G24
LA_P23D23
LA_P24H28
LA_P25G27
LA_P26D26
LA_P27C26
LA_P28H31
LA_P29G30
LA_P3G9
LA_P30H34
LA_P31G33
LA_P32H37
LA_P33G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
R40030
R40040
R89 10.0K
R4005DNI
R40070
R184 10.0K
J26C
ASP-134486-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11J31
HB_N12F32
HB_N13E31
HB_N14K35
HB_N15J34
HB_N16F35
HB_N17_CCK38
HB_N18J37
HB_N19E34
HB_N2F23
HB_N20F38
HB_N21E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11J30
HB_P12F31
HB_P13E30
HB_P14K34
HB_P15J33
HB_P16F34
HB_P17_CCK37
HB_P18J36
HB_P19E33
HB_P2F22
HB_P20F37
HB_P21E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
R4006DNI
R4008DNI
J26D
ASP-134486-01
DP0_C2M_NC3 DP0_C2M_PC2
DP0_M2C_NC7DP0_M2C_PC6
DP1_C2M_NA23 DP1_C2M_PA22
DP1_M2C_NA3DP1_M2C_PA2
DP2_C2M_NA27 DP2_C2M_PA26
DP2_M2C_NA7DP2_M2C_PA6
DP3_C2M_NA31 DP3_C2M_PA30
DP3_M2C_NA11DP3_M2C_PA10
DP4_C2M_NA35 DP4_C2M_PA34
DP4_M2C_NA15DP4_M2C_PA14
DP5_C2M_NA39 DP5_C2M_PA38
DP5_M2C_NA19DP5_M2C_PA18
DP6_C2M_NB37 DP6_C2M_PB36
DP6_M2C_NB17DP6_M2C_PB16
DP7_C2M_NB33 DP7_C2M_PB32
DP7_M2C_NB13DP7_M2C_PB12
DP8_C2M_NB29 DP8_C2M_PB28
DP8_M2C_NB9DP8_M2C_PB8
DP9_C2M_NB25 DP9_C2M_PB24
DP9_M2C_NB5DP9_M2C_PB4
GBTCLK0_M2C_ND5GBTCLK0_M2C_PD4
GBTCLK1_M2C_NB21GBTCLK1_M2C_PB20
J26B
ASP-134486-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12F14
HA_N13E13
HA_N14J16
HA_N15F17
HA_N16E16
HA_N17_CCK17
HA_N18J19
HA_N19F20
HA_N2K8
HA_N20E19
HA_N21K20
HA_N22J22
HA_N23K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12F13
HA_P13E12
HA_P14J15
HA_P15F16
HA_P16E15
HA_P17_CCK16
HA_P18J18
HA_P19F19
HA_P2K7
HA_P20E18
HA_P21K19
HA_P22J21
HA_P23K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
C67
0.1uF
R40090
R4010DNI
J26F
ASP-134486-01
GNDK2
GNDK3
GNDK6
GNDK9
GNDK12
GNDK15
GNDK18
GNDK21
GNDK24
GNDK27
GNDK30
GNDK33
GNDK36
GNDK39
GNDJ1
GNDJ4
GNDJ5
GNDJ8
GNDJ11
GNDJ14
GNDJ17
GNDJ20
GNDJ23
GNDJ26
GNDJ29
GNDJ32
GNDJ35
GNDJ38
GNDJ40
GNDH3
GNDH6
GNDH9
GNDH12
GNDH15
GNDH18
GNDH21
GNDH24
GNDH27
GNDH30
GNDH33
GNDH36
GNDH39
GNDD2
GNDD3
GNDD6
GNDD7
GNDD10
GNDD13
GNDD16
GNDD19
GNDD22
GNDD25
GNDD28
GNDD37
GNDD39
GNDC1
GNDC4
GNDC5
GNDC8
GNDC9
GNDC12
GNDC13
GNDC16
GNDC17
GNDC20
GNDC21
GNDC24
GNDC25
GNDC28
GNDC29
GNDC32
GNDC33
GNDC36GNDC38GNDC40GNDB2GNDB3GNDB6GNDB7GNDB10GNDB11GNDB14GNDB15GNDB18GNDB19GNDB22GNDB23GNDB26GNDB27GNDB30GNDB31GNDB34GNDB35GNDB38GNDB39GNDA1GNDA4GNDA5GNDA8GNDA9GNDA12GNDA13GNDA16GNDA17GNDA20GNDA21GNDA24GNDA25GNDA28GNDA29GNDA32GNDA33GNDA36GNDA37GNDA40GNDG1GNDG4GNDG5GNDG8GNDG11GNDG14GNDG17GNDG20GNDG23GNDG26GNDG29GNDG32GNDG35GNDG38GNDG40GNDF2GNDF3GNDF6GNDF9GNDF12GNDF15GNDF18GNDF21GNDF24GNDF27GNDF30GNDF33GNDF36GNDF39GNDE1GNDE4GNDE5GNDE8GNDE11GNDE14GNDE17GND
E20
GNDE23
GNDE26
GNDE29
GNDE32
GNDE35
GNDE38
GNDE40
C66
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FMC PORT B
CLK2_BIDIR, CLK3_BIDIR,and CLK_DIR only on HighPincount versions.
PG_M2C only on HighPincount versions.
SYNC (C->M)
Alt. DEVCLKB
Alt. DEVCLK
SYSREF (M->C)
SYSREF (C->M)
DEVCLK
DEVCLKB
Alt. SYSREF (M->C)
Alt. SYSREF (C->M)
Blue means change from current Altera FMC spec
Alt. SYNC (C->M)
SYNC (M->C)
Alt. SYNC(M->C)
TRANSLATOR
FMC PORT B INTERFACE
FMCB_LA_RX_N3FMCB_LA_RX_P3
FMCB_LA_RX_N14FMCB_LA_RX_P14
FMCB_LA_TX_N6FMCB_LA_TX_P6
FMCB_LA_TX_N5FMCB_LA_TX_P5
FMCB_GPIO0FMCB_GPIO1FMCB_GPIO2FMCB_GPIO3FMCB_GPIO4FMCB_GPIO5FMCB_GPIO6FMCB_GPIO7
FMCB_LA_RX_P12FMCB_LA_RX_N12
FMCB_LA_TX_P16FMCB_LA_TX_N16
FMCB_LA_RX_N8FMCB_LA_RX_P8
FMCB_LA_TX_N7FMCB_LA_TX_P7
FMCB_SYSREF_NFMCB_SYSREF_P
FMCB_LA_TX_N10
FMCB_LA_RX_N7FMCB_LA_RX_P7
FMCB_LA_TX_P10
FMCB_LA_TX_N0
FMCB_LA_RX_N6FMCB_LA_RX_P6
FMCB_LA_TX_P0
FMCB_LA_TX_N4
FMCB_LA_RX_N15FMCB_LA_RX_P15
FMCB_LA_TX_P4
FMCB_LA_TX_N15
FMCB_LA_RX_N4FMCB_LA_RX_P4
FMCB_LA_TX_P15
FMCB_LA_TX_N3FMCB_LA_TX_P3
FMCB_LA_RX_N11
FMCB_LA_RX_N2FMCB_LA_RX_P2
FMCB_LA_RX_P11
FMCB_LA_TX_N1
FMCB_LA_RX_N1FMCB_LA_RX_P1
FMCB_LA_TX_P1
FMCB_LA_TX_N12
FMCB_LA_RX_N13FMCB_LA_RX_P13
FMCB_LA_TX_P12
FMCB_LA_RX_N5FMCB_LA_RX_P5
FMCB_LA_TX_N9
FMCB_LA_RX_N0FMCB_LA_RX_P0
FMCB_LA_TX_P9
FMCB_LA_TX_N14
FMCB_LA_RX_N9FMCB_LA_RX_P9
FMCB_LA_TX_P14
FMCB_LA_RX_P10FMCB_LA_RX_N10
FMCB_LA_RX_CLK_NFMCB_LA_RX_CLK_P
FMCB_LA_TX_N17FMCB_LA_TX_P17
FMCB_LA_TX_N2FMCB_LA_TX_P2
FMCB_DEVCLK_PFMCB_DEVCLK_N
FMCB_DP_C2M_N0FMCB_DP_C2M_P0
FMCB_DP_C2M_N3FMCB_DP_C2M_P3FMCB_DP_C2M_N2FMCB_DP_C2M_P2FMCB_DP_C2M_N1FMCB_DP_C2M_P1
FMCB_C2M_PG
FMCB_GA0FMCB_GA1
FMCB_DP_M2C_N0FMCB_DP_M2C_P0
FMCB_DP_M2C_P3FMCB_DP_M2C_N2FMCB_DP_M2C_P2FMCB_DP_M2C_N1FMCB_DP_M2C_P1
FMCB_CLK_M2C_N1
FMCB_CLK_M2C_P0
FMCB_CLK_M2C_P1FMCB_CLK_M2C_N0
FMCB_M2C_PG
FMCB_JTAG_RST
FMCB_DP_M2C_N3 JTAG_MUX_TCK
FMCB_LA_TX_P13FMCB_LA_TX_N13FMCB_SYSREF_N
FMCB_SYSREF_P FMCB_DEVCLK_PFMCB_DEVCLK_N
FMCB_LA_TX_CLK_PFMCB_LA_TX_CLK_N
VREF_FMCB
3.3V
12V
VAR_VCCIOP
3.3V 3.3V
VREF_FMCB
VAR_VCCIOP
FMCB_DP_C2M_P[3:0]9
FMCB_DP_C2M_N[3:0]9
FMCB_JTAG_TDI 13,14
FMCB_DP_M2C_N[3:0]9
FMCB_DP_M2C_P[3:0]9
FMCB_GA[1:0]8
FMCB_JTAG_TMS 13
JTAG_MUX_TCK 13,14,19,24
FMCB_JTAG_TDO 13
FMCB_GBTCLK_M2C_P0 9FMCB_GBTCLK_M2C_N0 9FMCB_GBTCLK_M2C_P1 9FMCB_GBTCLK_M2C_N1 9
FMCB_CLK_M2C_P[1:0]10
FMCB_CLK_M2C_N[1:0]10
FMCB_PRSNTn6,28
FMCB_C2M_PG 19
FMCB_LA_TX_P[17:0]8,10
FMCB_LA_TX_N[17:0]8,10
FMCB_LA_RX_P[15:0]8,10
FMCB_LA_RX_N[15:0]8,10
FMCB_SCL6
FMCB_SDA6
FMCB_LA_RX_CLK_N10
FMCB_LA_RX_CLK_P10
FMCB_LA_TX_CLK_N10
FMCB_LA_TX_CLK_P10
FMCB_GPIO[7:0]6
LMK_SYSREF_FMCB_P12
LMK_SYSREF_FMCB_N12
LMK_CLK_FMCB_P12
LMK_CLK_FMCB_N12
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
25 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
25 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
25 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
J4F
ASP-134486-01
GNDK2
GNDK3
GNDK6
GNDK9
GNDK12
GNDK15
GNDK18
GNDK21
GNDK24
GNDK27
GNDK30
GNDK33
GNDK36
GNDK39
GNDJ1
GNDJ4
GNDJ5
GNDJ8
GNDJ11
GNDJ14
GNDJ17
GNDJ20
GNDJ23
GNDJ26
GNDJ29
GNDJ32
GNDJ35
GNDJ38
GNDJ40
GNDH3
GNDH6
GNDH9
GNDH12
GNDH15
GNDH18
GNDH21
GNDH24
GNDH27
GNDH30
GNDH33
GNDH36
GNDH39
GNDD2
GNDD3
GNDD6
GNDD7
GNDD10
GNDD13
GNDD16
GNDD19
GNDD22
GNDD25
GNDD28
GNDD37
GNDD39
GNDC1
GNDC4
GNDC5
GNDC8
GNDC9
GNDC12
GNDC13
GNDC16
GNDC17
GNDC20
GNDC21
GNDC24
GNDC25
GNDC28
GNDC29
GNDC32
GNDC33
GNDC36GNDC38GNDC40GNDB2GNDB3GNDB6GNDB7GNDB10GNDB11GNDB14GNDB15GNDB18GNDB19GNDB22GNDB23GNDB26GNDB27GNDB30GNDB31GNDB34GNDB35GNDB38GNDB39GNDA1GNDA4GNDA5GNDA8GNDA9GNDA12GNDA13GNDA16GNDA17GNDA20GNDA21GNDA24GNDA25GNDA28GNDA29GNDA32GNDA33GNDA36GNDA37GNDA40GNDG1GNDG4GNDG5GNDG8GNDG11GNDG14GNDG17GNDG20GNDG23GNDG26GNDG29GNDG32GNDG35GNDG38GNDG40GNDF2GNDF3GNDF6GNDF9GNDF12GNDF15GNDF18GNDF21GNDF24GNDF27GNDF30GNDF33GNDF36GNDF39GNDE1GNDE4GNDE5GNDE8GNDE11GNDE14GNDE17GND
E20
GNDE23
GNDE26
GNDE29
GNDE32
GNDE35
GNDE38
GNDE40
R40150
R342 10.0K
R4002
37.4
J4C
ASP-134486-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11J31
HB_N12F32
HB_N13E31
HB_N14K35
HB_N15J34
HB_N16F35
HB_N17_CCK38
HB_N18J37
HB_N19E34
HB_N2F23
HB_N20F38
HB_N21E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11J30
HB_P12F31
HB_P13E30
HB_P14K34
HB_P15J33
HB_P16F34
HB_P17_CCK37
HB_P18J36
HB_P19E33
HB_P2F22
HB_P20F37
HB_P21E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
C2
0.1uF
R40160
C1
0.1uF
R480 10.0K
R4
DNI
R4017DNI
R345 10.0K
J4D
ASP-134486-01
DP0_C2M_NC3 DP0_C2M_PC2
DP0_M2C_NC7DP0_M2C_PC6
DP1_C2M_NA23 DP1_C2M_PA22
DP1_M2C_NA3DP1_M2C_PA2
DP2_C2M_NA27 DP2_C2M_PA26
DP2_M2C_NA7DP2_M2C_PA6
DP3_C2M_NA31 DP3_C2M_PA30
DP3_M2C_NA11DP3_M2C_PA10
DP4_C2M_NA35 DP4_C2M_PA34
DP4_M2C_NA15DP4_M2C_PA14
DP5_C2M_NA39 DP5_C2M_PA38
DP5_M2C_NA19DP5_M2C_PA18
DP6_C2M_NB37 DP6_C2M_PB36
DP6_M2C_NB17DP6_M2C_PB16
DP7_C2M_NB33 DP7_C2M_PB32
DP7_M2C_NB13DP7_M2C_PB12
DP8_C2M_NB29 DP8_C2M_PB28
DP8_M2C_NB9DP8_M2C_PB8
DP9_C2M_NB25 DP9_C2M_PB24
DP9_M2C_NB5DP9_M2C_PB4
GBTCLK0_M2C_ND5GBTCLK0_M2C_PD4
GBTCLK1_M2C_NB21GBTCLK1_M2C_PB20
R40110
R4018DNI
R5
DNI
R4012DNI
J4A
ASP-134486-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16G19
LA_N17D21
LA_N18_CCC23
LA_N19H23
LA_N2H8
LA_N20G22
LA_N21H26
LA_N22G25
LA_N23D24
LA_N24H29
LA_N25G28
LA_N26D27
LA_N27C27
LA_N28H32
LA_N29G31
LA_N3G10
LA_N30H35
LA_N31G34
LA_N32H38
LA_N33G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16G18
LA_P17D20
LA_P18_CCC22
LA_P19H22
LA_P2H7
LA_P20G21
LA_P21H25
LA_P22G24
LA_P23D23
LA_P24H28
LA_P25G27
LA_P26D26
LA_P27C26
LA_P28H31
LA_P29G30
LA_P3G9
LA_P30H34
LA_P31G33
LA_P32H37
LA_P33G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
R40130
R4014DNI
J4E
ASP-134486-01
CLK_DIRB1
CLK0_M2C_NH5CLK0_M2C_PH4
CLK1_M2C_NG3CLK1_M2C_PG2
CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34
GA1D35
PG_C2MD1
PG_M2CF1
PRSNT_M2C_LH2
RES0B40
SCLC30 SDAC31
TCKD29TDID30TDOD31TMSD33TRSTD34
3P3VAUXD32
3P3VD40
3P3VC39
3P3VD36
3P3VD38
12P0VC35
12P0VC37
VADJE39
VADJF40
VADJG39
VADJH40
VIO_B_M2CK40
VIO_B_M2CJ39
VREF_B_M2CK1
VREF_A_M2CH1
J4B
ASP-134486-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12F14
HA_N13E13
HA_N14J16
HA_N15F17
HA_N16E16
HA_N17_CCK17
HA_N18J19
HA_N19F20
HA_N2K8
HA_N20E19
HA_N21K20
HA_N22J22
HA_N23K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12F13
HA_P13E12
HA_P14J15
HA_P15F16
HA_P16E15
HA_P17_CCK16
HA_P18J18
HA_P19F19
HA_P2K7
HA_P20E18
HA_P21K19
HA_P22J21
HA_P23K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
C848
39pF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
QSPI Flash & Reset Circuit
RESET CIRUIT
PLACE NEAR QSPI FLASH
QSPI FLASH
USB_RESET IS ACTIVE HIGH AND IS INVERTED THROUGH THE MAX V SYSTEM CONTROLLER
Input only to AV device cold reset
Input/output to AV device warm reset
PB_COLD_RESETn
HPS_RESETn
WARM_RESETn
PB_WARM_RESETn
MICTOR_RSTn
COLD_RESETn
MAX_QSPI_RSTn
3.3V
3.3V
3.3V3.3V
3.3V3.3V
3.3V
QSPI_SS07
QSPI_CLK7
QSPI_IO37
QSPI_IO27
QSPI_IO17
QSPI_IO07
ENET_HPS_RESETn 20
HPS_RESETn7,19
MICTOR_RSTn7,14,19
RESET_HPS_UARTB_N 29
ENET_DUAL_RESETn 4,21
RESET_HPS_UARTA_N 29
MAX_QSPI_RSTn19
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
26 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
26 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
26 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
U19
N25Q512A83GSF40F
DQ015
DQ18
DQ2/VPP/W#9
DQ3/HOLD#1
C16
S#7
RESET3
DNU14
DNU25
DNU36
DNU411
DNU512
DNU613
DNU714
VSS10
VCC2
R40320.0K
R481
2.00K
1%
C340
0.1uF
R659DNI
R40020.0K
R402 100K
R401
0
S9
PB Switch1 2
R4090
U66
MAX811
GND1
RESET2
VCC4
MR3
C3190.1uF
R399 100K
TP2
R398
4.70K, 1%
U65
MAX811
GND1
RESET2
VCC4
MR3
R408DNI
C3180.1uF
R407DNI
C339
4.7uF
S10
PB Switch1 2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
USB 2.0 OTG , Micro SD Card
PLACE NEAR USB3300
Micro SD / USB INTERFACE
USB 2.0 OTG
USB INTERFACE
Current limit for Rseti of 137k is 1.013A
USB FPGA INTERFACE
FPGA USB
PLACE NEAR FT245RQ USB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4USB_DATA5USB_DATA6USB_DATA7
USB_IDUSB_DP_PUSB_DM_N
USB_CLKUSB_NXTUSB_DIR
USB_STP
USB_RBIAS
USB_XIUSB_XO
USB_DATA[7..0]
USB_CLK
USB_CPEN
USB_VBUS
USB_EXTVBUS
USB_EXTVBUS
USB_RESET_PHY
USB_RESET
USB_RESET USB_RESET_PHY
SD_CLK
SD_CMD
SD_DAT1SD_DAT2SD_CD_DAT3
SD_DAT2SD_CD_DAT3SD_DAT0SD_DAT1SD_CMD
SD_CLK
SD_DAT0
USB_NXTUSB_DIRUSB_STP
USB_FPGA_WR
USB_F_RESET_PHY
USB_FPGA_TXEnUSB_FPGA_RXFn
USB_FPGA_RDnUSB_FPGA_WR
USB_FPGA_RESET
USB_F_DP_PUSB_F_DM_N
USB_FPGA_DATA[7..0]
USB_FPGA_RESET USB_F_RESET_PHY
USB_FPGA_RDn
USB_FPGA_RXFnUSB_FPGA_TXEn
USB_FPGA_DATA1USB_FPGA_DATA2USB_FPGA_DATA3USB_FPGA_DATA4USB_FPGA_DATA5USB_FPGA_DATA6USB_FPGA_DATA7
USB_FPGA_DATA0
5V_F_USB
USB_VDD
USB_VDDA
USB_VDD USB_VDDA
3.3V
5.0V
USB_5.0V
USB_5.0V
USB_5.0V
3.3V
3.3V
3.3V
3.3V
3.3V
USB_FPGA_3.3V
USB_FPGA_5.0V
USB_FPGA_2.5V
USB_FPGA_3.3VUSB_FPGA_2.5VUSB_FPGA_5.0V
USB_FPGA_5.0V
USB_FPGA_5.0V USB_FPGA_2.5V
USB_FPGA_2.5V
USB_FPGA_2.5V
USB_DATA[7..0] 7
USB_CLK 7USB_RESET 19
SD_DAT27SD_CD_DAT37SD_DAT07SD_DAT17SD_CMD7
SD_CLK7
USB_STP 7USB_DIR 7USB_NXT 7
USB_FPGA_DATA[7..0] 8,10
USB_FPGA_RESET 19
USB_FPGA_TXEn 8
USB_FPGA_RXFn 13
USB_FPGA_WR 8
USB_FPGA_RDn 8
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
27 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
27 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
27 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
X1
24MHz13
24
C317
0.1uF
C302
0.1uF
C292
0.1uF
R65 0R72
R33
R52C312
0.1uF
D7 ESD5V3U2U
K1
1
K2
2
A3
C304
1uF
R7110.0K
C301
0.1uF
R67 0
C7
2.2uF
TP3
R42C44
4.7uF
C307
0.1uF
C22
2.2uF
R68
D5 ESD5V3U2U
K1
1
K2
2
A3
C48
4.7uF
R20DNI
C32 30pF
C9 4.7uF
VBUS
D-
D+
ID
J1MICRO_USB_CONN
12345
6 7 8 9
U8
FT245RQ
GND17GND4
DATA030
DATA12
DATA232
DATA38
DATA431
DATA56
DATA67
DATA73
USBDP14USBDM15
RESET#18
OSCO28
RXF#22TXE#21
OSCI27
NC
429
VC
C19
3V
3V
OU
T16
WR11 PWREN#
9
VC
CIO
1
GND_PAD33
NC
05
NC
112
NC
213
NC
325
NC
523
GND20
AGND24
TEST26
RD#10
D6 ESD5V3U2U
K1
1
K2
2
A3
C43
4.7uF
J5
MicroSD_skt
CD/DAT32
CMD3
VSS6
VDD4
CLK5
DAT07
DAT18
DAT21
CAGE9
CAGE10
CAGE11
CAGE12
C299
4.7uF
C311
4.7uF
R64
C305
4.7uF
VBUS
D-
D+
ID
J14MICRO_USB_CONN
12345
6 7 8 9
C303
1uF
C306
0.1uF
R54
C39 30pF
R69
R51
U4
USB3300
VD
D3.3
6
VBUS4
CPEN3
ID5
GND2GND1
DATA024
DATA123
DATA222
DATA321
DATA420
DATA519
DATA618
DATA717
DP7DM8
RESET9
EXTVBUS10
NXT11
DIR12
STP13
CLKOUT14
VD
D1.8
15
VD
D3.3
16
VD
D3.3
25
VD
D1.8
26
VD
DA
1.8
29
XO27
XI28
VD
D3.3
30
REG_EN31
GND_FLAG33
RBIAS32
R19 820,1%C316
0.1uF
R347
5.11K
U2
MAX14523B
IN5
OUT4
ON7 GND
8FLAG2
NC26
SETI3NC1
1
GND_PAD9
R3465.23K
C298
0.1uF
R25
10.0K
R341
137K
1%
C10
0.1uF
R22
12.0K
R41
R26
100K
L93A, 30 Ohm FB
R73
R32DNI
R70
R624.70K, 1%
C11
0.1uF
C49 0.01uFC50 4.7uF
R18 0
R63
R21DNI
R4310.0K
C297
0.1uF
U6
LT3010
OUT1
SENSE2
NC33
GND4
SHDNn5 NC66 NC77 IN8
EPAD9
C308
0.01uF
C300
0.1uF
R27
1M
R53
R60 10.0K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PUSH BUTTON INTERFACE
LED INTERFACE
User I/O, RTC
DIPSW INTERFACE
I2C ADDRESS: 0x40
I2C ADDRESS: 0x50
Note to assembler: Use this resistorto attach to LCD Header (followassembly instructions).
MAX_LOAD
MAX_ERROR
MAX_CONF_DONE
MAX_RESETn
CPU_RESETn
USER_PB_HPS0
USER_PB_HPS1
USER_PB_HPS2
PGM_SEL
PGM_CONFIG
PGM_LED1
PGM_LED2
PGM_LED0
USER_LED_HPS0
USER_LED_HPS3
USER_LED_HPS2
USER_LED_HPS1
USER_LED_FPGA0
USER_LED_FPGA3
USER_LED_FPGA2
USER_LED_FPGA1
USER_DIPSW_FPGA1
USER_DIPSW_HPS1
USER_DIPSW_FPGA3
USER_DIPSW_HPS0
USER_DIPSW_HPS2
USER_DIPSW_FPGA0USER_DIPSW_HPS3
USER_DIPSW_FPGA2
USER_PB_FPGA0
USER_PB_FPGA1
USER_PB_HPS3
I2C_SCL_HPSI2C_SDA_HPS
VBAT
I2C_SCL_DISPI2C_SDA_DISP
I2C_SCL_DISPI2C_SDA_DISP
USER_PB_FPGA2
USER_PB_FPGA3
FMC_PRSNTn
FMCB_PRSNTn
3.3V
2.5V_REG_HPS
3.3V
3.3V
2.5V_REG_FPGA
2.5V_REG_FPGA
3.3V
1.5V_REG_FPGA
3.3V
2.5V_REG_HPS
5.0V
5.0V
3.3V
2.5V_REG_HPS
2.5V_REG_FPGA
2.5V_REG_FPGA
USER_DIPSW_FPGA[3:0]4
CPU_RESETn 13,19
MAX_ERROR19
MAX_LOAD 19
USER_LED_FPGA[3:0]4
MAX_CONF_DONE19
PGM_SEL 19PGM_CONFIG 19MAX_RESETn 19
PGM_LED[2:0]19
USER_PB_FPGA[3:0]4
USER_DIPSW_HPS[3:0]7
USER_PB_HPS[3:0]7
I2C_SDA_HPS 7,20,33
I2C_SCL_HPS 7,20,33
FMC_PRSNTn8,24
USER_LED_HPS[3:0]7
FMCB_PRSNTn6,25
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
28 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
28 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
28 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R374 49.9
R370 49.9
R380 4.70K, 1%
R694 49.9
S12
PB Switch1 2
R687 4.70K, 1%
R689 49.9
R386 4.70K, 1%
B4
HEADER 6X1
D10 Green_LED
R371 49.9
D41 Green_LED
R395 4.70K, 1%
S11
PB Switch1 2
R4
96
10K
S5
PB Switch1 2
R83 0
D16 Green_LED
D40 Green_LED
S8
PB Switch1 2
S1
PB Switch1 2
D11 Green_LED
R435 4.70K, 1%
D14 Green_LED
R103 4.70K, 1%R104 0
S4
PB Switch1 2
R348 49.9
R688 49.9
D38 Green_LED
R390 4.70K, 1%
D9 Green_LED
D15 Green_LED
S3
PB Switch1 2
R381 4.70K, 1%
R691 4.70K, 1%
R376 49.9
D13 Green_LED
D8 Green_LED
R393 4.70K, 1%
R387 4.70K, 1%
R690 49.9
D43 Green_LEDR693 49.9
R384 4.70K, 1%
R372 49.9
R91 49.9
U11
DS1339C
SDA16
SCL1
GND15
VCC3
VBACKUP14
SQW/INT2
NC54
NC65
NC76
NC87
NC98
NC109
NC410 NC311 NC212 NC113
R392 4.70K, 1%
C79 0.1uF
R692 4.70K, 1%
D42 Green_LED
R389 4.70K, 1%
R391 4.70K, 1%
S13
PB Switch1 2
R695 49.9
D12 Green_LED
R501
DNI
D20 Green_LED
R382 4.70K, 1%
S14
PB Switch1 2
R500 0
S2
PB Switch1 2
S6
PB Switch1 2
SW1
TDA08H0SB1
12345678
161514131211109
R373 49.9
J29
LCD_HEADER
123456789
10
R385 4.70K, 1%
R394 4.70K, 1%
R388 4.70K, 1%
S7
PB Switch1 2
R4
95
10K
R4000 B2
HEADER 3X1
U31
MAX3373
VCCIO21
GND2
VL3
VL_IO24VL_IO15
VCCIO18
VCC7
TRI_STATE6
R375 49.9
R369 49.9
B1
2x16 LCD I2C
R383 4.70K, 1%
BT1
12
D39 Red_LED
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
UARTS PORT A and PORT B
UART
DMA_N
PWR_ENA
UARTA_TX_LEDUARTA_RX_LED
DPA_P
RESET_HPS_UARTA_N
RESET_HPS_UARTB_N
DMB_N
PWR_ENB
UARTB_TX_LEDUARTB_RX_LED
DPB_P
3.3V_USB_UARTA
3.3V_USB_UARTA
3.3V
VIO_USB_UARTA
5V_USB_UARTA
3.3V_USB_UARTA VIO_USB_UARTA 5V_USB_UARTA
5V_USB_UARTA
5V_USB_UARTB
3.3V_USB_UARTB
3.3V_USB_UARTB
3.3V
VIO_USB_UARTB
5V_USB_UARTB
3.3V_USB_UARTB VIO_USB_UARTB 5V_USB_UARTB
RESET_HPS_UARTA_N26
UARTA_RX7UARTA_TX7
RESET_HPS_UARTB_N26
UARTB_RX7UARTB_TX7
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
29 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
29 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
29 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R494220
C82
39pF
R136 10.0K
TP9
J23
CON2
12
TP1
C146
2.2uF
XJ2
881545-2
XJ3
881545-2 C120
39pF
D21Green_LED
R118 0
R141DNI
R133 0
L11
742792780
C84
4.7uF
R441220
C83
39pF
C105
2.2uF
C121
39pF
C134
0.1uF
C128
0.1uF
C126
0.1uF
R119DNI
C86
2.2uF
C87
0.1uF
C102
0.1uF
R140 0
C122
4.7uF
D23Green_LED
R112 10.0K
R135
4.70K, 1%
U25
FT232R
VCCIO1RXD
2
RI3
GN
D1
4
NC35
DSR6
DCD7
CTS8
CBUS49
CBUS210
USBDP14
NC513NC412
CBUS311
GN
D2
17
USBDM15
3V3OUT16
RESET18
VCC19
CBUS022 NC2
23
AG
ND
24
CBUS121
GN
D3
20
NC125
OSCO28
NC629
TXD30
DTR31
RTS32
OSCI27
TE
ST
26
EP
AD
_G
ND
33
C125
2.2uF
R139 10.0K
L15
742792780
U20
TPD4S012DRYR
VB
US
6
ID3
D+
1
D-
2
NC
5G
ND
4
U32
TPD4S012DRYR
VB
US
6
ID3
D+
1
D-
2
NC
5G
ND
4
R117 10.0K
C94
0.1uF
J30
CON2
12
U36
FT232R
VCCIO1RXD
2
RI3
GN
D1
4
NC35
DSR6
DCD7
CTS8
CBUS49
CBUS210
USBDP14
NC513NC412
CBUS311
GN
D2
17
USBDM15
3V3OUT16
RESET18
VCC19
CBUS022 NC2
23A
GN
D24
CBUS121
GN
D3
20
NC125
OSCO28
NC629
TXD30
DTR31
RTS32
OSCI27
TE
ST
26
EP
AD
_G
ND
33
J27USB MINI-B
12345
6 7
D22Green_LED
R108 0
D24Green_LED
J22USB MINI-B
12345
6 7
R493220
R442220
R115
4.70K, 1%
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
On-Board USB Blaster II FPGA USB INTERFACE
PLACE NEAR MAX II (U14)
JTAG INTERFACE
PLACE NEAR CY7C68013A
MAX V USB INTERFACE
C_USB_MAX_TDOC_USB_MAX_TMS
C_USB_MAX_TCK
C_USB_MAX_TDI
FX2_D_NFX2_D_P
FX2_WAKEUPVBUS_5V
VBUS_5V
RESn_JTAG_TXJTAG_TX
FX2_PD4FX2_PD3
FX2_PD0FX2_PD1FX2_PD2
FX2_PD5FX2_PD6FX2_PD7
24M_XTALIN24M_XTALOUT
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
USB_B2_CLK
FX2_RESETn
USB_B2_DATA[7:0]
USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESETnUSB_OEnUSB_RDnUSB_WRn
FX2_SDA MAX_SDA
RESn_SC_RXSC_RX
RESn_SC_TXSC_TX
RESn_JTAG_RXJTAG_RX
JTAG_BLASTER_TDO
JTAG_TMSJTAG_BLASTER_TDI
JTAG_TCK
USB_DISABLEnFX2_FLAGCFX2_FLAGB
FX2_WAKEUP
FX2_SLWRnFX2_SLRDn
FX2_FLAGA
FX2_SCLFX2_SDA
FX2_RESETn
USB_SCLUSB_SDAUSB_FULLUSB_EMPTY
FACTORY_STATUSM570_CLOCK
FACTORY_REQUEST
FACTORY_REQUEST JTAG_BLASTER_TDOJTAG_BLASTER_TDIJTAG_TMSJTAG_TCK
C_JTAG_TDOC_JTAG_TDIC_JTAG_TMSC_JTAG_TCK
M570_PCIE_JTAG_EN
FX2_PD2FX2_PD0
FX2_PD3FX2_PD1
JTAG_BLASTER_TDI
USB_CFG[11:0]
C_USB_MAX_TDI
USB_B2_CLK
C_USB_MAX_TMS
MAX_SDA
C_USB_MAX_TCK
C_USB_MAX_TDO
FX2_RESETn
EXTRA_SIG[2:0]
FX2_FLAGC
FX2_PA3
FX2_PA2
FX2_PA4
FX2_PA7
FX2_PB4
FX2_PB7
FX2_FLAGA
FX2_PB5
FX2_FLAGB
FX2_PA1
FX2_PA6
FX2_PB0
FX2_PB2
USB_DISABLEn
FX2_SLWRn
JTAG_TX
M570_CLOCKUSB_CFG7
FX2_PB6
FX2_SCL
FX2_PB1FX2_PB3
FX2_PD4FX2_PD6
C_JTAG_TCK
FX2_SLRDn
FX2_PA5FX2_PD5FX2_PD7
C_JTAG_TDIC_JTAG_TMSC_JTAG_TDO
JTAG_RXFACTORY_REQUEST
USB_RESETnUSB_OEnUSB_RDnUSB_WRnFACTORY_STATUS
USB_CFG5
SC_RXSC_TX
USB_CFG3
USB_CFG4
USB_CFG6EXTRA_SIG1
USB_CFG2USB_CFG9
USB_CFG1USB_B2_DATA2
USB_B2_DATA0USB_B2_DATA1
USB_B2_DATA3USB_B2_DATA4
USB_B2_DATA7USB_B2_DATA5USB_B2_DATA6
RSTUSB_CFG8
TRSTUSB_FULLUSB_EMPTYUSB_CFG11USB_SCLUSB_SDAEXTRA_SIG2USB_CFG10USB_CFG0
M570_PCIE_JTAG_EN
EXTRA_SIG0
C_USB_MAX_TDI
C_USB_MAX_TMSC_USB_MAX_TCK
C_USB_MAX_TDO
3.3V3.3V
3.3V3.3V
1V83.3V
1V8
3.3V
3.3V
1.5V_REG_HPS
2.5V_REG_HPS
3.3V
1V8
1.5V_REG_HPS
1.5V_REG_HPS
USB_B2_DATA[7:0]4
USB_FULL4USB_EMPTY4
USB_SDA4
USB_RESETn4USB_OEn4USB_RDn4USB_WRn4
JTAG_BLASTER_TDO14
JTAG_TMS14JTAG_TCK14
JTAG_BLASTER_TDI14
USB_DISABLEn14
USB_SCL4
FACTORY_STATUS19M570_CLOCK19
USB_B2_CLK4,19
FACTORY_REQUEST19
M570_PCIE_JTAG_EN19
USB_CFG[11:0]19
EXTRA_SIG[2:0]19
TRST 19RST 19
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
30 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
30 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
30 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R315 DNI
Y7
24.00MHz
1 3
24
R6650R652 56.2
C825
0.1uF
R3341M
C837
0.1uF
R670 1.00K
R682 0 MAX IICONFIGURATION
U56D
EPM570GF100
IO2/GCLK2pF8
IO2/GCLK3pE10
IO1/DEV_CLRnK9
IO1/DEV_OEJ7
IO1/GCLK0pE2
IO1/GCLK1pE1
TCKH3 TDIH2
TMSJ1
TDOJ2
R685 10.0K
R683 0
R662 0
R684 0
R666 0
R6610
R362 1.00K
MAX IIPOWER
U56A
EPM570GF100
GNDINTC5
GNDINTF5 GNDINTE6
GNDIOD5
GNDIOG7
GNDIOD7
GNDIOG5 GNDIOF6 GNDIOE5
GNDINTH5
VCCINTC6
VCCINTE7
VCCINTH6VCCINTF4
VCCIO2F7VCCIO2D6VCCIO2D4
VCCIO1E4
VCCIO1G4
VCCIO1G6
D33
Green_LED
R673 1.00KC827
0.1uF
C826
0.1uF
MAX IIBANK 2
U56C
EPM570GF100
IO_B2_A1A1
IO_B2_A10A10
IO_B2_A2A2
IO_B2_A3A3
IO_B2_A4A4
IO_B2_A7A7
IO_B2_B8B8
IO_B2_D10D10
IO_B2_D9D9
IO_B2_A9A9
IO_B2_C7C7
IO_B2_B2B2
IO_B2_B3B3
IO_B2_B4B4
IO_B2_B5B5
IO_B2_B9B9
IO_B2_C9C9
IO_B2_C8C8
IO_B2_B7B7
IO_B2_B10B10
IO_B2_C3C3
IO_B2_C4C4
IO_B2_A6A6
IO_B2_F10F10
IO_B2_F9F9
IO_B2_D8D8
IO_B2_E8E8
IO_B2_C10C10
IO_B2_B6B6
IO_B2_E9E9
IO_B2_A5A5IO_B2_A8A8
IO_B2_G10G10
IO_B2_G8G8
IO_B2_G9G9
IO_B2_H10H10IO_B2_H9H9
IO_B2_J10J10
R679 2.00K
R6600
C2874.7nF
R651 56.2
C835
0.1uF
U61
CY7C68013A_VFBGA
RDY0A1
RDY1B1
XTALINC1
AVCCD1
DMINUSE1
AGNDF1
VCCG1
GNDH1
PD7A2
CLKOUTB2
XTALOUTC2
AVCCD2
DPLUSE2
AGNDF2
IFCLKG2
RESERVEDH2
PD5A3PD4B3
PD6C3
SCLF3
SDAG3
PB0H3
GNDA4
GNDB4
GNDC4
PB1F4
PB3G4PB2H4
VCCA5
VCCB5
PB6F5PB5G5PB4H5
PD3A6PD2B6
PA7C6
PA4F6
PA1G6
PB7H6
PD1A7
WAKEUPB7
PA6C7
GNDD7
VCCE7
PA3F7
CTL1G7CTL0H7
PD0A8
RESETB8
PA5C8
GNDD8
VCCE8
PA2F8
PA0G8
CTL2H8
VCCC5
MAX IIBANK 1
U56B
EPM570GF100
IO_B1_B1B1
IO_B1_C1C1
IO_B1_C2C2
IO_B1_D1D1
IO_B1_D2D2
IO_B1_D3D3
IO_B1_E3E3
IO_B1_F1F1
IO_B1_F2F2
IO_B1_F3F3
IO_B1_G1G1
IO_B1_G2G2
IO_B1_G3G3
IO_B1_H1H1
IO_B1_H4H4
IO_B1_H7H7
IO_B1_H8H8
IO_B1_J3J3
IO_B1_J4J4
IO_B1_J5J5
IO_B1_J6J6
IO_B1_J8J8
IO_B1_J9J9
IO_B1_K1K1
IO_B1_K10K10
IO_B1_K2K2
IO_B1_K3K3
IO_B1_K4K4
IO_B1_K5K5
IO_B1_K6K6
IO_B1_K7K7
IO_B1_K8K8
R672 1.00KC828
0.1uF
C830
0.1uFR650 56.2
J50USB MINI-B
12345
67
R645 DNIR377 1.00K
C246 0.1uF
U57
MAX811
GND1
RESET2
VCC4
MR3
R6640
C836
0.1uF
V81V77
U63
TPD2EUSB30
D-2D+1
GND3
D36
Green_LED
R264100K
R669 1.00K
C832
0.1uF
R671 1.00K
C841
0.1uF
V80
C829
0.1uF
C842
0.1uF
C267
12pF
D35
Green_LED
C833
0.1uF
R677 2.00K
D34
Green_LED
J51
DNI
11
33
55
77
22
44
66
88
99
1010
C843
0.1uF
C831
0.1uF
C266
12pF
R653 56.2
R686
20.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA Power Monitor 1
GND pad
LTC2977Address SelectPWRMON2 = 7'h5E
SCL_PMSDA_PM
PM_ALERTBPM_PWRGD
PM_CNTL0PM_CNTL1PM_RSTn
PM_ALERTBPM_PWRGD
1.5V_FPGA_VDACP2 PM_SHARE_CLK
PM2_ASEL1
PM_CNTL1PM_CNTL0
SDA_PM
PM_SHARE_CLK
SCL_PM
PM2_FAULTB10
PM2_FAULTB00
PM2_FAULTB11
PM_RSTn
PM2_FAULTB01
PM2_ASEL0PM2_ASEL1
PM2_FAULTB10
PM2_FAULTB00
PM2_FAULTB11
PM2_FAULTB01
2.5V_FPGA_V_0_P
1.1V_VCC_V_P
1.5V_FPGA_I_P1.5V_FPGA_I_N
1.1V_VCC_V_N
2.5V_FPGA_I_N2.5V_FPGA_I_P
1.1V_VCC_I_N
1.5V_FPGA_V_P
1.1V_VCC_I_P
1.5V_FPGA_V_N
2.5V_FPGA_V_0_N
TSENSE_FAN_CNTL
2.5V_FPGA_RUN
1.5V_FPGA_RUN
1.1V_FPGA_RUN
1.1V_FPGA_VDACP4
1.1V_FPGA_VDACP4
2.5V_FPGA_VDACP01.5V_FPGA_VDACP2
SDA_PMSCL_PM
SDA_PMSCL_PM
2.5V_FPGA_P
2.5V_FPGA_N
1.5V_FPGA_P
1.5V_FPGA_N
1.1V_VCC_P
1.1V_VCC_N
PM2_ASEL0
2.5V_FPGA_VDACP0
VAR_VCC_V_PVAR_VCC_V_N
VAR_VCC_I_NVAR_VCC_I_P
VAR_VCC_N
VAR_VCC_P
VAR_FPGA_VDACP6
VAR_FPGA_VDACP6
VAR_FPGA_RUN
12V
3.3V_PM_FPGA
12V
1.1V_VCC
1.1V_REG_VCC
1.5V_FPGA
1.5V_REG_FPGA
2.5V_FPGA
2.5V_REG_FPGA
3.3V_PM_FPGA
3.3V_PM_FPGA
VAR_VCCIOP
VAR_VCCIO
SCL_PM32,33
SDA_PM32,33
PM_PWRGD32,33
PM_CNTL032,33
PM_CNTL132,33
PM_RSTn32,33
PM_ALERTB32,33
PM_SHARE_CLK32,33
OVERTEMP 19
2.5V_FPGA_RUN37
1.5V_FPGA_RUN36
1.1V_FPGA_RUN35
2.5V_FPGA_VDACP0371.5V_FPGA_VDACP2361.1V_FPGA_VDACP435
I2C_SDA 10,19,32
I2C_SCL 10,19,32
VAR_FPGA_VDACP635
VAR_FPGA_RUN35
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
31 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
31 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
31 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C270 0.1uFR296 1K
R316 1K
C273 0.1uF
C274 0.1uF
V4
SENSE_PAD
RSNS1
SNS2
R317 1K
R30610K
R298 1K
R300 1K
C268 0.1uF
R301 1K
C839
0.1uf
C285 0.1uF
C278 0.1uF
C286
0.1uf
R294 1K
C271 0.1uF
C284 0.1uF
V78
SENSE_PAD
RSNS1
SNS2
R297 1K
R312
0
C289 0.1uF
Q1
FDV305N
C279 0.1uF
C288 0.1uF
R326 1K
R299 1K
V72
SENSE_PAD
RSNS1
SNS2
R31910K
R31810K
V1
SENSE_PAD
RSNS1
SNS2
C847
0.1uf
J20
22_23_2021
12
V67
SENSE_PAD
RSNS1
SNS2
R325 1K
R332 1K
C272 0.1uF
R295 1K
V71
SENSE_PAD
RSNS1
SNS2
R302
10K
R336 1K
C290
0.1uf
C269 0.1uF
R333 1K
B3
FAN_2pin_Conn
V79
SENSE_PAD
RSNS1
SNS2
C281 0.1uF
C275 0.1uF
R313 10KR307 10K
U64
LTC2977
VOUT_EN48
VOUT_EN59
VOUT_EN610
VOUT_EN711
VIN_EN12
NC13
VIN_SNS14
VPWR15
VDD33_OUT16
VDD33_IN17
VDD2518WP
19 PWRGD20SHARE_CLK
21
WDI/RESET22
FAULTB0023
FAULTB0124
FAULTB1025
FAULTB1126
SDA27 SCL28
ALERTB29
CONTROL030
CONTROL131
ASEL032
ASEL133
REFP34
REFM35VSENSEP0
36
VSENSEM037
VDACM038VDACP039
VDACP140
VDACM141
VSENSEP142
VSENSEM143
VDACP244
VDACM245
VSENSEP246
VSENSEM247
VSENSEP348
VSENSEM349
VDACP350
VDACM351
VSENSEP452
VSENSEM61
VSENSEP72
VSENSEM73
VOUT_EN04
VOUT_EN15
VOUT_EN26
VOUT_EN37
VSENSEM453
VDACM454VDACP455
VDACP556
VDACM557
VDACM658VDACP659
VDACP760
VDACM761
VSENSEP562
VSENSEM563
VSENSEP664
E-PAD65
C280 0.1uF
R335 1K
R327
10K
V68
SENSE_PAD
RSNS1
SNS2
R308
0
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA Power Monitor 2
GND pad
LTC2977Address SelectPWRMON2 = 7'h62
SDA_PMSCL_PM
1.1.5V_GXB_V_P
1.5V_VCCD_V_P
1.15V_VCCT_I_P1.15V_VCCT_I_N
1.5V_VCCD_V_N
1.15V_GXB_I_N1.15V_GXB_I_P
1.5V_VCCD_I_N
1.15V_VCCT_V_P
1.5V_VCCD_I_P
1.15V_VCCT_V_N
1.15V_GXB_V_N
1.15V_GXB_RUN
1.15V_VCCT_RUN
1.5V_VCCD_VCCH_RUN
PM3_FAULTB10
PM3_FAULTB00
PM3_FAULTB11
PM3_FAULTB01
1.5V_VCCD_VCCH_VDACP4
SCL_PMSDA_PM
PM_ALERTBPM_PWRGD
PM_CNTL0PM_CNTL1PM_RSTn
1.15V_GXB_VDACP0
PM_ALERTBPM_PWRGD
1.15V_VCCT_VDACP2
PM3_ASEL1
1.15V_GXB_P
1.15V_GXB_N
1.15V_VCCT_P
1.15V_VCCT_N
1.5V_VCCD_P
1.5V_VCCD_N
PM_SHARE_CLK
1.5V_VCCD_VCCH_VDACP4
1.15V_GXB_VDACP01.15V_VCCT_VDACP2
PM_CNTL1PM_CNTL0
SDA_PM
PM_SHARE_CLK
SCL_PM
PM3_FAULTB10
PM3_FAULTB00
PM3_FAULTB11
PM_RSTn
PM3_FAULTB01
PM3_ASEL0PM3_ASEL1
SDA_PM
PM3_ASEL0PM3_ASEL1
SCL_PM3.3V_PM_FPGA
12V
3.3V_PM_FPGA3.3V_PM_FPGA
1.15V_GXB
1.15V_VCCT
1.5V_VCCD_VCCH
1.15V_VCCTP
1.15V_GXBP
1.5V_VCCD_VCCHP
SCL_PM31,33
SDA_PM31,33
PM_PWRGD31,33
PM_CNTL031,33
PM_CNTL131,33
PM_RSTn31,33
PM_ALERTB31,33
PM_SHARE_CLK31,33
1.15V_GXB_RUN42
1.15V_VCCT_RUN42
1.5V_VCCD_VCCH_RUN42
1.15V_GXB_VDACP0421.15V_VCCT_VDACP2421.5V_VCCD_VCCH_VDACP442
I2C_SDA 10,19,31
I2C_SCL 10,19,31
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
32 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
32 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
32 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C210
0.1uf
C211
0.1uf
R219
10K
V74
SENSE_PAD
RSNS1
SNS2
C220 0.1uF
V3
SENSE_PAD
RSNS1
SNS2
R229
0
C235 0.1uF
R245
10K
C236 0.1uF
R220 1K
R22510K
R250 1K
R246 1K C232 0.1uF
R240 10K
C226 0.1uF
R235 1K
R233
0
R247 1K
R22410K
R226 1K
V6
SENSE_PAD
RSNS1
SNS2
C807
0.1uf
C209
0.1uf
C216 0.1uF
C229 0.1uF
C233 0.1uF
C231 0.1uF
C212 0.1uF
V73
SENSE_PAD
RSNS1
SNS2
R22810K
R230 1K
U54
LTC2977
VOUT_EN48
VOUT_EN59
VOUT_EN610
VOUT_EN711
VIN_EN12
NC13
VIN_SNS14
VPWR15
VDD33_OUT16
VDD33_IN17
VDD2518WP
19 PWRGD20SHARE_CLK
21
WDI/RESET22
FAULTB0023
FAULTB0124
FAULTB1025
FAULTB1126
SDA27 SCL28
ALERTB29
CONTROL030
CONTROL131
ASEL032
ASEL133
REFP34
REFM35VSENSEP0
36
VSENSEM037
VDACM038VDACP039
VDACP140
VDACM141
VSENSEP142
VSENSEM143
VDACP244
VDACM245
VSENSEP246
VSENSEM247
VSENSEP348
VSENSEM349
VDACP350
VDACM351
VSENSEP452
VSENSEM61
VSENSEP72
VSENSEM73
VOUT_EN04
VOUT_EN15
VOUT_EN26
VOUT_EN37
VSENSEM453
VDACM454VDACP455
VDACP556
VDACM557
VDACM658VDACP659
VDACP760
VDACM761
VSENSEP562
VSENSEM563
VSENSEP664
E-PAD65
R248 1K
V2
SENSE_PAD
RSNS1
SNS2
R241 1K
R234 10K
R236 1K
R221 1K
C234 0.1uFR249 1K
C227 0.1uF
V5
SENSE_PAD
RSNS1
SNS2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HPS Power Monitor
GND pad
these GND connections toeach VSENSEMx pinneeds to be placed closeto a GND pin of the BGA!
LTC2977Address SelectPWRMON1 = 7'h5C
I2C Interface
1.1V_HPS_V_P
1.1V_HPS_VDACP0
PM_ALERTBPM_PWRGD
2.5_HPS_VDACP4
1.5V_HPS_VDACP2
1.1V_HPS_I_N1.1V_HPS_I_P
2.5V_HPS_I_P
1.1V_HPS_V_N
PM_ALERTBPM_PWRGD
PM_CNTL0PM_CNTL1PM_RSTn
PM_SHARE_CLK
PM_PWRGD
SDA_PMSCL_PM
PM1_ASEL0
PM_RSTn
PM_ALERTBPM_CNTL1
SCL_PMSDA_PM
1.1V_HPS_VDACP0
2.5_HPS_VDACP41.5V_HPS_VDACP2
PM_SHARE_CLK
PM1_ASEL1
PM_SHARE_CLK
SCL_PM
PM1_FAULTB10
PM1_FAULTB00
PM1_FAULTB11
PM_RSTn
PM1_FAULTB01
SDA_PMPM1_ASEL0PM1_ASEL1
PM_CNTL1PM_CNTL0
SDA_PMSCL_PM
3.3_HPS_VDACP6
3.3_HPS_VDACP6
EN_1.5V_HPS
EN_1.1V_HPS
EN_2.5V_HPS
EN_3.3V_HPSEN_1.5V_HPSEN_1.1V_HPS
EN_2.5V_HPSEN_3.3V_HPS
PM1_FAULTB10
PM1_FAULTB00
PM1_FAULTB11
PM_ALERTB
PM1_FAULTB01
1.1V_HPS_P
1.1V_HPS_N
1.5V_HPS_P
1.5V_HPS_N
2.5V_HPS_P
2.5V_HPS_N
3.3V_HPS_P
3.3V_HPS_N
PM_CNTL0PM_CNTL1
1.5V_HPS_V_P
3.3V_HPS_V_P2.5V_HPS_I_N
3.3V_HPS_V_N
1.5V_HPS_I_N1.5V_HPS_I_P
3.3V_HPS_I_N
2.5V_HPS_V_P
3.3V_HPS_I_P
2.5V_HPS_V_N
1.5V_HPS_V_N
12V
3.3V_PM_HPS
3.3V_HPS
3.3V_REG_HPS
2.5V_HPS
2.5V_REG_HPS
1.5V_HPS
1.5V_REG_HPS
1.1V_HPS
1.1V_REG_HPS
3.3V_PM_HPS
SCL_PM31,32 SDA_PM31,32
1.1V_HPS_VDACP0411.5V_HPS_VDACP2392.5_HPS_VDACP438
PM_PWRGD31,32
PM_CNTL031,32
PM_CNTL131,32
PM_RSTn31,32
PM_ALERTB31,32
PM_SHARE_CLK31,32
3.3_HPS_VDACP640
EN_1.1V_HPS41EN_1.5V_HPS39EN_2.5V_HPS38EN_3.3V_HPS40
I2C_SDA_HPS 7,20,28I2C_SCL_HPS 7,20,28
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
33 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
33 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
33 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R176 1K
R21310K
R21110K
U50
LTC2977
VOUT_EN48
VOUT_EN59
VOUT_EN610
VOUT_EN711
VIN_EN12
NC13
VIN_SNS14
VPWR15
VDD33_OUT16
VDD33_IN17
VDD2518WP
19 PWRGD20SHARE_CLK
21
WDI/RESET22
FAULTB0023
FAULTB0124
FAULTB1025
FAULTB1126
SDA27 SCL28
ALERTB29
CONTROL030
CONTROL131
ASEL032
ASEL133
REFP34
REFM35VSENSEP0
36
VSENSEM037
VDACM038VDACP039
VDACP140
VDACM141
VSENSEP142
VSENSEM143
VDACP244
VDACM245
VSENSEP246
VSENSEM247
VSENSEP348
VSENSEM349
VDACP350
VDACM351
VSENSEP452
VSENSEM61
VSENSEP72
VSENSEM73
VOUT_EN04
VOUT_EN15
VOUT_EN26
VOUT_EN37
VSENSEM453
VDACM454VDACP455
VDACP556
VDACM557
VDACM658VDACP659
VDACP760
VDACM761
VSENSEP562
VSENSEM563
VSENSEP664
E-PAD65
C176 0.1uF
R174 1K
R185 1K
R172 1K
C182 0.1uF
R171 1K
C177 0.1uF
C196
0.1uf
R177 1K
R173 1K
C185 0.1uF
C179 0.1uF
R190 1K
C181 0.1uF
R196 1K
C178 0.1uF
C197 0.1uF
R175 1K
R20910K
V34
SENSE_PAD
RSNS1
SNS2
C184 0.1uF
R624
0
V37
SENSE_PAD
RSNS1
SNS2
C200 0.1uF
R625
0
V33
SENSE_PAD
RSNS1
SNS2
J36
2x6HDR
11
22
33
44
55
66
77
88
99
1010
1212
1111
C199
0.1uf
C175 0.1uF
V35
SENSE_PAD
RSNS1
SNS2
C201 0.1uF
R21210K
C192 0.1uF
R208
10K
R20410K
R21410K
R20510K
V32
SENSE_PAD
RSNS1
SNS2
R186 1K
R189 1K
V36
SENSE_PAD
RSNS1
SNS2
C783
0.1uf
C180 0.1uF
V43
SENSE_PAD
RSNS1
SNS2
R194 1K
R20710K
C191 0.1uF
C190 0.1uF
V44
SENSE_PAD
RSNS1
SNS2
R191 1K
R20310K
R21010K
R170 1K
C204
0.1uf
R195 1K
R20610K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 1 - DC Input & 12V, 3.3V Output
POWER LED
19VDC Input
LTC3855_S2PLTC3855_S2N
PG_12V
VFB2
INTVCC_1
INTVCC_1
VFB2
LTC3855_S1N
INTVCC_1
3.3V_SHDNn
DIFFOUT
12V_SHDNn
DIFFOUT
3.3V_SHDNn12V_SHDNn
LTC3855_S1P
PWR1_EXTVCC
5.0V
DC_IN
12V_REG
3.3V
DC_IN
3.3V
DC_INPUT
DC_IN DC_IN
DC_IN
3.3V
12V
12V_ATX
12V_REG
12V_ATX
12V_ATX12V_ATXTitle
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
34 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
34 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
34 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R309100K
C70822uF25V
D31
MMBD1205
D45
CMDSH-3
R570
2.55K
drain-tab
Q7RJK0305DPB
4
5
31 2
U48
FDMC8878
5
123
4
R676
1.00K
R58320.0K
L21
0.68uH12
V70
SENSE_PAD
RSNS1
SNS2
Q6
FDMC8878
5
123
4 C753
22pF
gnd-pad
U71
LTC3855EUJ
TK/SS11 ITH12
VFB13
SGND14
VFB25
ITH26
TK/SS27
SENSE2+8
SENSE2-9
PGOOD217
NC18
PGOOD116
TG220
BOOST221
PGND222
BG223
EXTVCC24 INTVCC25
PGND128
SW219
DIFFP10
DIFFN11
DIFFOUT12
RUN213
ILIM114
ILIM215
VIN26
BG127
BOOST129
TG130
SW131
CLKOUT32 PHSASMD33 MODE/PLLIN34 FREQ35
ITEMP236
ITEMP137 RUN138
SENSE1+39
SENSE1-40
SGND241
C65622uF25V
C168
47uF35V
C709 0.1uF
J34CONN JACK PWR
3
21
C657
4.7uF
C556
68uF25V
U60
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
R5843.09K
J33
ATX-POWER_4P
COM1
COM2
+12V3
+12V4
R55257.6K
R321100K
drain-tab
Q8RJK0301DPB
4
5
31 2
L25
1.5uH12
R32220.0K
R544
DNI
V46
SENSE_PAD
RSNS1
SNS2
R543 3.92K
C635 0.1uF
drain-tab
Q10RJK0305DPB
4
5
31 2
U47
FDMC8878
5
123
4
V45
SENSE_PAD
RS
NS
1S
NS
2
R56911.3KC636
0.1uF
C687
22pF
C163
68uF25V
U72
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
drain-tab
Q2
RJK0305DPB4
5
31 2
D37
BLUE LED
R58220.0K
D44CMDSH-3
C173
68uF25V
R548100K
R561215.0K
R314100K
R581169.0K
C752
1000pF
R579
52.3K
C198
47uF35V
C208
330uF
10V
drain-tab
Q9
RJK0301DPB4
5
31 2
U70
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
U58
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
Q5
FDMC8878
5
123
4
C18922uF25V
C723
0.1uF
SW5SW SLIDE-4P2T
1
239
8
7
4
56
10
1211
R32020.0K
R5774.02K
C724
82pF
R57811.5K
V69
SENSE_PAD
RS
NS
1S
NS
2
C195100uF
6.3v
C658
1000pF
C17422uF25V
C659100pF
R323 100K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 2 1.15V FPGA CORE
Vout=1.15V
1.2V 953k P02-16417R1.5V 549k P02-14713R (0603)1.8V 383k P02-14133R + P02-15998R2.5V 226k P02-14130R3.3V 154k P02-15947R
744308033
P02-11401RRESISTORS • RES,1.15K OHMS,1.0%,1/16W,0402
P02-14067RRESISTORS • RES - 665 OHMS 1.0% 1/16W 0402
A5_VCC_TRACK
SW_VCC
BST
VFBDIFF_O
SNSAP
ITH
1.1V_REG
ITH
VFB
DIFF_O
INTVCC
1.1V_REG
3.3V_SET
2.5V_SET
1.8V_SET
1.5V_SET
1.2V_SET
SW_VCCP
SW_VCCP
INTVCC
VFB
P2_EXT
LTC3866_1.1V_RUN
1.1V_VCC 1.15V_VCCP
12V
1.1V_VCC1.1V_REG_VCC
12V
12V
VAR_VCCIOVAR_VCCIOP
1.1V_VCC
3.3V
3.3V
1.1V_FPGA_RUN31
VAR_FPGA_VDACP631
VAR_FPGA_RUN
31
1.1V_FPGA_VDACP431
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
35 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
35 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
35 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C330
10uF 25V
R632 137K1%
C327
0.1uf
C218
100uF6.3V
C809
220pF
R2181.15K
LTC3866
U74
SNSAP8
ILIM9
CLKOUT10
PGND11
BG12SW13
ITH1
VFB2
DIFFOUT3
DIFFN4 DIFFP5
SNSDP6
ITEMP19
EXTVCC18
VIN17
INTVCC16
BOOST15
TG14
SGND25
TK_SS24
RUN23
FREQ22
MODE_PLLIN21
PGOOD20
SNSM7
C225
22uF4V
U9B
LTM8025
GNDA5
GNDA6
GNDA7
GNDB5
GNDB6
GNDB7
GNDC5
GNDC6
GNDC7
GNDD5
GNDE4
GNDE5
GNDE6
GNDE7
GNDF4GNDF5
GNDF7
GNDG1
GNDF6
GNDG2
GNDG3
GNDD6
GNDG4
GNDD7
GNDG6
GNDH6
GNDJ5
GNDJ6
GNDK5
GNDK6
GNDL7
GNDE3 GNDE2 GNDE1
GNDF3
GNDF2
GNDF1
R63810K
R44953K
R5682K
C224
22uF4V
C82422uF25V
1210
R55549K
V75
SENSE_PAD
RS
NS
1S
NS
2
R641
15K
1%
C321
2.2uF
R217665
C78422uF25V
1210
R1020.003
R45226K
D46
CMDSH-3
L34
3A, 30 Ohm FB
R633 10.0K
L27
0.22uH12
R41240.2K
R634 0
C7860.1uf
C808
1500pF
R6263.09K
C785
4.7uF
U9A
LTM8025
VOUT1A1
VOUT2A2
VOUT3A3
VOUT4A4
VOUT7B3
VOUT8B4
VOUT5B1
VOUT6B2
BIASH5
ADJK7
RUNN/SSL5
VOUT9C1
VOUT10C2
VOUT11C3
VOUT12C4
AUXG5
PGOODJ7
RTG7
SHAREH7
SYNCL6
VIN1J1
VIN2J2
VIN3J3
VIN4K1
VIN5K2
VIN6K3
VOUT14D2
VOUT16D4
VOUT13D1
VOUT15D3
VIN7L1
VIN8L2
VIN9L3
R639
16.2K
C8030.22uF
C21522uF25V
R4140
drain-tab
Q4
RJK0305DPB4
5
31 2
C219
470uF6.3V
R411215.0K
XJ7
881545-2
J6
2x5Header
11
33
55
77
22
44
66
88
99
1010
drain-tab
Q3
RJK0301DPB4
5
31 2
C223
22uF4V
C395
100uF6.3V
C806
0.1uF
V76
SENSE_PAD
RS
NS
1S
NS
2
C214
100uF6.3V
R57300K
R640215.0K
R46154K
R410 10.0K
R2320.001
C326
10uF 25V
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 3 - 1.5V FPGA
CAD Note:Regulator input capsPlace near regulator controller
Design Note:DNI for ES device
Cad Note:1 overlapping pad
Design Note:Ith is tied to INTVCC forinternal compensation
CAD Note:Overlap R182 & R183pads at 1 of the pinsPlace resistor & capnear pin 6
Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1
Design Note:tss = Css x 0.6V/2uARamp rate ~990us
Cad Note:Place output caps near inductor
Design Note:Prefer 0603 size cap25V rated voltage is sufficient
3.3V logic signal
LTC3605C_FB
PGOOD_FPGA_1.5V
LTC3605C_SVIN
LTC3605C_INTVCC
LTC3605C_FB
LTC3605C_SW
LTC3605C_BOOST
LTC3605C_SS
LTC3605C_RT
LTC3605C_ITHLTC3605C_INTVCC
1.5V_FPGA_RUN LTC3605C_RUN
1.5V_REG_FPGA 1.5V_FPGA
3.3V
12V
3.3V
1.5V_FPGA_RUN 31
1.5V_FPGA_VDACP231
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
36 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
36 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
36 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R183 24.0K 1%
R182 DNI
C726
22uF
D28
CMDSH-3
C727
22uF
C666 2.2uF
R188
15K
1%
C638 1.0UF
C193 1200pF
C728
22uF
R571 100K
R572 215.0K
R187
10.0K
EXPOSED PAD
LTC3605EUFU46
RT1
PHMODE2
MODE3
FB4
TRACK/SS5
ITH6
RU
N7
PG
OO
D8
VO
N9
PG
ND
10
SW
11
SW
12
SW13
SW14
SW15
SW16
PVIN17
PVIN18
SV
IN19
BO
OS
T20
INT
VC
C21
SG
ND
22
CLK
OU
T23
CLK
IN24
PG
ND
25
C17122uF25V
1210
R573 0
R1970.003
C665
0.1UF
50V
C194
22uFC186
39pF
C688 3300pF
C16922uF25V
1210
R167169.0K
C689 33pF
L22
1.2uH
Isat = 11A
R574 10.0K
R168 10
C616
0.1uF
25V
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 3 - 2.5V FPGA
Design Note:DCR = 40m ohmsCAD Note:
Regulator input capsPlace near regulator controller
Design Note:DNI for ES device
Cad Note:1 overlapping pad
Design Note:Ith is tied to INTVCC forinternal compensation
CAD Note:Overlap R200 & R201pads at 1 of the pinsPlace resistor & capnear pin 6
Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1
Design Note:tss = Css x 0.6V/2uARamp rate ~990us
Cad Note:Place output caps near inductor
Design Note:Prefer 0603 size cap25V rated voltage is sufficient
LTC3605D_FB
PGOOD_FPGA_2.5V
LTC3605D_SVIN
LTC3605D_INTVCC
LTC3605D_FB
LTC3605D_SW
LTC3605D_BOOST
LTC3605D_SS
LTC3605D_RT
LTC3605D_ITHLTC3605D_INTVCC
2.5V_FPGA_RUN LTC3605D_RUN
2.5V_FPGA_FILT2.5V_FPGA
3.3V
12V
2.5V_FPGA2.5V_REG_FPGA
3.3V
2.5V_FPGA_RUN 31
2.5V_FPGA_VDACP031
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
37 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
37 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
37 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R589 215.0K
C773
0.1UF
50V
R201 47.5K 1%
R193 0.001
R199
137K
1%
D30
CMDSH-3
C787 10pF
R200 DNI
C772
22uF
C789 2.2uF
C788 3300pF
C202
39pF
C755
0.1uF
25V
C754
22uF
C18722uF25V
1210
L24
3A, 30 Ohm FB
C725
22uF
C207 560pF
R590 100K
EXPOSED PAD
LTC3605EUFU52
RT1
PHMODE2
MODE3
FB4
TRACK/SS5
ITH6
RU
N7
PG
OO
D8
VO
N9
PG
ND
10
SW
11
SW
12
SW13
SW14
SW15
SW16
PVIN17
PVIN18
SV
IN19
BO
OS
T20
INT
VC
C21
SG
ND
22
CLK
OU
T23
CLK
IN24
PG
ND
25
C18822uF25V
1210
C203
22uF
L23
1.2uH
Isat = 11A
R192 10
R198
15K
1%
C790 1.0UF
R596 0R202
4.70K, 1%
R597 10.0K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Cad Note:Place near INTVCC pin
Power 3 - 2.5V HPS
Design Note:DCR = 40m ohms
CAD Note:Regulator input capsPlace near regulator controller
Design Note:Ith is tied to INTVCC forinternal compensation
CAD Note:Overlap R179 & R180pads at 1 of the pinsPlace resistor & capnear pin 6
Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1
Design Note:tss = Css x 0.6V/2uARamp rate ~990us
Cad Note:Place output caps near inductor
Design Note:Prefer 0603 size cap25V rated voltage is sufficient
LTC3605E_FB
PGOOD_HPS_2.5V
RUN_2.5V_HPS
LTC3605E_SVIN
LTC3605E_INTVCC
LTC3605E_FB
LTC3605E_SW
LTC3605E_BOOST
LTC3605E_SS
LTC3605E_RT
LTC3605E_ITHLTC3605E_INTVCC
EN_2.5V_HPS
2.5V_HPS_FILT2.5V_HPS
3.3V
12V
2.5V_HPS2.5V_REG_HPS
3.3V
EN_2.5V_HPS 33
2.5_HPS_VDACP433
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
38 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
38 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
38 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R165 10
D29
CMDSH-3
R169
15K
1%
R166 0.001
R178
137K
1%
R554 0
C170
39pF
R553 178K1%
C663 2.2uF
R179 DNI
L20
1.2uH
Isat = 11A
C589
22uF
C615
0.1uF
25V
C661 10pF
R181
4.70K, 1%
C16422uF25V
1210
C664 1.0UF
C662 3300pF
EXPOSED PAD
LTC3605EUFU45
RT1
PHMODE2
MODE3
FB4
TRACK/SS5
ITH6
RU
N7
PG
OO
D8
VO
N9
PG
ND
10
SW
11
SW
12
SW13
SW14
SW15
SW16
PVIN17
PVIN18
SV
IN19
BO
OS
T20
INT
VC
C21
SG
ND
22
CLK
OU
T23
CLK
IN24
PG
ND
25
C16522uF25V
1210
R180 47.5K 1%
C660
22uF
C637
0.1UF
50V
C172
22uF
L19
3A, 30 Ohm FB
R549 100K
C183 560pF
R555 10.0K
C614
22uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 3 - 1.5V & 1.5V FPGA
CAD Note:Regulator input capsPlace near regulator controller
Design Note:Ith is tied to INTVCC forinternal compensation
CAD Note:Overlap R153 & R154pads at 1 of the pinsPlace resistor & capnear pin 6
Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1
Design Note:tss = Css x 0.6V/2uARamp rate ~990us
Cad Note:Place output caps near inductor
Design Note:Prefer 0603 size cap25V rated voltage is sufficient
PGOOD__HPS_1.5V
RUN_1.5V_HPS
LTC3605_SVIN
LTC3605_INTVCC
LTC3605_FB
LTC3605_FB
LTC3605_SW
LTC3605_BOOST
LTC3605_SS
LTC3605_RT
LTC3605_ITHLTC3605_INTVCC
EN_1.5V_HPS
1.5V_REG_HPS 1.5V_HPS
3.3V
12V
3.3V
EN_1.5V_HPS 33
1.5V_HPS_VDACP233
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
39 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
39 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
39 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C472 3300pFC528
22uF
C470 1.0UF
C510
0.1uF
25V
D27
CMDSH-3
C136 1200pF
C473 33pF
R519 10.0K
R155169.0K
R157
15K
1%
C511
22uF
C471 2.2uF
EXPOSED PAD
LTC3605EUFU40
RT1
PHMODE2
MODE3
FB4
TRACK/SS5
ITH6
RU
N7
PG
OO
D8
VO
N9
PG
ND
10
SW
11
SW
12
SW13
SW14
SW15
SW16
PVIN17
PVIN18
SV
IN19
BO
OS
T20
INT
VC
C21
SG
ND
22
CLK
OU
T23
CLK
IN24
PG
ND
25
C494
22uF
C15822uF25V
1210
C149
39pF
C15922uF25V
1210
R523 100K
R154 DNI
R152
10.0K
R153 24.0K 1%
L17
1.2uH
Isat = 11A
R520 0
C148
22uF
C493
0.1UF
50V
R521 215.0K
R1590.003
R163 10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Cad Note:Place near INTVCC pin
Power 3 - 3.3V HPS
CAD Note:Regulator input capsPlace near regulator controller
Design Note:Ith is tied to INTVCC forinternal compensation
CAD Note:Overlap R143 & R144pads at 1 of the pinsPlace resistor & capnear pin 6
Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1
Design Note:tss = Css x 0.6V/2uARamp rate ~990us
Cad Note:Place output caps near inductor
Design Note:Prefer 0603 size cap25V rated voltage is sufficient
3.3V logic signal
LTC3605A_FB
PGOOD_3.3V
RUN_3.3V_HPS
LTC3605A_SVIN
LTC3605A_INTVCC
LTC3605A_FB
LTC3605A_SW
LTC3605A_BOOST
LTC3605A_SS
LTC3605A_RT
LTC3605A_ITHLTC3605A_INTVCC
EN_3.3V_HPS
3.3V_HPS
3.3V_REG_HPS
3.3V
12V
3.3V
EN_3.3V_HPS 33
3.3_HPS_VDACP633
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
40 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
40 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
40 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C129
39pF
C11822uF25V
1210
R143 DNI
EXPOSED PAD
LTC3605EUFU33
RT1
PHMODE2
MODE3
FB4
TRACK/SS5
ITH6
RU
N7
PG
OO
D8
VO
N9
PG
ND
10
SW
11
SW
12
SW13
SW14
SW15
SW16
PVIN17
PVIN18
SV
IN19
BO
OS
T20
INT
VC
C21
SG
ND
22
CLK
OU
T23
CLK
IN24
PG
ND
25
C428 2.2uF
R144 69.8K 1%
C415
0.1UF
50V
C11922uF25V
1210
R510 10.0K
C137 220pF
C399
22uF
R134 10
C427 3300pFC391
22uF
C429 1.0UF
C131
22uF
C426 5pF
R138 0.001
R142
90.9K
1%
R508 66.5K
R506 100K
L16
1.2uH
Isat = 11A
D25
CMDSH-3
R509 0
C400
0.1uF
25V
R145
2.55K
1%
R137
11.5K
1%
C425
22uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - 1.15V_HPS, 5.0V, 1.8V
Fsw=1.7MHz
CAD Note:Regulator input capsPlace near regulator controller
Design Note:0.001 ohm sense resistorminimized IR drop @ 3A
CAD Note:Regulator input capsPlace near regulator controller
Design Note:Ith is tied to INTVCC forinternal compensation
CAD Note:Overlap R158 & R161pads at 1 of the pinsPlace resistor & capnear pin 6
Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1
Design Note:tss = Css x 0.6V/2uARamp rate ~990us
Cad Note:Place output caps near inductor
Design Note:Prefer 0603 size cap25V rated voltage is sufficient
CAD Note:Regulator input capsPlace near regulator controller
FB_5.0V
LTC3605B_SVIN
1.15V_HPS_INTVCC
1.15V_HPS_FB
1.15V_HPS_FB
PGOOD_1.1V_HPS
1.15V_HPS_SW
1.15V_HPS_BOOST
1.15V_HPS_SS
1.15V_HPS_ITH1.15V_HPS_INTVCC
EN_1.1V_HPS
1.15V_HPS_RT
RUN_1.15V_HPS
12V
5.0V
5.0V
1V8
1.1V_HPS
1.1V_REG_HPS
3.3V
12V
12V
3.3V
EN_1.1V_HPS 33
1.1V_HPS_VDACP033
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
41 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
41 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
41 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C76 22uF25V
R530 0
R529 100K
C6122uF25V
1210
D26
CMDSH-3
C59DNI
R161 10.0K
R151 10
C450
0.1uF
25V
D18DFLS2302 1
R80
52.3K
EXPOSED PAD
LTC3605EUFU39
RT1
PHMODE2
MODE3
FB4
TRACK/SS5
ITH6
RU
N7
PG
OO
D8
VO
N9
PG
ND
10
SW
11
SW
12
SW13
SW14
SW15
SW16
PVIN17
PVIN18
SV
IN19
BO
OS
T20
INT
VC
C21
SG
ND
22
CLK
OU
T23
CLK
IN24
PG
ND
25
C155
39pF
C51368pF
L32
6.5uHIsat = 6A
1 2
C558
22uF
C495
0.1UF
50V
R160
15K
1%
R79
10K
C5722uF25V
C14722uF25V
1210
C58 DNI
R162
13.7KR158 DNI
R164 0.001
C71
0.1uF
U10
LT3509EDE
VIN4
BOOST12
BOOST26
SW13
SW25
DA11
DA27
FB114
FB28
RUN/SS113
RUN/SS29
BD12
GND15
SYNC11
RT10
C474 1.0UF
R82
10K
C496 2.2uF
C70
0.1uF
L31
6.5uHIsat = 6A
1 2
R81 16.2K
C15747UF6.3V
C32422uF25V
1210
R534 10.0K
C13522uF25V
1210
R77
12.4K
C41622uF25V
1210
R156
316k
1%
D17 DFLS23021
C557
22uF
R535 215.0K
L18
1.2uH
Isat = 11A
C60
22uF4V
C512 1000pF
C1541.0nF
C41722uF25V
1210
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 4 - Linear Regulators
DDR3 FPGA VTT, VREFDDR3 HPS VTT, VREF
1.15V_GXB1.15V_VCCT
1.5V VCCD VCCH
DDR3 HPS VTT, VREF
VCCGXBVCCT
VCCDH
VCCT
VCCDH
VCCGXB
3.3V
VTT_FPGA_DDR3A
VREF_FPGA_DDR3A
1.5V_REG_FPGA
3.3V
VREF_HPS_DDR3
VTT_HPS_DDR3
1.5V_REG_HPS
2.5V_REG_FPGA
5.0V3.3V
1.15V_GXB
5.0V
1.15V_VCCT
3.3V
5.0V
1.5V_VCCD_VCCH
3.3V
1.15V_VCCTP1.15V_GXBP
1.5V_VCCD_VCCHP
3.3V
1.5V_REG_FPGA
VREF_FPGA_DDR3B
VTT_FPGA_DDR3B
3.3V
3.3V
3.3V
1.15V_GXB_RUN 32
1.5V_VCCD_VCCH_RUN
32
1.15V_GXB_VDACP032
1.15V_VCCT_VDACP232
1.5V_VCCD_VCCH_VDACP432
1.15V_VCCT_RUN
32
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
42 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
42 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
42 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R478
10.0K
C554
10uF
C451
10uF
C387
10uF
C206
2.2uF
C771
1.0nF
C88
10uF
C452
1.0nF
R1090
C7522uF
C722
10uF
C555
10uF
C729
10uF
C751
10uFU68
TPS51200
VIN10
EN7
PGOOD9
REFOUT6
GN
D_P
AD
11
PG
ND
4
GN
D8
VLDOIN2
REFIN1
VO3
VOSNS5
C359
10uF
C213
10uF
C782
1uF
U53
LTC3026
IN11
IN22
GN
D3
SW4
BST5
SHDN6
PG7ADJ8
OUT19OUT210
GN
D11
R467
10.0K
R1210
C348
0.1uF
R605 10.0K
R635215.0K
R227 10.0K
C367
10uF
C756
10uF
C101
2.2uF
C613
10uF
R456 10.0K
C667
10uF
R468 10.0K
C475
10uF
C100 1uF
R48210.0K
C78
10uFR106
0.003R457215.0K
C8922uF
U14
LTC3026
IN11
IN22
GN
D3
SW4
BST5
SHDN6
PG7ADJ8
OUT19OUT210
GN
D11
R2220
C655
10uF
R2160.003
C514
0.1uF
U73
TPS51200
VIN10
EN7
PGOOD9
REFOUT6
GN
D_P
AD
11
PG
ND
4
GN
D8
VLDOIN2
REFIN1
VO3
VOSNS5
R122
24.0K
1%
C617
10uF
C368
10uF
C477
1uF
C217 1uF
R466 10.0K
R1280.003
C430
10uF
R215
45.3K 1%
R110
4.99K
R52210.0KU69
TPS51200
VIN10
EN7
PGOOD9
REFOUT6
GN
D_P
AD
11
PG
ND
4
GN
D8
VLDOIN2
REFIN1
VO3
VOSNS5
C476
10uF
R524 10.0K
C781
0.1uF
C85 1uF
C770
10uF
R223
24.0K
1%
R516
10.0K
R588
10.0K
R123
45.3K 1%
C559
10uF
R477215.0K
C392
10uF
C20522uF
R58010.0K
U22
LTC3026
IN11
IN22
GN
D3
SW4
BST5
SHDN6
PG7ADJ8
OUT19OUT210
GN
D11
R10513.7K
C347
1uF
C358
1.0nF
C69
2.2uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 7 - Arria V ST Power
2.5V_FPGA
1.1V_HPS2.5V_FPGA_FILT
2.5V_VCCAUX_SHARED
2.5V_VCCAUX_SHARED2.5V_HPS
2.5V_HPS_FILT
1.1V_VCC
2.5V_FPGA_FILT
2.5V_HPS
2.5V_HPS_FILT
3.3V_HPS
3.3V_HPS
2.5V_HPS
1.15V_VCCP
1.5V_VCCD_VCCH
1.5V_VCCD_VCCH
1.1V_HPS
1.5V_HPS
1.5V_HPS
VREF_HPS_DDR3
1.15V_GXB
1.15V_GXB
1.5V_FPGA
2.5V_FPGA
VREF_FPGA_DDR3A
1.5V_FPGA
1.5V_FPGA
VREF_FPGA_DDR3B
2.5V_FPGA
VREF_FPGA_DDR3A
1.5V_FPGA
1.15V_VCCT
VREF_FPGA_DDR3B
VAR_VCCIO
VAR_VCCIO
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
43 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
43 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
43 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Arria V SX (SoC) HPS Power
5ASTFD5K3_F1517
U41T
VCCRSTCLK_HPSL10
VCCPLL_HPSU8
VCCPD7A_HPSR12
VCCPD6A6B_HPST8
VCCPD6A6B_HPSL9
VCCPD6A6B_HPST6
VCCPD6A6B_HPST10
VCCPD7E_HPSR18
VCCPD7B_HPST14
VCCPD7D_HPST17
VCCPD7C_HPSR16
VCC_HPSU14
VCC_HPSW12
VCC_HPSW14
VCC_HPSU12
VCC_HPSY13
VCC_HPSV16
VCC_HPSV13 VCC_HPSV12
VCC_HPSV10
VCC_HPSV15
VCC_HPST13
VCC_HPSV11
VCC_HPSU9
VCCIO6A_HPSA10
VCCIO6A_HPSC5
VCCIO6A_HPSC8
VCCIO6A_HPSF6
VCCIO6A_HPSF8
VCCIO6A_HPSJ6
VCCIO6A_HPSK8
VCCIO6A_HPSM8
VCCIO6A_HPSP9
VCCIO6B_HPSB3
VCCIO6B_HPSD4
VCCIO6B_HPSG3
VCCIO6B_HPSJ3
VCCIO6B_HPSL3
VCCIO6B_HPSN2
VCCIO6B_HPSN5
VCCIO7A_HPSB13
VCCIO7A_HPSE10
VCCIO7A_HPSG12
VCCIO7A_HPSK13
VCCIO7B_HPSE14
VCCIO7B_HPSJ15
VCCIO7C_HPSD17
VCCIO7D_HPSB18
VCCIO7D_HPSG17
VCCIO7E_HPSJ20
VREFB6AN0_HPSP10
VREFB6BN0_HPSM4
VREFB7A7B7C7D7EN0_HPSP18
VCCRSTCLK_HPSJ10
Arria V SX (SoC) Power
5ASTFD5K3_F1517
U41J
VCCAA10
VCCAA12
VCCAA14
VCCAA16
VCCAA18
VCCAA20
VCCAA22
VCCAA24
VCCAA26
VCCAB11
VCCAB17
VCCU18
VCCV17
VCCV22
VCCPD3AA28VCCPD3AA27
VCCPD4AAC10
VCCPD3AB30VCCPD3AB24VCCPD3AB23VCCPD3AB22
VCCPD4BCDAB12
VCCPD4AAE10
VCCPD4BCDAB16VCCPD4BCDAB13
VCCA_FPLLAC9VCCA_FPLLAC30VCCA_FPLLAB21VCCA_FPLLAA9
VCCA_FPLLV20
VCCA_FPLLV31
VCCY19 VCCY17 VCCY15 VCCY11 VCCW28 VCCW26 VCCW24 VCCW22 VCCW20 VCCW18 VCCV29 VCCV23
VCCPD4BCDAB18
VCCPD8R32
VCCPD8T30
VCCPD8U22
VCCPD8U24
VCCPD8U26
VCCBATR33
VCCPGMAG29
VCCPGMJ19
VCC_AUXAB14
VCC_AUXAB26
VCC_AUXU28
VCC_AUX_SHAREDU15
VCCY21
VCCY29 VCCY25 VCCY23
VCCA_FPLLY30
VCCPD8U29
VCCPD7FGU21
VCCPD4BCDAB19
VCCPD3AA29
VCCD_FPLLAB20
VCCD_FPLLAD31
VCCD_FPLLAE9
VCCD_FPLLT31
VCCD_FPLLV19
VCCD_FPLLW30
VCCD_FPLLW9
Arria V SX (SoC)TransceiverPower
5ASTFD5K3_F1517
U41L
VCCA_GXBL0AF33
VCCA_GXBL1AB33
VCCA_GXBL2V33
VCCA_GXBR0AE7
VCCL_GXBL0AD34
VCCA_GXBR1AA7
VCCH_GXBL0AD33
VCCL_GXBL2T34VCCL_GXBL1Y35VCCL_GXBL1Y34VCCL_GXBL0AD35
VCCPAA25
VCCPV25 VCCPU16
VCCPY27 VCCPW10
VCCPU10
VCCPAA21
VCCPV27
VCCPAB15
VCCH_GXBR0AC7
VCCH_GXBR1W7
VCCH_GXBL1Y33
VCCH_GXBL2T33
VCCL_GXBR1W5
VCCL_GXBR1W6
VCCL_GXBR0AC6VCCL_GXBR0AC5VCCL_GXBL2T35
VCCR_GXBLAA34
VCCR_GXBLAB35
VCCR_GXBLAC35
VCCR_GXBLAE34
VCCR_GXBLAF35
VCCR_GXBLU34
VCCR_GXBLW34
VCCR_GXBRAA5
VCCR_GXBRAB5
VCCR_GXBRAB6
VCCR_GXBRV5
VCCR_GXBRV6
VCCR_GXBRY6
VCCT_GXBL0AG34
VCCT_GXBL0AG35
VCCT_GXBL1V35
VCCT_GXBL1W35
VCCT_GXBL2AC34
VCCT_GXBL2R35
VCCT_GXBR0AD6
VCCT_GXBR0AE5
VCCT_GXBR1AF5
VCCT_GXBR1AF6
Arria V SX (SoC) Power
5ASTFD5K3_F1517
U41K
VCCIO3AAH29
VCCIO3AAJ30
VCCIO3AAK35
VCCIO3AAM30
VCCIO3AAT35
VCCIO3BAK28
VCCIO3BAL27
VCCIO3BAN28
VCCIO3CAJ24
VCCIO3CAM24
VCCIO3CAR24VCCIO3CAU25
VCCIO3DAJ22
VCCIO3DAM22VCCIO3DAP21VCCIO3DAR22VCCIO3DAU21
VCCIO4AAN5
VCCIO4AAL5
VCCIO4AAJ5
VCCIO4BAM12
VCCIO4BAK13
VCCIO4DAM19
VCCIO4DAJ19
VCCIO4CAV15VCCIO4CAR15VCCIO4CAM15VCCIO4CAJ15
VCCIO4BAT10
VCCIO4BAR12
VCCIO4BAN13
VCCIO3AAP35
VCCIO3CAL25
VCCIO3BAT28
VCCIO3DAL21
VCCIO4AAR5
VCCIO4DAK18
VCCIO4AAG10
VCCIO4AAU5
VCCIO4BAN10
VCCIO4DAN18
VCCIO3CAP25
VCCIO4DAR19
VCCIO4DAT18
VCCIO7GK19
VCCIO8AB35
VCCIO8AG31
VCCIO8AG33
VCCIO8AK31
VCCIO8AK33
VCCIO8AP33
VCCIO8BE28
VCCIO8BE30
VCCIO8BH30
VCCIO8BK28
VCCIO8CC25
VCCIO8CD27
VCCIO8CF25
VCCIO8CG27
VCCIO8CJ25
VCCIO8CM24
VCCIO8DC21
VCCIO8DD22
VCCIO8DF21
VCCIO8DG22
VCCIO8DK22
VCCIO8DM21
VREFB3AN0AJ31
VREFB3BN0AL28
VREFB3CN0AK26
VREFB3DN0AJ21
VREFB4AN0AH7
VREFB4BN0AN11
VREFB4CN0AG15
VREFB4DN0AF18
VREFB7GN0P19
VREFB8AN0H33
VREFB8BN0R31
VREFB8CN0L25
VREFB8DN0H22
L36
3A, 30 Ohm FB
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 8 - Arria V ST Ground
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
44 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
44 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
44 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Arria V SX(SoC) GND
5ASTFD5K3_F1517
U41H
GNDA12
GNDAA11
GNDAA13
GNDAA15
GNDAA17
GNDAA19
GNDAA23
GNDAA3
GNDAA30
GNDAA33
GNDAA35
GNDAA38
GNDAA39
GNDAA4
GNDAA6
GNDAA8
GNDAB1
GNDAB10
GNDAB2
GNDAB31
GNDAB32
GNDAB34
GNDAB36
GNDAB37
GNDAB7
GNDAC11
GNDAC14
GNDAC17
GNDAC20
GNDAC23
GNDAC26
GNDAC28
GNDAC3
GNDAC33
GNDAC38
GNDAC39
GNDAC4
GNDAC8
GNDAD1
GNDAD10
GNDAD2
GNDAD30
GNDAD32
GNDAD36
GNDAD37
GNDAD5
GNDAD7
GNDAE3
GNDAE30
GNDAE33
GNDAE35
GNDAE38
GNDAE39
GNDAE4
GNDAE6
GNDAE8
GNDAF1
GNDAF20
GNDAF23
GNDAF26
GNDAF29
GNDAF30
GNDAF31
GNDAF32
GNDAF34
GNDAF36
GNDAF37
GNDAF9
GNDAG3
GNDAG31
GNDAG38
GNDAG39
GNDAG4
GNDAG5
GNDAG6
GNDAG7
GNDAG8
GNDAG9
GNDAH1
GNDAH2
GNDAH32
GNDAH34
GNDAH35
GNDAH36
GNDAH37
GNDAH5
GNDAJ11
GNDAJ14
GNDAJ17
GNDAJ20
GNDAJ23
GNDAJ26
GNDAJ29
GNDAJ3
GNDAJ38
GNDAK5GNDAK37
GNDAJ8
GNDAJ39
GNDAJ32
GNDAJ35
GNDAK2
GNDAL3
GNDAK36
GNDAK1
GNDAL35
GNDAJ4
GNDAH33
GNDAL4
GNDAM1
GNDAL39GNDAL38
GNDAM14GNDAM11
GNDAF14 GNDAF11
GNDAF17 GND
AM2
GNDAM20
GNDAM17
GNDAF2
GNDAM23
Arria V SX(SoC) GND
5ASTFD5K3_F1517
U41I
GNDAM26
GNDAM29
GNDAM32
GNDAM36
GNDAM37
GNDAM5
GNDAM8
GNDAN3
GNDAN35
GNDAN38
GNDAN39
GNDAN4
GNDAP1
GNDAP2
GNDAP36
GNDAP37
GNDAP5
GNDAR11
GNDAR14
GNDAR17
GNDAR20
GNDAR23
GNDAR26
GNDAR29
GNDAR3
GNDAR32
GNDAR35
GNDAR38
GNDAR39
GNDAR4
GNDAR8
GNDAT1
GNDAT2
GNDAT36
GNDAT37
GNDAT5
GNDAU3
GNDAU35
GNDAU38
GNDAU39
GNDAU4
GNDAV1
GNDAV11
GNDAV14
GNDAV17
GNDAV2
GNDAV20
GNDAV23
GNDAV26
GNDAV29
GNDAV32
GNDAV35
GNDAV36
GNDAV37
GNDAV38
GNDAV39
GNDAV5
GNDB16
GNDB2
GNDB20
GNDB23
GNDB26
GNDB29
GNDB32
GNDB36
GNDB37
GNDB5
GNDB8
GNDC11
GNDC35
GNDC38
GNDC39
GNDD36
GNDD37
GNDE11
GNDE17
GNDE2
GNDE20
GNDE23
GNDE26
GNDE29
GNDE35
GNDE38
GNDE39
GNDE5
GNDE8
GNDF14
GNDF36
GNDF37
GNDG35
GNDG38
GNDG39
GNDH11
GNDH17
GNDH23
GNDJ14GNDH8
GNDH32
GNDH26
GNDH2
GNDH20
GNDH37
GNDJ35
GNDH5
GNDH36
GNDJ38
GNDH29
GNDE32
GNDK36
GNDK37
GNDK20GNDJ39
GNDL17GNDL11
GNDAW35 GND
AV8
GNDAW38 GND
L23
GNDL26
GNDL2
GNDB11
GNDL29
Arria V SX(SoC) GND
5ASTFD5K3_F1517
U41S
GNDL32
GNDL35
GNDL38
GNDL39
GNDL5
GNDL8
GNDM11
GNDM36
GNDM37
GNDN14
GNDN17
GNDN20
GNDN3
GNDN35
GNDN38
GNDN39
GNDN4
GNDP1
GNDP11
GNDP2
GNDP23
GNDP26
GNDP29
GNDP32
GNDP35
GNDP36
GNDP37
GNDP5
GNDP8
GNDR3
GNDR34
GNDR38
GNDR39
GNDR4
GNDR5
GNDT1
GNDT12
GNDT15
GNDT16
GNDT18
GNDT2
GNDT20
GNDT32
GNDT36
GNDT37
GNDT5
GNDT9
GNDU11
GNDU13
GNDU17
GNDU23
GNDU25
GNDU27
GNDU3
GNDU30
GNDU33
GNDU35
GNDU38
GNDU39
GNDU4
GNDU5
GNDU6
GNDU7
GNDV1
GNDV14
GNDV18
GNDV2
GNDV21
GNDV24
GNDV26
GNDV28
GNDV30
GNDV32
GNDV34
GNDV36
GNDV37
GNDV7
GNDV8
GNDV9
GNDW11
GNDW13
GNDW16
GNDW17
GNDW19
GNDW21
GNDW23
GNDW25
GNDW27
GNDW29
GNDW3
GNDW33
GNDW38
GNDW39
GNDW4
GNDY10
GNDY24GNDY22
GNDY16
GNDY12
GNDW8
GNDY1
GNDY2
GNDY26
GNDY20
GNDY18
GNDY28
GNDY14
GNDW15
GNDY36
GNDY37
GNDY32GNDY31
GNDY7GNDY5
DNU2AE20 DNU1
A38
DNU3AH31 DNU6
B12
DNU7B38
DNU5AW3
DNU4AV3
DNU8F20
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Decoupling1.15V_vcc
1.15V_vccp
1.5V_vccio
2.5V_hps
3.3v_HPS
1.5V_hps
2.5V_fpga
2.5V_fpga_filt
2.5V_HPS_FILT
1.15V_hps
VAR_VCCIO1.5V_VCCD_VCCH1.15V_GXB
1.15V_VCCT
1.15V_VCCP1.1V_VCC
1.5V_FPGA
1.1V_HPS
2.5V_HPS_FILT
3.3V_HPS
2.5V_HPS
2.5V_FPGA_FILT
2.5V_FPGA
1.5V_HPS
2.5V_VCCAUX_SHARED
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
45 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
45 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C1
Arria V SoC FPGA Development Kit Board
B
45 45Thursday, December 12, 2013
150-0320807-C1 (6XX-44209R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C699
0.1uF
C605
0.01uF
C711
100uF6.3V
C743
2.2uF
C444
4.7nF
C627
4.7nF
C515
22nF
C767
100uF6.3V
C542
22nF
C577
22nF
C646
0.22uF
C410
0.1uF
STANDOFF3
C520
22nFC629
47nF
C763
100uF6.3V
STANDOFF1
C567
22nF
C434
4.7nF
C765
100uF6.3V
C398
10uF
C446
0.01uF
C421
0.1uF
C648
4.7nF
C394
100uF6.3V
C534
2.2uF
C543
22nF
C563
0.47uF
C438
4.7nF
C407
0.1uF
C668
100uF6.3V
C437
4.7nF
C582
22nF
C640
47nF
C575
0.22uF
C505
22nF
C508
22nF
C436
47nF
C501
0.01uF
C441
0.01uF
C469
4.7nF
C621
0.01uF
C620
47nF
C698
0.22uF
C583
4.7uF
C600
22nF
C573
22nF
C439
4.7nF
C597
4.7uF
SCREW4
C596
100uF6.3V
C624
4.7nF
SPACER2
C562
22nF
C498
100uF6.3V
C740
10uF
C679
0.01uF
C538
4.7nF
C479
47nF
C466
4.7nF
C703
47nF
C447
0.01uF
C649
0.01uF
C419
100uF6.3V
SPACER1
C535
22nF
C633
100uF6.3V
C618
4.7uF
C609
22nF
C738
0.1uF
C716
0.47uF
C518
47nF
STANDOFF5
C414
0.47uF
C735
0.1uF
C733
0.47uF
C485
0.01uF
C704
0.1uF
C482
4.7nF
STANDOFF2
C598
22nF
C546
22nF
C462
47nF
SCREW1
PCB1
C745
100uF6.3V
C442
1uF
C522
0.1uF
C776
330uF2.5V
C732
1uF
C569
4.7nF
C420
100uF6.3V
C580
22nF
C478
47nF
C581
22nF
C539
47nF
C639
47nF
C506
22nF
C644
22nF
C459
100uF6.3V
C601
47nF
C500
47nF
C672
0.22uF
C647
4.7nF
C678
0.47uF
C480
0.01uF
C706
4.7nF
C746
4.7uF
C739
0.1uF
C734
0.1uF
C481
4.7nF
C412
0.22uF
C393
100uF6.3V
C670
47nF
C737
0.1uF
C645
22nFC606
0.1uFC547
2.2uF
C642
47nF
C440
4.7nF
C626
4.7nF
C443
22nF
C625
22nF
C503
22nF
C619
47nF
C701
4.7nF
C576
22nF
C517
4.7nF
C519
22nF
C537
0.01uF
C435
4.7nF
C631
47nF
STANDOFF6
C445
4.7nF
C422
0.1uF
C673
22nF
C632
4.7nF
C766
100uF6.3V
C696
0.22uF
C521
22nF
SCREW3
C731
0.22uF
C484
0.01uF
C643
0.01uF
C578
22nF
C568
4.7nF
C574
22nF
C499
47nF
C599
22nF
C641
0.01uF
C747
100uF6.3V
C705
0.01uF
C697
4.7nF
C408
0.1uF
C561
22nF
C465
0.01uF
C680
47nF
C715
0.47uF
C433
47nF
C463
47nF
C464
4.7nF
C460
4.7uF
C775
100uF6.3V
C676
0.01uF
C630
22nF
C608
1uF
C483
4.7nF
C607
47nF
C570
0.47uF
C671
47nF
C604
47nF
C622
0.01uF
C764
100uF6.3V
C467
4.7nF
C702
47nF
C579
22nF
C432
0.1uF
C700
0.01uF
C674
22nF
C623
22nF
C397
100uF6.3V
C741
0.47uF
C677
22nF
C603
0.01uF
SCREW2
C497
100uF6.3V
C713
0.22uF
C544
47nF
C516
22nF
C675
0.22uF
C540
4.7nF
C541
22nF
C411
1uF
C736
0.22uF
C545
22nF
C409
0.22uF
C669
100uF6.3V
C507
0.47uF
C413
0.22uF
C744
4.7uF
C406
0.47uF
C681
100uF6.3V
C565
47nF
C523
22nF
C502
0.1uF
C742
0.22uF SCREW7SCREW6
C564
4.7nF
C524
47nF
C536
22nF
C695
0.22uF
C628
4.7nF
C714
0.22uF
SCREW5C525
10uF
C602
4.7nF
C468
22nF
C566
22nF
SCREW8
STANDOFF4
C504
22nF
C396
2.2uF
C461
47nF
C707
0.1uF
C768
0.22uF
C712
4.7uF
C650
0.1uF
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