ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU CH9 Multiplexers, Decoders, and CH9 Multiplexers, Decoders, and Programmable Logic Devices Programmable Logic Devices Lecturer:吳安宇 教授 Date:2006/11/10 V2.0
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Graduate Institute of Electronics Engineering, NTU
CH9 Multiplexers, Decoders, and CH9 Multiplexers, Decoders, and Programmable Logic DevicesProgrammable Logic Devices
Lecturer:吳安宇 教授
Date:2006/11/10V2.0
Graduate Institute of Electronics Engineering, NTU
pp. 2
GoogolplexGoogolplexGoogolplex (From Wikipedia)Googolplex is the number,
It can also be written as 10googol, or as a 1 followed by a googol (10100) zeroes
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pp. 3
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays
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pp. 4
Integrated Circuits (IC)Integrated Circuits (IC)
Small-Scale Integrated circuit (SSI):
Medium-Scale IC (MSI)
Large-Scale IC (LSI) : Arithmetic-Logic Unit (ALU)
Very Large-Scale IC (VLSI)
NORNANDNOTXORMultiplexer
Decoder
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pp. 5
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays
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pp. 6
Multiplexers(1/2)Multiplexers(1/2)
I0A B Z0 0 I00 1 I11 0 I21 1 I3
ZI1I2I3
A B
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pp. 7
Multiplexers(2/2)Multiplexers(2/2)Z = A’B’I0 + A’BI1 + AB’I2 + ABI3
= m0I0 + m1I1 + m2I2 + m3I3 ( mi : Minterm )
A B
I0
I1
I2
I3
z
AND-OR Network
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pp. 8
General 2General 2nn--toto--1 Multiplexer1 Multiplexer
2n-to-1Mux
Z
2n
DataLines
n control Inputs
∑−
=
=12
0
n
kkk Imz
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pp. 9
Application: Application: 4-bit Word Selector
sel
A B
C
A= ( a3a2a1a0 )B= ( b3b2b1b0 )
C= ( c3c2c1c0 )
Sel C
01
AB
sel 2-to-1
a3 b3
c3
2-to-1
a2 b2
c2
2-to-1
a1 b1
c1
2-to-1
a0 b0
c0
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pp. 10
Realize Combinational Logic FunctionRealize Combinational Logic Function
)0'('''1)'(''''⋅+++⋅=
++=+=BAABCCABBABBACBAACBAF
0 0 1 0 1 1 0 1
1C0C
I0I1
I3
I2Z=A’B’+AC
A B
A B Z
0 00 11 01 1
1C0C
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pp. 11
Other Examples (skipped)Other Examples (skipped)Use 8-to-1 Mux to Realize F=A’B’ + AC
1
A B C
I0
I5I6I7
I2I3I4
I1
8-to-1MUX
1 0 1 1
1 0 0 0
1 1 0 1
0 1 1 0
00 01 11 10AB
CD00011110
ABC = 001 ABC = 101
ABC = 000
1
0
D1
D010 ZD’I1=D
1
0
D0
D
D’D’
1
I6=D’
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pp. 12
Other Examples (skipped)Other Examples (skipped)
Use 8Use 8--toto--1 1 MuxMux to Realize F(A,B,C,Dto Realize F(A,B,C,D))A B C Z
0123
0 0 00 0 10 1 00 1 1
1D01
4567
1 0 01 0 11 1 01 1 1
D’DD’D’
F = A’B’C’ + B’CD + A’BC + A’BC + AC’D’(From K-map)
A B C Z
0123
0 0 00 0 10 1 00 1 1
C’1CC
4567
1 0 01 0 11 1 01 1 1
C’C10
1 0 1 1
1 0 0 0
1 1 0 1
0 1 1 0
AB
CD00011110
00 01 11 10
I0=C’ I1=1I2=C I3=CI4=C’ I5=CI6=1 I7=0
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pp. 13
44--toto--1 Mux to Realize 1 Mux to Realize F(A,B,C,D)F(A,B,C,D)
C D I1
0 0 0
0 1 0
1 1 1
1 0 1
C D I1
0 0 1
0 1 0
1 1 1
1 0 0
C D I1
0 0 1
0 1 0
1 1 0
1 0 1
1 0 1 1
1 0 0 0
1 1 0 1
0 1 1 0
AB
00011110
CD 00 01 11 10C D I10 0 10 1 11 1 11 0 0
I0I1I2I3
''''
')'(
3
2
1
0
DIDCCDDCI
CIDCCDI
=⊕=+=
=+==
ZC
C’DC’D
D’
A B
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pp. 14
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State (Tri-state) Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays
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pp. 15
ThreeThree--state (tristate (tri--state) Buffer(1/3)state) Buffer(1/3)
F C
F = C Buffer Gate
F C
Invert pairsGate Circuit with added Buffer(for driving capability)
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pp. 16
ThreeThree--state Buffer(2/3)state Buffer(2/3)
B = 1, C=A0, Open circuit
(High-impedance)
B A C
0 0 Z
0 1 Z
1 1 1
1 0 0
B A C
0 0 1
0 1 0
1 1 Z
1 0 Z
B A C
0 0 Z
0 1 Z
1 1 1
1 0 1
B A C
0 0 0
0 1 1
1 1 Z
1 0 Z
Operations of tri-state buffers
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pp. 17
ThreeThree--state Buffer(3/3)state Buffer(3/3)
S1 x 0 1 zx01z
x x x xx 0 x 0x x 1 1x 0 1 z
Outputs of both Tri-state buffers
S2
(B,D are independent)
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pp. 18
Application of TriApplication of Tri--state Buffersstate Buffers
Bus structure:Multiple I/O on a Busfor communication
{EnA, EnB, EnC, EnD} should be exclusive ( Only 1 active )
Bi-directional I/O pinBi-directional means that the same pin can be used as can input pin and as an output pin, but not both at the same time
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pp. 19
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays
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pp. 20
33--toto--8 Decoder (MSI)8 Decoder (MSI)
a b c y0 y1 y2 y3 y4 y5 y6 y7
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
1 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1
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pp. 21
Realization of a Decoder (MSI 7442)Realization of a Decoder (MSI 7442)BCD input Decimal Output
A B C D 0 1 2 3 4 5 6 7 8 9
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(a) Logic Diagram
(c) Truth table
(b) Block Diagram
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pp. 22
An nAn n--toto--22nn Decoder generate 2Decoder generate 2n n mintermsminterms
1
1
2 to0 ,)'(
2 to0 ,−
−
===
==n
iii
nii
iMmy
imy(Inverted outputs)
(non-Inverted outputs)
)9,7,4(),,,()4,2,1(),,,(
9742
4211
mmmmdcbafmmmmdcbaf
∑=++=∑=++=
Ex:
)''''()''''(
9742
4211
mmmfmmmf⋅⋅=⋅⋅= (NAND)
(NAND)
Using MSI 7442 (BCD input decoder)
Note: M > 10 is not allowed!!
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pp. 23
Priority Encoders (8Priority Encoders (8--toto--3)3)
y0 y1 y2 y3 y4 y5 y6 y7 a b c d0 0 0 00 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0x 1 0 0 0 0 0 0x x 1 0 0 0 0 0x x x 1 0 0 0 0x x x x 1 0 0 0x x x x x 1 0 0
0 1 0 10 1 1 11 0 0 1
0 0 0 10 0 1 1
1 1 0 11 1 1 1
1 0 1 1
x x x x x x x 1x x x x x x 1 0
No signal
happen
Event detect with priority!
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pp. 24
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays
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pp. 25
ReadRead--only Memory (ROM)only Memory (ROM)
An 8-word x 4-Bit ROM: each word is 4-bit, total 8 words in this ROM
A B C F0 F1 F2 F3
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
1 0 1 01 0 1 00 1 1 10 1 0 11 1 0 00 0 0 11 1 1 10 1 0 1
Input (ABC)=23 input values (0~7 address)Output(F0 F1 F2 F3 )=(word)
typical datastored in ROM(2n words of 4 bits each)
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pp. 26
Generalized Form ( Generalized Form ( nn--inputs/minputs/m--outputsoutputs ))
n-bit input address
m-bit Output data
00…0000…0100…1000…11
11…0011…0111…1011…11
100…110010…111101…101110…010
001…011110…110011…000111…101
typical dataarray storedin ROM(2n words, each m-bits)
Size = m x 2n (bits)
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pp. 27
Basic ROM Structure Basic ROM Structure (A Decoder + Memory Array)(1/2)(A Decoder + Memory Array)(1/2)
Figure 9-19Basic ROM Structure
2n entriesM output lines
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pp. 28
Basic ROM Structure (2/2)Basic ROM Structure (2/2)
F0 F1 F2 F3
0123
1 0 1 01 0 1 00 1 1 10 1 0 1
4567
1 1 0 00 0 0 11 1 1 10 1 0 1
BACmFBCBAmFACBmFACBAmF
+=∑=+=∑=+=∑=+=∑=
)7,6,5,3,2(''')6,2,1,0(')7,6,4,3,2(''')6,4,1,0(
3
2
1
0
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pp. 29
Contents of ROM specifies a Contents of ROM specifies a ““TRUTH TABLETRUTH TABLE””
InputW X Y Z
HexDigit
ASCII Code for Hex DigitA6 A5 A4 A3 A2 A1 A0
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0123456789ABCDEF
0 1 1 0 0 0 00 1 1 0 0 0 10 1 1 0 0 1 00 1 1 0 0 1 10 1 1 0 1 0 00 1 1 0 1 0 10 1 1 0 1 1 00 1 1 0 1 1 10 1 1 1 0 0 00 1 1 1 0 0 11 0 0 0 0 0 11 0 0 0 0 1 01 0 0 0 0 1 11 0 0 0 1 0 01 0 0 0 1 0 11 0 0 0 1 1 0
invert Same
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pp. 30
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays
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pp. 31
Different Types of ROMDifferent Types of ROMMask-programmable ROM (manufactured)Programmable ROM(PROM) - Program onceElectrically Erasable Programmable ROM(EE-PROM)
Programmable Logic Device (PLD)N-by-m PLD
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pp. 32
Programmable Logic Array (PLA) (1/2)Programmable Logic Array (PLA) (1/2)AND plane generates minterm (Product terms)OR plane sums the product terms
Product Term
InputsA B C
OutputsF0 F1 F2 F3
A’B’AC’BBC’AC
0 0 -1 - 0- 1 -- 1 01 - 1
1 0 1 01 1 0 00 1 0 10 0 1 00 0 0 1
.
ACBFBCBAF
BACFACBAF
+=+=+=+=
3
2
1
0
''''
'''
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pp. 33
)15,14,13,9,8,7,6()15,14,11,10,7,6,5,3,2(
)15,13,11,10,9,8,7,5,3,2(
3
2
1
mfmfmf
∑=∑=∑=
abdcabbcfbdacf
cbcababdbdaf
++=+=
++++=
'''
''''
3
2
1
a b c d f1 f2 f3a’bdabdab’c’b’ccbc
0 1 – 11 1 – 11 0 0 –– 0 1 –– – 1 –– 1 1 –
1 1 01 0 11 0 11 0 00 1 00 0 1
Programmable Logic Array (PLA) (2/2)Programmable Logic Array (PLA) (2/2)
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pp. 34
Programmable Array Logic (PAL)Programmable Array Logic (PAL)
(1) Notation
(2) Fixed product terms
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pp. 35
PAL : Fixed OR arrayPAL : Fixed OR array
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pp. 36
Implementation of Full Adder using PALImplementation of Full Adder using PAL
X Y Cin Sum Cout
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 01 01 00 11 00 10 11 1
XYYCinXCinCoutXYCinCinXYYCinXCinYXSum
++=+++= ''''''
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pp. 37
Programmable Array Logic (PAL)Programmable Array Logic (PAL)
Programmable array logic (PAL) device Standard PAL representation
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pp. 38
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices
(not in Exam!)9.8 Field Programmable Gate Arrays
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pp. 39
Complex Programmable Logic Device Complex Programmable Logic Device (CPLD)(CPLD)
Tools will program for you
Architecture of Xilinx XCR3064XL CPLD
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pp. 40
CPLD Function Block and CPLD Function Block and MacrocellMacrocell
(a Simplified Version of XCR3064XL)
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pp. 41
OutlineOutline9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field Programmable Gate Arrays (NOT in Exam!)
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pp. 42
Field Programmable Gate Arrays Field Programmable Gate Arrays (FPGA)(FPGA)
Layout of a Typical FPGA
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pp. 43
Simplified Configurable Logic Block (CLB)Simplified Configurable Logic Block (CLB)
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pp. 44
Implementation of a Lookup Table Implementation of a Lookup Table (LUT)(LUT)
a b c d F
0 0 0 00 0 0 0
1 1 1 1
01
1
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pp. 45
(9.8) Decomposition of Switching (9.8) Decomposition of Switching Function (Function (in Examin Exam))
Purpose: Reduce input variablesf(a,b,c,d) = a’f(b,c,d) + af(b,c,d) = af1 + a’f0
Ex: f(a,b,c,d) = c’d’+a’b’c+bcd+ac’=c’d’(a+a’) + a’b’c + bcd(a+a’)+ ac’=a’(c’d’+b’c+bcd) + a(c’d’+bcd+c’)=a’(c’d’+b’c+cd) + a(c’+bd)=a’f0 + af1
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pp. 46
KK--map approachmap approacha=0, f0 = c’d’ + b’c + cda=1, f1 = c’ + bd
1 1 1 1
0 0 1 1
1 1 1 0
1 0 0 0
00 01 11 10
1 1 1 1
0 0 1 1
1 1 1 0
1 0 0 0
00 01 11 10ab
cd00011110
F0 F1
a=0 a=1ab
cd00011110
F
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pp. 47
Generalized expressionGeneralized expression
10
1121
1121
1121
'),,,1,,,,(
),,,0,,,,('),,,,,,,(
fxfxxxxxxfx
xxxxxfxxxxxxxf
ii
niii
niii
niii
+=+=
+−
+−
+−
LL
LL
LL
Input variables Reduces from n to (n-1)
onefunction
twofunctions
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pp. 48
Ex: 5Ex: 5--variable Functionvariable Function
10'),,,,1(),,,,0('),,,,(
fafaedcbafedcbfaedcbaf
⋅+⋅=+=
Two 4-variable functions+ 2-to-1 Mux(controlled by a)
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pp. 49
Ex: 6Ex: 6--Variable FunctionVariable Function
10'),,,,,1(),,,,,0('),,,,,(
GaGafedcbaffedcbfafedcbaG
⋅+⋅=+=
0100
0
'),,,,1,0(),,,,0,0('
GGbfedcbGfedcGbG
+=+=
1110
1
'),,,,1,1(),,,,0,1('
bGGbfedcbGfedcGbG
+=+=
11100100 '''' abGGabbGaGbaG +++= Four 4-variablefunctions+3 2-to-1 mux